coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

mingw build problem with seabios/tools/kconfig
by Scott Duplichan 01 Apr '11

01 Apr '11

Hello, I am trying to overcome problems building seabios/tools/kconfig from the windows/mingw environment. Here are the failures: 1) Link step for tools/kconfig/conf fails to find regcomp/regexec/regfree. In the mingw environment these functions are available in libregex, but libregex is not included in the standard library search. I have not found a way to add '-lregex' to the link command line: $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) HOSTLDFLAGS occurs too early in the file list for this use. 2) Link step for tools/kconfig/conf fails to find function uname(). I can come up with a library to provide this function but need help passing it to the linker, same as with item 1. 3) Function mkdir() takes only one argument in the mingw environment, yet takes 2 arguments otherwise. I have not found a good way to overcome this difference. Thanks, Scott

5 12

[PATCH] Add build instructions for coreinfo in readme
by Hamo 31 Mar '11

31 Mar '11

Add build instructions for coreinfo, specially pointing out installing gcc-multilib on a 64bit system. Signed-off-by: Yang Hamo Bai <hamo.by(a)gmail.com> This is the very first time I send a patch to coreboot, any comment is welcome. Thanks.

2 2

[PATCH] FILO: Add NAND support for HY27UF081G2A
by Nathan Williams 31 Mar '11

31 Mar '11

This patch adds the device id for the Hynix HY27UF081G2A 128MB NAND flash IC. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Index: lxflash.c =================================================================== --- lxflash.c (revision 142) +++ lxflash.c (working copy) @@ -586,6 +586,7 @@ break; case ST_NAND_128MB: + case HY_NAND_128MB: g_flashInfo.numBlocks = 1024; g_flashInfo.pagesPerBlock = 64; Index: lxflash.h =================================================================== --- lxflash.h (revision 142) +++ lxflash.h (working copy) @@ -140,6 +140,7 @@ #define ST_NAND_64MB 0x76207620 #define ST_NAND_512MB 0x9580dc20 #define ST_NAND_128MB 0x1d80f120 +#define HY_NAND_128MB 0x1d80f1ad #define ERROR_SUCCESS 0 #define ERROR_BAD_PARAMS -1

2 1

[FILO] r143 - trunk/filo/drivers/flash
by repository service 31 Mar '11

31 Mar '11

Author: stepan Date: Thu Mar 31 23:26:40 2011 New Revision: 143 URL: http://tracker.coreboot.org/trac/filo/changeset/143 Log: This patch adds the device id for the Hynix HY27UF081G2A 128MB NAND flash IC. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/filo/drivers/flash/lxflash.c trunk/filo/drivers/flash/lxflash.h Modified: trunk/filo/drivers/flash/lxflash.c ============================================================================== --- trunk/filo/drivers/flash/lxflash.c Fri Feb 25 21:35:07 2011 (r142) +++ trunk/filo/drivers/flash/lxflash.c Thu Mar 31 23:26:40 2011 (r143) @@ -586,6 +586,7 @@ break; case ST_NAND_128MB: + case HY_NAND_128MB: g_flashInfo.numBlocks = 1024; g_flashInfo.pagesPerBlock = 64; Modified: trunk/filo/drivers/flash/lxflash.h ============================================================================== --- trunk/filo/drivers/flash/lxflash.h Fri Feb 25 21:35:07 2011 (r142) +++ trunk/filo/drivers/flash/lxflash.h Thu Mar 31 23:26:40 2011 (r143) @@ -140,6 +140,7 @@ #define ST_NAND_64MB 0x76207620 #define ST_NAND_512MB 0x9580dc20 #define ST_NAND_128MB 0x1d80f120 +#define HY_NAND_128MB 0x1d80f1ad #define ERROR_SUCCESS 0 #define ERROR_BAD_PARAMS -1

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[PATCH] ICH7: Fix register naming error
by Sven Schnelle 31 Mar '11

31 Mar '11

There's an off-by-one error in the ACPI GP_LVL declaration: it declares GL00 with a bit count of 6, and continues with GP07 afterwards. This should be GP06, as the first bitfield covers GP00-GP05. While at it, change it to GP00-GP05, as right now GL00 isn't used, and single bitfield are more usable here. Als adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/getac/p470/acpi/ec.asl | 26 +++++++------- src/southbridge/intel/i82801gx/acpi/ich7.asl | 46 ++++++++++++++----------- 2 files changed, 39 insertions(+), 33 deletions(-) diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 30e78fa..6538b83 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -491,16 +491,16 @@ Scope(\_SB) If(And(RFDV, 0x08)) { Or(Local0, 0x08, Local0) } - If(And(GP16, 0x01)) { // GDIS + If(And(GP15, 0x01)) { // GDIS Or(Local0, 0x10, Local0) } - If(And(GP13, 0x01)) { // WIFI Led (WLED) + If(And(GP12, 0x01)) { // WIFI Led (WLED) Or(Local0, 0x20, Local0) } If(And(BTEN, 0x01)) { // BlueTooth Enable Or(Local0, 0x40, Local0) } - If(And(GP11, 0x01)) { // GPS Enable + If(And(GP10, 0x01)) { // GPS Enable Or(Local0, 0x80, Local0) } @@ -511,28 +511,28 @@ Scope(\_SB) Method(SRFD, 1, Serialized) { If (And(Arg0, 0x01)) { - Store (1, GP15) // GLED - Store (1, GP16) // GDIS + Store (1, GP14) // GLED + Store (1, GP15) // GDIS } Else { + Store (0, GP14) Store (0, GP15) - Store (0, GP16) } /* WIFI */ If (And(Arg0, 0x02)) { - Store (1, GP13) // WLED - Store (1, GP26) // WLAN + Store (1, GP12) // WLED + Store (1, GP25) // WLAN } Else { - Store (0, GP13) - Store (0, GP26) + Store (0, GP12) + Store (0, GP25) } /* Bluetooth */ If (And(Arg0, 0x04)) { - Store (1, GP14) // BLED + Store (1, GP13) // BLED Store (1, BTEN) } Else { - Store (0, GP14) // BLED + Store (0, GP13) // BLED Store (0, BTEN) } Return (0) @@ -577,7 +577,7 @@ Scope(\_SB) /* ??? */ Method(GTSD, 0, Serialized) { - Return (GP20) // TSDT + Return (GP19) // TSDT } /* Not even decent function names anymore? */ diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 8387b20..ad5bdd0 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -59,29 +59,35 @@ Scope(\) GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 6, - GP07, 1, // GDET + GP00, 1, + GP01, 1, + GP02, 1, + GP03, 1, + GP04, 1, + GP05, 1, + GP06, 1, // GDET + GP07, 1, GP08, 1, - GP09, 1, - GP10, 1, // HPMU - GP11, 1, // GPSE - GP12, 1, - GP13, 1, // WLED - GP14, 1, // BLED - GP15, 1, // GLED - GP16, 1, // GDIS + GP09, 1, // HPMU + GP10, 1, // GPSE + GP11, 1, + GP12, 1, // WLED + GP13, 1, // BLED + GP14, 1, // GLED + GP15, 1, // GDIS + GP16, 1, GP17, 1, - GP18, 1, - GP19, 1, // SPCI - GP20, 1, // TSDT - GP21, 1, // SCPU + GP18, 1, // SPCI + GP19, 1, // TSDT + GP20, 1, // SCPU + GP21, 1, GP22, 1, - GP23, 1, - GP24, 1, // LANP - GP25, 1, // DKLR - GP26, 1, // WLAN - GP27, 1, // SATA_PWR_EN #0 / SPOF - GP28, 1, // SATA_PWR_EN #1 / SPMU + GP23, 1, // LANP + GP24, 1, // DKLR + GP25, 1, // WLAN + GP26, 1, // SATA_PWR_EN #0 / SPOF + GP27, 1, // SATA_PWR_EN #1 / SPMU + GP28, 1, GP29, 1, GP30, 1, GP31, 1, -- 1.7.4.1

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X60: add support for Ultrabase X6
by Sven Schnelle 31 Mar '11

31 Mar '11

Hi List, these patches add support for the Ultrabase X6 to the Lenovo X60 port. while we already did initialize a Docking station in romstage to have serial output, these patches move those code to dock.c, which is used in romstage and SMM for Docking/Undocking. This patch only adds the basic ACPI code for getting the Fn-F9 key to work, all other required ACPI code will be submitted later.

2 4

Call for coreboot wiki updates
by Marc Jones 31 Mar '11

31 Mar '11

Hi corebooters! We have started to notice that some of the wiki articles have become out of date (v4, build/kconfig, seabios, libpayload, hardware support, etc). This has been a challenge for potential GSoC students and other developers that are new coreboot. If you have a little time and want to help the coreboot project, please update the wiki to reflect the current state of coreboot development. Thanks! Marc -- http://se-eng.com

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MSI 890FXA-GD70 (MS-7640)
by Linux User #330250 31 Mar '11

31 Mar '11

Hello! Will coreboot work on my system? *Step* *1:* A very brief description of your system: board vendor: MSI board name: 890FXA-GD70 (MS-7640) CPU: AMD Phenom II X6 1090T (stepping 00) northbridge: AMD 890FX southbridge: AMD SB850 /optionally/ /other/ /important/ /details:/ USB 3.0: Renesas/NEC μPD720200 *Step* *2:* Linux "lspci -tvnn" output for your system original BIOS, version 1.80 (release date 2011-02-24) /see/ /attachment/ /1:/ lspci.txt *Step* *3:* Super I/O chip on the mainboard According to [1] the chip is a Fintek F71889ED. This is yet unconfirmed, as superiotool (Gentoo Linux, see below) doesn't find it. /see/ /attachment/ /2:/ superiotool.txt *Step* *4:* Type of BIOS device /see/ /attachment/ /3:/ flashrom.txt BIOS/ROM flashing works. I successfully updated from 1.70 to 1.80. *Step* *5:* URL to the mainboard specifications page http://www.msi.com/product/mb/890FXA-GD70.html *Step* *6:* Any other relevant information you can provide None so far. If all components are already supported for other mainboards, it should /theoretically/ be possible to add this mainboard to the coreboot configuration. I'd be happy about it. How can I confirm the Super I/O chip? I used the official source tree ebuild sys-apps/superiotool-9999 from Gentoo Linux: This version apparently doesn't even give a release information. I'd be happy if the 890FXA-GD70 was supported by coreboot. Thanks, Andreas aka Linux User #330250 Sources: [1]: http://www.hardwaresecrets.com/article/MSI-890FXA-GD70-Motherboard/1023/7

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Board Incompatible but chipset is?
by Brandon 31 Mar '11

31 Mar '11

Hello. I have a Tyan Trinity S1857 board and according to your compatible chipset list, it's chipset (Intel 440BX) is compatible. Is there anyway I can get a port of some kind? I'm really not good with C at all and I'd really like use Coreboot. Any reply will be greatly appreciated. Thank you :)

3 2

Re: [coreboot] [SerialICE] Serial output on Winbond W83627HG
by Joseph Smith 29 Mar '11

29 Mar '11

On 03/29/2011 05:34 PM, Stefan Reinauer wrote: > * Joseph Smith<joe(a)settoplinux.org> [110329 23:00]: >> Oh for reference: >> "To enable configuration registers programming, entry key must >> output twice to index port continuously. The entry key is decided by >> power on setting pins RTS2#/PS_CONF_KEY1 and RTS3#/PS_CONF_KEY0 as >> following: >> >> RTS2#/PS_CONF_KEY1 RTS3#/PS_CONF_KEY0 Entry key >> 0 0 0x77 ( default ) >> 0 1 0xA0 >> 1 0 0x87 >> 1 1 0x67 >> >> 0x67 was the winner for me :-) > > Please supply a patch that adds this entry key to the fintec code in > superiotool. > Yes on my todo list. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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coreboot March 2011