coreboot March 2011

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[commit] r6465 - trunk/src/southbridge/amd
by repository service 28 Mar '11

28 Mar '11

Author: zbao Date: Mon Mar 28 06:36:21 2011 New Revision: 6465 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6465 Log: Add the SR5650 & SP5100 to the Kconfig and Makefile.inc Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/southbridge/amd/Kconfig trunk/src/southbridge/amd/Makefile.inc Modified: trunk/src/southbridge/amd/Kconfig ============================================================================== --- trunk/src/southbridge/amd/Kconfig Mon Mar 28 06:29:14 2011 (r6464) +++ trunk/src/southbridge/amd/Kconfig Mon Mar 28 06:36:21 2011 (r6465) @@ -12,3 +12,4 @@ source src/southbridge/amd/sb700/Kconfig source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx_wrapper/Kconfig +source src/southbridge/amd/sr5650/Kconfig Modified: trunk/src/southbridge/amd/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/Makefile.inc Mon Mar 28 06:29:14 2011 (r6464) +++ trunk/src/southbridge/amd/Makefile.inc Mon Mar 28 06:36:21 2011 (r6465) @@ -7,6 +7,8 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536

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[commit] r6464 - in trunk/src: cpu/amd cpu/amd/model_10xxx cpu/amd/socket_C32 northbridge/amd/amdfam10 northbridge/amd/amdmct northbridge/amd/amdmct/mct
by repository service 28 Mar '11

28 Mar '11

Author: zbao Date: Mon Mar 28 06:29:14 2011 New Revision: 6464 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6464 Log: Add AMD C32 support. It is based on other existing Fam10 code. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/cpu/amd/model_10xxx/mc_patch_010000c4.h trunk/src/cpu/amd/socket_C32/ (props changed) - copied from r6462, trunk/src/cpu/amd/socket_AM3/ trunk/src/cpu/amd/socket_C32/socket_C32.c (contents, props changed) - copied, changed from r6462, trunk/src/cpu/amd/socket_AM3/socket_AM3.c Deleted: trunk/src/cpu/amd/socket_C32/socket_AM3.c Modified: trunk/src/cpu/amd/Kconfig trunk/src/cpu/amd/Makefile.inc trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/src/cpu/amd/model_10xxx/processor_name.c trunk/src/cpu/amd/model_10xxx/update_microcode.c trunk/src/cpu/amd/socket_C32/Kconfig trunk/src/cpu/amd/socket_C32/Makefile.inc trunk/src/cpu/amd/socket_C32/chip.h trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdmct/amddefs.h trunk/src/northbridge/amd/amdmct/mct/mct_d.c Modified: trunk/src/cpu/amd/Kconfig ============================================================================== --- trunk/src/cpu/amd/Kconfig Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/Kconfig Mon Mar 28 06:29:14 2011 (r6464) @@ -8,6 +8,7 @@ source src/cpu/amd/socket_AM2/Kconfig source src/cpu/amd/socket_AM2r2/Kconfig source src/cpu/amd/socket_AM3/Kconfig +source src/cpu/amd/socket_C32/Kconfig source src/cpu/amd/socket_ASB2/Kconfig source src/cpu/amd/socket_F/Kconfig source src/cpu/amd/socket_F_1207/Kconfig Modified: trunk/src/cpu/amd/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/Makefile.inc Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/Makefile.inc Mon Mar 28 06:29:14 2011 (r6464) @@ -7,6 +7,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 +subdirs-$(CONFIG_CPU_AMD_SOCKET_C32) += socket_C32 subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 subdirs-$(CONFIG_CPU_AMD_LX) += model_lx Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Mon Mar 28 06:29:14 2011 (r6464) @@ -89,9 +89,25 @@ 0x00000000, 1 << (33-32), 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ - { BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL, + { BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL, 0x00000000, 1 << (35-32), 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */ + + { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00000004, 0x00000000, + 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */ + + { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC, + 0x0000000C, 0x00000000, + 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */ + + { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00000000, 1 << (50-32), + 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ + + { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL, + 0x00000000, 1 << (51 - 32), + 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */ }; @@ -140,28 +156,28 @@ * program Link Global Extended Control Register[ForceFullT0] * (F0x16C[15:13]) to 000b */ - { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */ + { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */ 0x00000000, 0x00000100 }, - { 0, 0x174, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x178, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x17C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x180, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x184, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x188, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x18C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, + { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, - 0x00000014, 0x0000E03F }, /* [15:13] ForceFullT0 = 0b, + { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, * Set T0Time 14h per BKDG */ @@ -297,7 +313,7 @@ [5] DisPciCfgCpuMstAbtRsp = 1, [1] SyncFloodOnUsPwDataErr = 1 */ - /* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23] too but I can't find their constants + /* errata 346 - Fam10 C2, C3 * System software should set F3x188[22] to 1b. */ { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, 0x00400000, 0x00400000 }, @@ -324,100 +340,100 @@ u32 mask; } fam10_htphy_default[] = { - /* Errata 344 - Fam10 C2/D0 -- FIXME at 25.6.2010 should be for ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them + /* Errata 344 - Fam10 C2/C3, D0/D1 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_DRBH_Cx , AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - /* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants + /* Errata 354 - Fam10 C2, C3 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ - { 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - /* Errata 327 - Fam10 C2/D0 + /* Errata 327 - Fam10 C2/C3, D0/D1 * BIOS should set the Link Phy Impedance Register[RttCtl] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and * Link Phy Impedance Register[RttIndex] * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */ - { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, - { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ - { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */ { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, Added: trunk/src/cpu/amd/model_10xxx/mc_patch_010000c4.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/model_10xxx/mc_patch_010000c4.h Mon Mar 28 06:29:14 2011 (r6464) @@ -0,0 +1,186 @@ +/* + ****************************************************************************** + * + * Copyright 2010 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + +0x10, 0x20, 0x03, 0x03, 0xc4, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x01, +0x4a, 0xe0, 0x9c, 0x93, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x81, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xa7, 0x0b, 0x00, 0x00, +0x14, 0x0c, 0x00, 0x00, 0x55, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, +0x51, 0x03, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0xff, 0xff, 0xff, 0xff, 0x4f, 0xdf, 0x38, 0x00, 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trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Mon Mar 28 06:29:14 2011 (r6464) @@ -145,6 +145,7 @@ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ { 0, 0 }, }; Modified: trunk/src/cpu/amd/model_10xxx/processor_name.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/processor_name.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/processor_name.c Mon Mar 28 06:29:14 2011 (r6464) @@ -154,6 +154,25 @@ {0, 0, 0, NULL} }; +static const struct str_s String1_socket_C32[] = { + {0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"}, + {0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"}, + {0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "}, + {0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "}, + {0, 0, 0, NULL} +}; + +static const struct str_s String2_socket_C32[] = { + {0x00, 0x03, 0x00, " HE"}, + {0x00, 0x03, 0x01, " EE"}, + {0x00, 0x05, 0x00, " HE"}, + {0x00, 0x05, 0x01, " EE"}, + {0x01, 0x03, 0x01, "QS HE"}, + {0x01, 0x03, 0x02, "LE HE"}, + {0x01, 0x05, 0x01, "KX HE"}, + {0x01, 0x05, 0x02, "GL EE"}, + {0, 0, 0, NULL} +}; const char const *unknown = "AMD Processor model unknown"; const char const *unknown2 = " type unknown"; @@ -218,6 +237,10 @@ str = String1_socket_AM2; str2 = String2_socket_AM2; break; + case 5: /* C32 */ + str = String1_socket_C32; + str2 = String2_socket_C32; + break; default: goto done; } Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/update_microcode.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/cpu/amd/model_10xxx/update_microcode.c Mon Mar 28 06:29:14 2011 (r6464) @@ -50,6 +50,7 @@ * 00100F43h (RB-C3) 1043h 010000b6h * 00100F62h (DA-C2) 1062h 0100009Fh * 00100F63h (DA-C3) 1043h 010000b6h + * 00100F81h (HY-D1) 1081h 010000c4h */ #include CONFIG_AMD_UCODE_PATCH_FILE @@ -76,6 +77,7 @@ 0x100f43, 0x1043, 0x100f62, 0x1062, 0x100f63, 0x1043, + 0x100f81, 0x1081, }; u32 new_id; Modified: trunk/src/cpu/amd/socket_C32/Kconfig ============================================================================== --- trunk/src/cpu/amd/socket_AM3/Kconfig Sun Mar 27 18:39:58 2011 (r6462) +++ trunk/src/cpu/amd/socket_C32/Kconfig Mon Mar 28 06:29:14 2011 (r6464) @@ -1,4 +1,4 @@ -config CPU_AMD_SOCKET_AM3 +config CPU_AMD_SOCKET_C32 bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT @@ -7,36 +7,36 @@ config CPU_SOCKET_TYPE hex - default 0x11 - depends on CPU_AMD_SOCKET_AM3 + default 0x14 + depends on CPU_AMD_SOCKET_C32 config EXT_RT_TBL_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32 config EXT_CONF_SUPPORT bool default n - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32 config CBB hex default 0x0 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32 config CDB hex default 0x18 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32 config XIP_ROM_BASE hex default 0xfff80000 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32 config XIP_ROM_SIZE hex default 0x80000 - depends on CPU_AMD_SOCKET_AM3 + depends on CPU_AMD_SOCKET_C32 Modified: trunk/src/cpu/amd/socket_C32/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/socket_AM3/Makefile.inc Sun Mar 27 18:39:58 2011 (r6462) +++ trunk/src/cpu/amd/socket_C32/Makefile.inc Mon Mar 28 06:29:14 2011 (r6464) @@ -1,4 +1,4 @@ -ramstage-y += socket_AM3.c +ramstage-y += socket_C32.c subdirs-y += ../model_10xxx subdirs-y += ../quadcore subdirs-y += ../mtrr Modified: trunk/src/cpu/amd/socket_C32/chip.h ============================================================================== --- trunk/src/cpu/amd/socket_AM3/chip.h Sun Mar 27 18:39:58 2011 (r6462) +++ trunk/src/cpu/amd/socket_C32/chip.h Mon Mar 28 06:29:14 2011 (r6464) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -extern struct chip_operations cpu_amd_socket_AM3_ops; +extern struct chip_operations cpu_amd_socket_C32_ops; -struct cpu_amd_socket_AM3_config { +struct cpu_amd_socket_C32_config { }; Copied and modified: trunk/src/cpu/amd/socket_C32/socket_C32.c (from r6462, trunk/src/cpu/amd/socket_AM3/socket_AM3.c) ============================================================================== --- trunk/src/cpu/amd/socket_AM3/socket_AM3.c Sun Mar 27 18:39:58 2011 (r6462, copy source) +++ trunk/src/cpu/amd/socket_C32/socket_C32.c Mon Mar 28 06:29:14 2011 (r6464) @@ -20,6 +20,6 @@ #include <device/device.h> #include "chip.h" -struct chip_operations cpu_amd_socket_AM3_ops = { - CHIP_NAME("socket AM3") +struct chip_operations cpu_amd_socket_C32_ops = { + CHIP_NAME("socket C32") }; Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Mon Mar 28 06:29:14 2011 (r6464) @@ -78,6 +78,9 @@ #elif CONFIG_CPU_SOCKET_TYPE == 0x13 //ASB2 #include "../amdmct/mct_ddr3/mctardk5.c" +//C32 +#elif CONFIG_CPU_SOCKET_TYPE == 0x14 +#include "../amdmct/mct_ddr3/mctardk5.c" #endif #else /* DDR2 */ @@ -205,6 +208,9 @@ case 0x10080: ret = AMD_HY_D0; break; + case 0x10081: + ret = AMD_HY_D1; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Mon Mar 28 06:29:14 2011 (r6464) @@ -45,6 +45,7 @@ #define AMD_HY_D0 0x04000000 /* Istanbul D0 */ #define AMD_RB_C3 0x08000000 /* ??? C3 */ #define AMD_DA_C3 0x10000000 /* XXXX C3 */ +#define AMD_HY_D1 0x20000000 /* Istanbul D1 */ /* * Groups - Create as many as you wish, from the above public values @@ -61,19 +62,18 @@ #define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) +#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) #define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) -#define AMD_DR_Dx (AMD_HY_D0) -#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) -#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) - -#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) -#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3) +#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) +#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) +#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3) /* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Mon Mar 28 05:33:10 2011 (r6463) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Mon Mar 28 06:29:14 2011 (r6464) @@ -2407,7 +2407,7 @@ // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct); /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */ - if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) { + if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { if (pDCTstat->GangedMode) { val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); val |= 1 << DisAutoRefresh; @@ -2421,7 +2421,7 @@ * to ensure both DCTs are in sync (Erratum 278) */ - if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) { + if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { if (pDCTstat->GangedMode) { do { val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));

1 0

[PATCH] 440BX registered SDRAM support
by Keith Hui 28 Mar '11

28 Mar '11

See attached for patch with sign-off inside. Boot tested on ASUS P2B-LS with both regular and registered ECC modules. Now that I got some registered ECC modules in, I am able to code up this patch to allow registered SDRAM to initialize. This is needed in advance of ECC support because most ECC modules are registered. The same modules I have also happened to be electrically "256MB single side" so I am finally able to, unfortunately, exercise the "set it smaller so at least I can use it" patch of r5508. ECC is still not enabled in this patch. That would be for a separate patch. Enjoy Keith

2 1

[commit] r6462 - in trunk/src: include/device southbridge/amd/sr5650
by repository service 27 Mar '11

27 Mar '11

Author: zbao Date: Sun Mar 27 18:39:58 2011 New Revision: 6462 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6462 Log: Add AMD SR56x0 support. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/southbridge/amd/sr5650/ trunk/src/southbridge/amd/sr5650/Kconfig trunk/src/southbridge/amd/sr5650/Makefile.inc trunk/src/southbridge/amd/sr5650/chip.h trunk/src/southbridge/amd/sr5650/cmn.h trunk/src/southbridge/amd/sr5650/early_setup.c trunk/src/southbridge/amd/sr5650/ht.c trunk/src/southbridge/amd/sr5650/pcie.c trunk/src/southbridge/amd/sr5650/rev.h trunk/src/southbridge/amd/sr5650/sr5650.c trunk/src/southbridge/amd/sr5650/sr5650.h Modified: trunk/src/include/device/pci_ids.h Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Sun Mar 27 18:33:09 2011 (r6461) +++ trunk/src/include/device/pci_ids.h Sun Mar 27 18:39:58 2011 (r6462) @@ -365,6 +365,23 @@ #define PCI_DEVICE_ID_ATI_RS785MC_INT_GFX 0x9713 #define PCI_DEVICE_ID_ATI_RS785D_INT_GFX 0x9714 +#define PCI_DEVICE_ID_AMD_SR5650_HT 0x5A13 +#define PCI_DEVICE_ID_AMD_SR5670_HT 0x5A12 +#define PCI_DEVICE_ID_AMD_SR5690_HT 0x5A10 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2 0x5A16 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3 0x5A17 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4 0x5A18 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV5 0x5A19 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV6 0x5A1A +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV7 0x5A1B +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV9 0x5A1C +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV10 0x5A1D +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV11 0x5A1F +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12 0x5A20 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E +#define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 + #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 #define PCI_DEVICE_ID_VLSI_82C593 0x0006 Added: trunk/src/southbridge/amd/sr5650/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/Kconfig Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_SR5650 + bool Added: trunk/src/southbridge/amd/sr5650/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/Makefile.inc Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,3 @@ +driver-y += sr5650.c +driver-y += pcie.c +driver-y += ht.c Added: trunk/src/southbridge/amd/sr5650/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/chip.h Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SR5650_CHIP_H +#define SR5650_CHIP_H + +/* Member variables are defined in Config.lb. */ +struct southbridge_amd_sr5650_config +{ + u8 gpp1_configuration; /* The configuration of General Purpose Port. */ + u8 gpp2_configuration; /* The configuration of General Purpose Port. */ + u8 gpp3a_configuration; /* The configuration of General Purpose Port. */ + u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */ +}; +struct chip_operations; +extern struct chip_operations southbridge_amd_sr5650_ops; + +#endif /* SR5650_CHIP_H */ Added: trunk/src/southbridge/amd/sr5650/cmn.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/cmn.h Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SR5650_CMN_H__ +#define __SR5650_CMN_H__ + +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 +#define EXT_CONF_BASE_ADDRESS 0xE0000000 +#define TEMP_MMIO_BASE_ADDRESS 0xC0000000 + +static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +{ + pci_write_config32(dev, index_reg, index); + return pci_read_config32(dev, index_reg + 0x4); +} + +static inline void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +{ + pci_write_config32(dev, index_reg, index); + pci_write_config32(dev, index_reg + 0x4, data); +} + +static inline u32 nbmisc_read_index(device_t nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMISC_INDEX, (index)); +} + +static inline void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); +} + +static inline void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, + u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmisc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmisc_write_index(nb_dev, reg_pos, reg); + } +} + +static inline u32 htiu_read_index(device_t nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); +} + +static inline void htiu_write_index(device_t nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); +} + +static inline u32 nbmc_read_index(device_t nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBMC_INDEX, (index)); +} + +static inline void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); +} + +static inline void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, + u32 val) +{ + u32 reg_old, reg; + reg = reg_old = htiu_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + htiu_write_index(nb_dev, reg_pos, reg); + } +} + +static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, + u32 val) +{ + u32 reg_old, reg; + reg = reg_old = pci_read_config32(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config32(nb_dev, reg_pos, reg); + } +} + +static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, + u8 val) +{ + u8 reg_old, reg; + reg = reg_old = pci_read_config8(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + pci_write_config8(nb_dev, reg_pos, reg); + } +} + +static inline void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, + u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nbmc_read_index(nb_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nbmc_write_index(nb_dev, reg_pos, reg); + } +} + +static inline void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg); + } +} +#endif /* __SR5650_CMN_H__ */ Added: trunk/src/southbridge/amd/sr5650/early_setup.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/early_setup.c Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,540 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "sr5650.h" +#include "cmn.h" + +/* family 10 only, for reg > 0xFF */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 +static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, + u32 val) +{ + u32 reg_old, reg; + reg = reg_old = Get_NB32(fam10_dev, reg_pos); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + Set_NB32(fam10_dev, reg_pos, reg); + } +} +#else +#define set_fam10_ext_cfg_enable_bits(a, b, c, d) do {} while (0) +#endif + + +/* +* Compliant with CIM_33's ATINB_PrepareInit +*/ +static void get_cpu_rev(void) +{ + u32 eax; + + eax = cpuid_eax(1); + printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); + if (eax <= 0xfff) + printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); + else if (eax <= 0x10fff) + printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); + else if (eax <= 0x20fff) + printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); + else if (eax <= 0x40fff) + printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); + else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); + else if (eax <= 0X60FF0) + printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); + else if (eax <= 0x100000) + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); + else if (eax <= 0x100f00) + printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); + else + printk(BIOS_INFO, "CPU Rev is not recognized.\n"); +} + +/* +CIM NB_GetRevisionInfo() +*/ +static u8 get_nb_rev(device_t nb_dev) +{ + u8 reg; + reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */ + switch(reg & 3) + { + case 0x00: + reg = REV_SR5650_A11; + break; + case 0x02: + default: + reg = REV_SR5650_A12; + break; + } + return reg; +} + +/***************************************** +* Compliant with SR5650_CIMX_4_5_0 NBHT_InitHT(). +* Init HT link speed/width for sr5650 -- k8 link +1: Check CPU Family, Family10? +2: Get CPU's HT speed and width +3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1 +4: +*****************************************/ +static const u8 sr5650_ibias[] = { + /* 1, 3 are reserved. */ + [0x0] = 0x44, /* 200Mhz HyperTransport 1 only */ + [0x2] = 0x44, /* 400Mhz HyperTransport 1 only */ + [0x4] = 0xB6, /* 600Mhz HyperTransport 1 only */ + [0x5] = 0x44, /* 800Mhz HyperTransport 1 only */ + [0x6] = 0x96, /* 1Ghz HyperTransport 1 only */ + /* HT3 for Family 10 */ + [0x7] = 0xB6, /* 1.2Ghz HyperTransport 3 only */ + [0x8] = 0x23, /* 1.4Ghz HyperTransport 3 only */ + [0x9] = 0x44, /* 1.6Ghz HyperTransport 3 only */ + [0xa] = 0x64, /* 1.8Ghz HyperTransport 3 only */ + [0xb] = 0x96, /* 2.0Ghz HyperTransport 3 only */ + [0xc] = 0xA6, /* 2.2Ghz HyperTransport 3 only */ + [0xd] = 0xB6, /* 2.4Ghz HyperTransport 3 only */ + [0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */ +}; + +static void sr5650_htinit(void) +{ + /* + * About HT, it has been done in enumerate_ht_chain(). + */ + device_t cpu_f0, sr5650_f0, clk_f1, cpu1_f0; + u32 reg; + u8 cpu_ht_freq, ibias; + + cpu_f0 = PCI_DEV(0, 0x18, 0); + cpu1_f0 = PCI_DEV(0, 0x19, 0); + /************************ + * get cpu's ht freq, in cpu's function 0, offset 0x88 + * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. + * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero + * value to this reg, and that value takes effect on the next warm reset or + * LDTSTOP_L disconnect sequence. + * please see the table sr5650_ibias about the value and its corresponding frequency. + ************************/ + /* Link0, Link1 are for connection between P0 and P1. + * Link2 should be 0xC8? + * TODO: Check the topology of the MP and NB. Or we just read the nbconfig? */ + /* NOTE: In most cases, we only have one CPU. In that case, we should read 0x88. */ + + reg = pci_read_config32(cpu1_f0, 0x0); + reg = pci_read_config32(cpu_f0, + reg == 0 || reg == -1 ? 0x88 : 0xC8 + ); + cpu_ht_freq = (reg & 0xf00) >> 8; + printk(BIOS_INFO, "sr5650_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); + sr5650_f0 = PCI_DEV(0, 0, 0); + + clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */ + + ibias = sr5650_ibias[cpu_ht_freq]; + + /* If HT freq>1GHz, we assume the CPU is fam10, else it is K8. + * Is it appropriate? + * Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases. + * So we check 6 only, it would be faster. */ + if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || + (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { + printk(BIOS_INFO, "sr5650_htinit: HT1 mode\n"); + + /* HT1 mode, RPR 5.4.2 */ + /* set IBIAS code */ + set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); + /* Optimizes chipset HT transmitter drive strength */ + set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x3); + } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { + printk(BIOS_INFO, "sr5650_htinit: HT3 mode\n"); + + /* Enable Protocol checker */ + set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC); + + #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ + /* HT3 mode, RPR 5.4.3 */ + set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0); + + /* set IBIAS code */ + set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias); + /* Optimizes chipset HT transmitter drive strength */ + set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x1); + /* Enables error-retry mode */ + set_nbcfg_enable_bits(sr5650_f0, 0x44, 0x1, 0x1); + /* Enables scrambling and Disalbes command throttling */ + set_nbcfg_enable_bits(sr5650_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14)); + /* Enables transmitter de-emphasis */ + set_nbcfg_enable_bits(sr5650_f0, 0xa4, 1 << 31, 1 << 31); + /* Enabels transmitter de-emphasis level */ + /* Sets training 0 time */ + set_nbcfg_enable_bits(sr5650_f0, 0xa0, 0x3F, 0x14); + + /* Enables strict TM4 detection */ + set_htiu_enable_bits(sr5650_f0, 0x15, 0x1 << 22, 0x1 << 22); + + /* HyperTransport 3 Processor register settings to be done in northbridge */ + /* Enables error-retry mode */ + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0); + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x134, 1 << 0, 1 << 0); /* TODO: Check if it is needed to set other node. */ + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x138, 1 << 0, 1 << 0); + /* Enables scrambling */ + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3); + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x174, 1 << 3, 1 << 3); /* TODO: Check if it is needed to set other node. */ + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x178, 1 << 3, 1 << 3); + /* Enables transmitter de-emphasis + * This depends on the PCB design and the trace */ + /* Disables command throttling */ + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10); + /* Sets Training 0 Time. See T0Time table for encodings */ + set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); + /* HT Buffer Allocation for Ganged Links!!! */ + #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ + } +} + +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */ +/******************************************************* +* Optimize k8 with UMA. +* See BKDG_NPT_0F guide for details. +* The processor node is addressed by its Node ID on the HT link and can be +* accessed with a device number in the PCI configuration space on Bus0. +* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped +* to Device 25, and so on. +* The processor implements configuration registers in PCI configuration +* space using the following four headers +* Function0: HT technology configuration +* Function1: Address map configuration +* Function2: DRAM and HT technology Trace mode configuration +* Function3: Miscellaneous configuration +*******************************************************/ +static void k8_optimization(void) +{ + device_t k8_f0, k8_f2, k8_f3; + msr_t msr; + + printk(BIOS_INFO, "k8_optimization()\n"); + k8_f0 = PCI_DEV(0, 0x18, 0); + k8_f2 = PCI_DEV(0, 0x18, 2); + k8_f3 = PCI_DEV(0, 0x18, 3); + + pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */ + set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28); + set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27, + 1 << 26 | 1 << 27); + set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11); + /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */ + + pci_write_config32(k8_f3, 0x70, 0x51220111); /* CIM NPT_Optimization */ + pci_write_config32(k8_f3, 0x74, 0x50404021); + pci_write_config32(k8_f3, 0x78, 0x08002A00); + if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12) + pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */ + else + pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */ + set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25); + + set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); + set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24); + set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10); + set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); + set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); + + msr = rdmsr(0xC001001F); + msr.lo &= ~(1 << 9); + msr.hi &= ~(1 << 4); + wrmsr(0xC001001F, msr); +} +#else +#define k8_optimization() do{}while(0) +#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ + +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ +void fam10_optimization(void) +{ + device_t cpu_f0, cpu_f2, cpu_f3; + device_t cpu1_f0, cpu1_f2, cpu1_f3; + msr_t msr; + u32 val; + + printk(BIOS_INFO, "fam10_optimization()\n"); + msr = rdmsr(0xC001001F); + msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */ + wrmsr(0xC001001F, msr); + + cpu_f0 = PCI_DEV(0, 0x18, 0); + cpu_f2 = PCI_DEV(0, 0x18, 2); + cpu_f3 = PCI_DEV(0, 0x18, 3); + cpu1_f0 = PCI_DEV(0, 0x19, 0); + cpu1_f2 = PCI_DEV(0, 0x19, 2); + cpu1_f3 = PCI_DEV(0, 0x19, 3); + + val = pci_read_config32(cpu1_f3, 0x8C); + val |= 1 << 14; + pci_write_config32(cpu1_f3, 0x8C, val); + + /* TODO: HT Buffer Allocation for (un)Ganged Links */ + /* rpr Table 5-11, 5-12 */ +} +#else +#define fam10_optimization() do{}while(0) +#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ + +/***************************************** +* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE +*****************************************/ +static void sr5650_por_pcicfg_init(device_t nb_dev) +{ + /* enable PCI Memory Access */ + set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); + + set_nbcfg_enable_bits(nb_dev, 0x14, ~0, 0x0); + set_nbcfg_enable_bits(nb_dev, 0x18, ~0, 0x0); + set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0); + set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010); + + /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation + * BMMsgEn */ + set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042); + + set_nbcfg_enable_bits(nb_dev, 0x7C, (u8)(~0), 0x0); + + /* Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, + * force this BAR as mem type in sr5650_gfx.c */ + //set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); +} + +/***************************************** +* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE +* Compliant with CIM_33's MISC_INIT_TBL +*****************************************/ +static void sr5650_por_misc_index_init(device_t nb_dev) +{ + /* disable IOMMU */ + set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x0); + /* NBMISCIND:0x75[29]= 1 Device ID for hotplug and PME message */ + set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 29, 1 << 29); + set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 9, 1 << 9); /* no doc reference, comply with BTS */ + set_nbmisc_enable_bits(nb_dev, 0x46, 1 << 7, 1 << 7); /* bit7 BTS fail*/ + /*P2P*/ + set_nbmisc_enable_bits(nb_dev, 0x48, 1 << 8, 0); + + set_nbmisc_enable_bits(nb_dev, 0x2A, 1 << 15 | 1 << 17, 1 << 17); + set_nbmisc_enable_bits(nb_dev, 0x2B, 1 << 15 | 1 << 27, 1 << 15 | 1 << 27); + set_nbmisc_enable_bits(nb_dev, 0x2C, 1 << 0 | 1 << 1 | 1 << 5 | 1 << 4 | 1 << 10, 1 << 0 | 1 << 1 | 1 << 5); + set_nbmisc_enable_bits(nb_dev, 0x32, 0x3F << 20, 0x2A << 20); + set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23 | 1 << 31, 0); /* bit31 BTS fail */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3F << 26, 0x2A << 26); + set_nbmisc_enable_bits(nb_dev, 0x37, 0xfff << 20, 0xddd << 20); + set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 11, 0); + /* PCIE CDR setting */ + set_nbmisc_enable_bits(nb_dev, 0x38, 0xFFFFFFFF, 0xC0C0C0); + set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 31, 0); /* bit31 BTS fail */ + set_nbmisc_enable_bits(nb_dev, 0x22, 0xFFFFFFFF, (1 << 27) | (0x8 << 12) | (0x8 << 16) | (0x8 << 20)); + set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7); + + set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 4 | 1 << 24, 0xF << 4 | 1 << 24); + set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10 | 1 << 11 | 1 << 26, 1 << 11); + set_nbmisc_enable_bits(nb_dev, 0x67, 3 << 21, 3 << 21); + set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 8 | 1 << 9 | 1 << 19, 1 << 9 | 1 << 19); + set_nbmisc_enable_bits(nb_dev, 0x6B, 3 << 3 | 1 << 15 | 0x1F << 27, 3 << 3 | 1 << 15 | 0x1F << 27); + set_nbmisc_enable_bits(nb_dev, 0x6C, 0xFFFFFFFF, 0x41183000); + + /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL + * Block non-snoop DMA request if PMArbDis is set. + * Set BMSetDis */ + set_nbmisc_enable_bits(nb_dev, 0x0B, 0xFFFFFFFF, 0x00400180); + set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); + + /* NBCFG (NBMISCIND 0x0): NB_CNTL - + * HIDE_NB_AGP_CAP ([0], default=1)HIDE + * HIDE_P2P_AGP_CAP ([1], default=1)HIDE + * HIDE_NB_GART_BAR ([2], default=1)HIDE + * AGPMODE30 ([4], default=0)DISABLE + * AGP30ENCHANCED ([5], default=0)DISABLE + * HIDE_AGP_CAP ([8], default=1)ENABLE */ + set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 6); + + /* IOC_LAT_PERF_CNTR_CNTL */ + set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); + //set_nbmisc_enable_bits(nb_dev, 0x31, 0xFF, 0x00); + + /* IOC_LAT_PERF_CNTR_OUT */ + /* IOC_JTAG_CNTL */ + set_nbmisc_enable_bits(nb_dev, 0x47, 0xFFFFFFFF, 0x0000000B); + + set_nbmisc_enable_bits(nb_dev, 0x12, 0xFFFFFFFF, 0x00FB5555); + set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001f37EC); + set_nbmisc_enable_bits(nb_dev, 0x15, 0xFFFFFFFF, 0x0); + + /* NB_PROG_DEVICE_REMAP */ + set_nbmisc_enable_bits(nb_dev, 0x20, 0xFFFFFFFF, 0x0); + set_nbmisc_enable_bits(nb_dev, 0x21, 0xFFFFFFFF, 0x0); + + /* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE + * Enable access to DEV8 + * Enable setPower message for all ports + */ + set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x61, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x63, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8); + + /* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */ + set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x400180); +} + +/***************************************** +* Some setting is from rpr. Some is from CIMx. +*****************************************/ +static void sr5650_por_htiu_index_init(device_t nb_dev) +{ + device_t cpu_f0; + + cpu_f0 = PCI_DEV(0, 0x18, 0); + + set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); + set_htiu_enable_bits(nb_dev, 0x05, 0x1<<8, 0x1<<8); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17); + set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30); + + set_htiu_enable_bits(nb_dev, 0x07, 0x1 << 0 | 0x1 << 1 | 0x1 << 2, 0x1 << 0); + + set_htiu_enable_bits(nb_dev, 0x16, 0x1<<11, 0x1<<11); + + set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2, 0x1<<2); + set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4, 0x1<<4); + + set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 0 << 21); + axindxc_reg(0x10, 1 << 9, 1 << 9); + set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9); + set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26); + set_htiu_enable_bits(nb_dev, 0x16, 0x1<<10, 0x1<<10); + + /* Enable BIAS circuit for all lanes. */ + //set_htiu_enable_bits(nb_dev, 0x2B, 0xF<<28, 0xF<<28); + set_htiu_enable_bits(nb_dev, 0x2B, 0xF << 28, 0); + set_htiu_enable_bits(nb_dev, 0x05, 0xFFFFFF, 0xFF558); + set_htiu_enable_bits(nb_dev, 0x06, 0xFFFFFFFE, 0x04203A202); + set_htiu_enable_bits(nb_dev, 0x0C, 0xFFFF, 0x101); + + /* A21 only */ + //if (REV_SR5650_A21 == get_nb_rev(nb_dev)) { + if (get_nb_rev(nb_dev) > REV_SR5650_A11) { + set_htiu_enable_bits(nb_dev, 0x05, 0x3<<3| 1<<6 | 1<<10 | 0xFF<<12, 0x3<<3 | 1<<6 | 1<<10 | 0xFF<<12); + set_htiu_enable_bits(nb_dev, 0x1D, 1 << 2 | 1 << 4, 0); + } +} + +/***************************************** +* Compliant with CIM_33's ATINB_POR_INIT_JMPDI +* Configure SR5650 registers to power-on default RPR. +* POR: Power On Reset +* RPR: Register Programming Requirements +*****************************************/ +static void sr5650_por_init(device_t nb_dev) +{ + printk(BIOS_INFO, "sr5650_por_init\n"); + /* ATINB_PCICFG_POR_TABLE, initialize the values for sr5650 PCI Config registers */ + sr5650_por_pcicfg_init(nb_dev); + + /* ATINB_MISCIND_POR_TABLE */ + sr5650_por_misc_index_init(nb_dev); + + /* ATINB_HTIUNBIND_POR_TABLE */ + sr5650_por_htiu_index_init(nb_dev); + + /* ATINB_CLKCFG_PORT_TABLE */ + /* sr5650 A11 SB Link full swing? */ +} + +/* enable CFG access to Dev8, which is the SB P2P Bridge */ +static void enable_sr5650_dev8(void) +{ + set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); +} + +/* +* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). +*/ +static void sr5650_before_pci_init(void) +{ +} + +/* +* The calling sequence is same as CIM. +*/ +static void sr5650_early_setup(void) +{ + device_t nb_dev = PCI_DEV(0, 0, 0); + printk(BIOS_INFO, "sr5650_early_setup()\n"); + + /*ATINB_PrepareInit */ + get_cpu_rev(); + + switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */ + case REV_SR5650_A11: + printk(BIOS_INFO, "NB Revision is A11.\n"); + break; + case REV_SR5650_A12: + printk(BIOS_INFO, "NB Revision is A12.\n"); + break; + case REV_SR5650_A21: + printk(BIOS_INFO, "NB Revision is A21.\n"); + break; + } + +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 + + fam10_optimization(); +#else + k8_optimization(); +#endif + + sr5650_por_init(nb_dev); +} + +/** + * @brief disable GPP1 Port0,1, GPP3a Port0,1,2,3,4,5 + * + */ +void disable_pcie_bridge(void) +{ + u32 mask; + u32 reg; + device_t nb_dev = PCI_DEV(0, 0, 0); + + mask = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | + (1 << 16) | (1 << 17); + reg = mask; + set_nbmisc_enable_bits(nb_dev, 0x0c, mask, reg); +} Added: trunk/src/southbridge/amd/sr5650/ht.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/ht.c Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/ioapic.h> +#include "sr5650.h" + +/* Table 6-6 Recommended Interrupt Routing Configuration */ +typedef struct _apic_device_info { + u8 group; + u8 swizzle; + u8 pin; +} apic_device_info; + +#define ABCD 0 +#define BCDA 1 +#define CDAB 2 +#define DABC 3 + +static const apic_device_info default_apic_device_info_t [] = { + /* Group Swizzling Port Int Pin */ + [0] = {0, 0, 31}, /* HT */ + [1] = {0, 0, 31}, /* IOMMU */ + [2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */ + [3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */ + [4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */ + [5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */ + [6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */ + [7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */ + [8] = {0, 0, 0 }, /* Reserved */ + [9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */ + [10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */ + [11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */ + [12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */ + [13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */ +}; + +/* Their name are quite regular. So I undefine them. */ +#undef ABCD +#undef BCDA +#undef CDAB +#undef DABC + +/* Init APIC of sr5690 */ +static void sr5690_apic_init(struct device *dev) +{ + u32 dword; + const apic_device_info *entry = default_apic_device_info_t; + + /* rpr6.2.(2). Write to the IOAPIC Features Enable register */ + pci_write_config32(dev, 0xF8, 0x0); + pci_write_config32(dev, 0xFC, 0x1F); + /* rpr6.2.(3). Write to the remaining interrupt routing registers */ + + /* IOAPICCMISCIND:0x3, group & swizzle of Dev 2,3,4,5 */ + dword = (entry[2].group | entry[2].swizzle << 4) << 0 | + (entry[3].group | entry[3].swizzle << 4) << 8 | + (entry[4].group | entry[4].swizzle << 4) << 16 | + (entry[5].group | entry[5].swizzle << 4) << 24; + pci_write_config32(dev, 0xF8, 0x3); + pci_write_config32(dev, 0xFC, dword); + + /* IOAPICCMISCIND:0x4, group & swizzle of Dev 6,7,9,10 */ + dword = (entry[6].group | entry[6].swizzle << 4) << 0 | + (entry[7].group | entry[7].swizzle << 4) << 8 | + (entry[9].group | entry[9].swizzle << 4) << 16 | + (entry[10].group | entry[10].swizzle << 4) << 24; + pci_write_config32(dev, 0xF8, 0x4); + pci_write_config32(dev, 0xFC, dword); + + /* IOAPICCMISCIND:0x5, group & swizzle of Dev 11,12,13 */ + dword = (entry[11].group | entry[11].swizzle << 4) << 0 | + (entry[12].group | entry[12].swizzle << 4) << 8 | + (entry[13].group | entry[13].swizzle << 4) << 16; + pci_write_config32(dev, 0xF8, 0x5); + pci_write_config32(dev, 0xFC, dword); + + /* IOAPICCMISCIND:0x6, pin map of dev 2,3,4,5 */ + dword = entry[2].pin | + entry[3].pin << 8 | + entry[4].pin << 16| + entry[5].pin << 24; + pci_write_config32(dev, 0xF8, 0x6); + pci_write_config32(dev, 0xFC, dword); + + /* IOAPICCMISCIND:0x7, pin map of dev 6,7,8,9 */ + dword = entry[6].pin | + entry[7].pin << 8 | + entry[8].pin << 16| + entry[9].pin << 24; + pci_write_config32(dev, 0xF8, 0x7); + pci_write_config32(dev, 0xFC, dword); + + /* IOAPICCMISCIND:0x8, pin map of dev 10,11,12,13 */ + dword = entry[10].pin | + entry[11].pin << 8 | + entry[12].pin << 16| + entry[13].pin << 24; + pci_write_config32(dev, 0xF8, 0x8); + pci_write_config32(dev, 0xFC, dword); + + /* IOAPICCMISCIND:0x9, pin map of ht, iommu */ + dword = entry[0].pin | entry[1].pin << 8; + pci_write_config32(dev, 0xF8, 0x9); + pci_write_config32(dev, 0xFC, dword); + + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + /* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the + * 2nd one. We need to check if it also is on your board. */ + setup_ioapic(dword, 1); +} + +static void pcie_init(struct device *dev) +{ + /* Enable pci error detecting */ + u32 dword; + + printk(BIOS_INFO, "pcie_init in sr5650_ht.c\n"); + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1 << 8); /* System error enable */ + dword |= (1 << 30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + + /* + * 1 is APIC enable + * 18 is enable nb to accept A4 interrupt request from SB. + */ + dword = pci_read_config32(dev, 0x4C); + dword |= 1 << 1 | 1 << 18; /* Clear possible errors */ + pci_write_config32(dev, 0x4C, dword); + + sr5690_apic_init(dev); +} + +static void sr5690_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void sr5690_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = sr5690_read_resource, + .set_resources = sr5690_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pcie_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; Added: trunk/src/southbridge/amd/sr5650/pcie.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/pcie.c Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,812 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <delay.h> +#include "sr5650.h" +#include "cmn.h" + +/*------------------------------------------------ +* Global variable +------------------------------------------------*/ +PCIE_CFG AtiPcieCfg = { + PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */ + 0, /* ResetReleaseDelay */ + 0, /* Gfx0Width */ + 0, /* Gfx1Width */ + 0, /* GfxPayload */ + 0, /* GppPayload */ + 0, /* PortDetect, filled by GppSbInit */ + 0, /* PortHp */ + 0, /* DbgConfig */ + 0, /* DbgConfig2 */ + 0, /* GfxLx */ + 0, /* GppLx */ + 0, /* NBSBLx */ + 0, /* PortSlotInit */ + 0, /* Gfx0Pwr */ + 0, /* Gfx1Pwr */ + 0 /* GppPwr */ +}; + +static void ValidatePortEn(device_t nb_dev); + +static void ValidatePortEn(device_t nb_dev) +{ +} + +/***************************************************************** +* Compliant with CIM_33's PCIEPowerOffGppPorts +* Power off unused GPP lines +*****************************************************************/ +static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) +{ + u32 reg; + u16 state_save; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + u16 state = cfg->port_enable; + + if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) + state &= AtiPcieCfg.PortDetect; + state = ~state; + state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7); + state_save = state << 17; + state &= !(AtiPcieCfg.PortHp); + reg = nbmisc_read_index(nb_dev, 0x0c); + reg |= state; + nbmisc_write_index(nb_dev, 0x0c, reg); + + reg = nbmisc_read_index(nb_dev, 0x08); + reg |= state_save; + nbmisc_write_index(nb_dev, 0x08, reg); + + if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES) + && !(AtiPcieCfg. + Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS + + PCIE_GFX_COMPLIANCE))) { + } + /* step 3 Power Down Control for Southbridge */ + reg = nbpcie_p_read_index(dev, 0xa2); + + switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */ + case 1: + nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e); + break; + case 2: + nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c); + break; + default: + break; + } +} + +/********************************************************************** +**********************************************************************/ +static void switching_gpp1_configurations(device_t nb_dev, device_t sb_dev) +{ + u32 reg; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + /* 4.3.3.1.1.1.step1. Asserts PCIE-GPP1 global reset */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg |= 1 << 15; + nbmisc_write_index(nb_dev, 0x8, reg); + + /* 4.3.3.1.1.1.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP1 core */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg |= 1 << 28; + nbmisc_write_index(nb_dev, 0x26, reg); + + /* 4.3.3.1.1.1.step3. Programs PCIE-GPP1 to be desired port configuration 8:8 or 16:0. */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg &= ~(1 << 8); /* clean */ + reg |= cfg->gpp1_configuration << 8; + nbmisc_write_index(nb_dev, 0x8, reg); + + /* 4.3.3.1.1.1.step4. Wait for 2ms */ + mdelay(1); + + /* 4.3.3.1.1.1.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP1 core */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg &= ~(1 << 28); + nbmisc_write_index(nb_dev, 0x26, reg); + + /* 4.3.3.1.1.1.step6. De-asserts PCIE-GPP1 global reset */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg &= ~(1 << 15); + nbmisc_write_index(nb_dev, 0x8, reg); + + /* Follow the procedure for PCIE-GPP1 common initialization and + * link training sequence. */ +} + +/********************************************************************** +**********************************************************************/ +static void switching_gpp2_configurations(device_t nb_dev, device_t sb_dev) +{ + u32 reg; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + /* 4.3.3.1.1.2.step1. Asserts PCIE-GPP2 global reset */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg |= 1 << 13; + nbmisc_write_index(nb_dev, 0x8, reg); + + /* 4.3.3.1.1.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP2 core */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg |= 1 << 29; + nbmisc_write_index(nb_dev, 0x26, reg); + + /* 4.3.3.1.1.2.step3. Programs PCIE-GPP2 to be desired port configuration 8:8 or 16:0. */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg &= ~(1 << 9); /* clean */ + reg |= (cfg->gpp2_configuration & 1) << 9; + nbmisc_write_index(nb_dev, 0x8, reg); + + /* 4.3.3.1.1.2.step4. Wait for 2ms */ + mdelay(2); + + /* 4.3.3.1.1.2.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP2 core */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg &= ~(1 << 29); + nbmisc_write_index(nb_dev, 0x26, reg); + + /* 4.3.3.1.1.2.step6. De-asserts PCIE-GPP2 global reset */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg &= ~(1 << 13); + nbmisc_write_index(nb_dev, 0x8, reg); + + /* Follow the procedure for PCIE-GPP2 common initialization and + * link training sequence. */ +} +static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev) +{ + u32 reg; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + /* 4.3.3.2.3.2.step1. Asserts PCIE-GPP3a global reset. */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg |= 1 << 31; + nbmisc_write_index(nb_dev, 0x8, reg); + /* 4.3.3.2.3.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg |= 1 << 30; + nbmisc_write_index(nb_dev, 0x26, reg); + /* 4.3.3.2.3.2.step3. Programs the desired PCIE-GPP3a configuration. */ + reg = nbmisc_read_index(nb_dev, 0x67); + reg &= ~0x1F; /* clean */ + reg |= cfg->gpp3a_configuration; + nbmisc_write_index(nb_dev, 0x67, reg); + /* 4.3.3.2.3.2.step4. Programs PCIE-GPP3a Line Director. */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg &= 0xF0000000; /* TODO:Lane reversed. */ + switch (cfg->gpp3a_configuration) { + case 0xB: /* 1:1:1:1:1:1 */ + reg |= 0x2AA3554; + break; + case 0x1: /* 4:2:0:0:0:0 */ + reg |= 0x055B000; + break; + case 0x2: /* 4:1:1:0:0:0 */ + reg |= 0x215B400; + break; + case 0xC: /* 2:2:2:0:0:0 */ + reg |= 0xFF0BAA0; + break; + case 0xA: /* 2:2:1:1:0:0 */ + reg |= 0x215B400; + break; + case 0x4: /* 2:1:1:1:1:0 */ + reg |= 0xFF0BAA0; + break; + default: /* shouldn't be here. */ + printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); + break; + } + nbmisc_write_index(nb_dev, 0x26, reg); + /* 4.3.3.2.3.2.step5. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */ + reg = nbmisc_read_index(nb_dev, 0x26); + reg &= ~(1 << 30); + nbmisc_write_index(nb_dev, 0x26, reg); + /* 4.3.3.2.3.2.step6. De-asserts PCIE-GPP3a global reset. */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg &= ~(1 << 31); + nbmisc_write_index(nb_dev, 0x8, reg); +} + +/***************************************************************** +* The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration +* Space to a 256MB range within the first 4GB of addressable memory. +*****************************************************************/ +void enable_pcie_bar3(device_t nb_dev) +{ + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); + set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ + set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); + + pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */ + pci_write_config32(nb_dev, 0x20, 0x00000000); + set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); +} + +/***************************************************************** +* We should disable bar3 when we want to exit sr5650_enable, because bar3 will be +* remapped in set_resource later. +*****************************************************************/ +void disable_pcie_bar3(device_t nb_dev) +{ + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); + pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ + set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ + ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); +} + +/* +*/ +void init_gen2(device_t nb_dev, device_t dev, u8 port) +{ + u32 reg, val; + /* for A11 (0x89 == 0) */ + reg = 0x34; + if (port <= 3){ + val = 1<<5; + }else{ + val = 1<<31; + if (port >= 9 ) + reg = 0x39; + } + + /* todo: check for rev > a11 + switch (port) { + case 2; + reg = 0x34; + val = 1<<5; + break; + case 3: + reg = 0x22; + val = 1<<6; + break; + case 4: + reg = 0x34; + val = 1<<31; + break; + case 5: + case 6: + reg = 0x39; + val = 1<<31; + break; + case 7..9: + reg = 0x37; + val = 1<<port; + break; + case 10: + reg = 0x22; + val = 1<<5; + break; + default: + reg = 0; + break; + } + */ + set_pcie_enable_bits(dev, 0xA4, 0x1, 0x1); + pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2*/ + set_nbmisc_enable_bits(nb_dev, reg, val, val); +} + + +/* Alternative to default CPL buffer count */ +const u8 pGpp420000[] = {0x38, 0x1C}; +const u8 pGpp411000[] = {0x38, 0x0E, 0x0E}; +const u8 pGpp222000[] = {0x1C, 0x1C, 0x1C}; +const u8 pGpp221100[] = {0x1C, 0x1C, 0x0E, 0x0E}; +const u8 pGpp211110[] = {0x1C, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E}; +const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E}; + +/* + * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP3a Ports + * PcieLibCplBufferAllocation + */ +static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) +{ + u8 dev_index; + u8 *slave_cpl; + u8 value; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + dev_index = dev->path.pci.devfn >> 3; + if (dev_index < 4 || dev_index > 0xa) { + return; + } + + switch (cfg->gpp3a_configuration) { + case 0x1: /* 4:2:0:0:0:0 */ + slave_cpl = (u8 *)&pGpp420000; + break; + case 0x2: /* 4:1:1:0:0:0 */ + slave_cpl = (u8 *)&pGpp411000; + break; + case 0xC: /* 2:2:2:0:0:0 */ + slave_cpl = (u8 *)&pGpp222000; + break; + case 0xA: /* 2:2:1:1:0:0 */ + slave_cpl = (u8 *)&pGpp221100; + break; + case 0x4: /* 2:1:1:1:1:0 */ + slave_cpl = (u8 *)&pGpp211110; + break; + case 0xB: /* 1:1:1:1:1:1 */ + slave_cpl = (u8 *)&pGpp111111; + break; + default: /* shouldn't be here. */ + printk(BIOS_DEBUG, "buggy gpp3a_configuration\n"); + break; + } + + value = slave_cpl[dev_index - 4]; + if (value != 0) { + set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); + set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); + } +} + +/* + * Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports + * PcieLibCplBufferAllocation + */ +static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev) +{ + u8 gpp_cfg; + u8 value; + u8 dev_index; + + dev_index = dev->path.pci.devfn >> 3; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + if (dev_index < 4) { + gpp_cfg = cfg->gpp1_configuration; + } else if (dev_index > 0xa) { + gpp_cfg = cfg->gpp2_configuration; + } else { + return; + } + + if (gpp_cfg == 0) { + /* Configuration 16:0, leave the default value */ + } else if (gpp_cfg == 1) { + /* Configuration 8:8 */ + value = 0x60; + set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); + set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); + } else { + printk(BIOS_DEBUG, "buggy gpp configuration\n"); + } +} + +#if 0 /* BTS report error without this function. But some board + * fail to boot. Leave it here for future debug. */ + +/* + * Enable LCLK clock gating + */ +static void EnableLclkGating(device_t dev) +{ + u8 port; + u32 reg = 0; + u32 mask = 0; + u32 value = 0; + device_t nb_dev = dev_find_slot(0, 0); + device_t clk_f1= dev_find_slot(0, 1); + + port = dev->path.pci.devfn >> 3; + switch (port) { + //PCIE_CORE_INDEX_GPP1 + case 2: + case 3: + reg = 0x94; + mask = 1 << 16; + break; + + //PCIE_CORE_INDEX_GPP2 + case 11: + case 12: + reg = 0xE8; + value = 1 << 28; + break; + + //PCIE_CORE_INDEX_GPP3a + case 4 ... 7: + case 9: + case 10: + reg = 0xE8; + value = 1 << 31; + break; + + //PCIE_CORE_INDEX_GPP3b; + case 13: + reg = 0xE8; + value = 1 << 25; + break; + + //PCIE_CORE_INDEX_SB; + case 8: + reg = 0x94; + mask = 1 << 24; + break; + default: + break; + } + /* enable access func1 */ + set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0); + set_nbcfg_enable_bits(clk_f1, reg, mask, value); +} +#endif + +/***************************************** +* Compliant with CIM_33's PCIEGPPInit +* nb_dev: +* root bridge struct +* dev: +* p2p bridge struct +* port: +* p2p bridge number, 4-10 +*****************************************/ +void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) +{ + u32 gpp_sb_sel = 0; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); + switch (port) { + case 2: + case 3: + gpp_sb_sel = PCIE_CORE_INDEX_GPP1; + break; + case 4 ... 7: + case 9: + case 10: + gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; + break; + case 8: + gpp_sb_sel = PCIE_CORE_INDEX_SB; + break; + case 11: + case 12: + gpp_sb_sel = PCIE_CORE_INDEX_GPP2; + break; + case 13: + gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; + break; + } + + /* Init common Core registers */ + set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19, + 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19); + if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) { + set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22); + /* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */ + gpp3a_cpl_buf_alloc(nb_dev, dev); + } + if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) { + gpp12_cpl_buf_alloc(nb_dev, dev); + } + set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11); + set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830); + // PCIE should not ignore malformed packet error or ATS request + set_pcie_enable_bits(dev, 0x70, 1 << 12, 0); + //Step 14.1: Advertising Hot Plug Capabilities + set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault + + set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0); + + /* init GPP core */ + /* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */ + pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0); + /* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */ + set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); + /* 4.4.2.step13.3. Enable slave ordering rules */ + set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8); + /* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */ + set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10); + /* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs + during L1 so that Tx Clk can be turned off. */ + set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx + /* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to + prevent LC from going to L1 when there are outstanding completions.*/ + set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15); + /* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent + lc to go to from L0 to Rcv_L0s if L1 is armed. */ + set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); + /* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */ + set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27); + /* 4.4.2.step13.9. Prevents Electrical Idle from causing a + transition from Rcv_L0 to Rcv_L0s. */ + set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20); + /* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if + it has already acknowledged a request to go + to L1 but it has not transitioned there yet. */ + /* seems the same as step13.7 */ + set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11); + /* 4.4.2.step13.11. Transmits FTS before Recovery. */ + set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9); + /* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin + for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */ + //if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */ + set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109); + /* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/ + set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4); + /* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when + turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical + Idle. + NOTE: LC still uses Inferred Electrical Idle. */ + set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14); + /* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon + exit from Electrical Idle, rather than being tied to PLL_PDNB. */ + set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25); + + /* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency. + TX L0s exit latency to be 100b: 512ns to less than 1us; + L1 exit latency to be 011b: 4us to less than 8us. + For Hot-Plug Slots: Advertise TX L0s and L1 exit latency. + TX L0s exit latency to be 110b: 2us to 4us. + L1 exit latency to be 111b: more than 64us.*/ + //set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */ + set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */ + /* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to + workaround credit control issue on PM_NAK + message of SB700 and SB800. */ + /* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */ + if (port == 8) { + set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23); + set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1); + } + /* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */ + /* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/ + set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0); + /* Disables GEN2 capability of the device. + * RPR typo- it says enable but the bit setting says disable. + * Disable it here and we enable it later. */ + set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0); + /* 4.4.2.step13.21. */ + /* 4.4.2.step13.22 */ + /* Enable native PME. */ + set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3); + /* This bit when set indicates that the PCIe Link associated with this port + is connected to a slot. */ + pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8); + /* This bit when set indicates that this slot is capable of supporting + Hot-Plug operations. */ + set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6); + /* Enables flushing of TLPs when Data Link is down. */ + set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); + + /* 4.4.2.step14. Server Class Hot Plug Feature */ + /* 4.4.2 step14.1: Advertising Hot Plug Capabilities */ + /* 4.4.2.step14.2: Firmware Upload */ + /* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */ + /* step14.4 */ + /* step14.5 */ + /* skip */ + + /* CIMx LPC Deadlock workaround - Enable Memory Write Map*/ + if (gpp_sb_sel == PCIE_CORE_INDEX_SB) { + set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9); + set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26); + } + + /* This CPL setup requires more than this one register and should be done in gpp_core. + * The additional setup is for the different revisions. */ + + /* CIMx CommonPortInit settings that are not set above. */ + pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */ + + if ( port == 8 ) + set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23); + + /* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */ + init_gen2(nb_dev, dev, port); + set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29); + set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0); + set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0); + + /* Hotplug Support - bit5 + bit6 capable and surprise */ + pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60); + + /* Set interrupt pin info 0x3d */ + pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8); + + /* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq + The RPR is wrong - this is not a PCIEND_P register */ + pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3); + + /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */ + if ( port != 8) + set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2); + + /* Not sure about this PME setup */ + /* Native PME */ + set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */ + + /* PME Enable */ + pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */ + + /* 4.4.3 Training for GPP devices */ + /* init GPP */ + switch (port) { + case 2: + case 3: + case 4: /* GPP_SB */ + case 5: + case 6: + case 7: + case 9: /*GPP*/ + case 10: + case 11: + case 12: + case 13: + /* 4.4.2.step13.5. Blocks DMA traffic during C3 state */ + set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); + /* Enabels TLP flushing */ + set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19); + + /* check port enable */ + if (cfg->port_enable & (1 << port)) { + PcieReleasePortTraining(nb_dev, dev, port); + if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { + u8 res = PcieTrainPort(nb_dev, dev, port); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); + if (res) { + AtiPcieCfg.PortDetect |= 1 << port; + } + } + } + break; + case 8: /* SB */ + break; + default: + break; + } + + /* Re-enable RC ordering logic after training (from CIMx)*/ + set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0); + + /* Advertising Hot Plug Capabilities */ + pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B); + + /* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */ + /* Set Slot Number */ + pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19); + + /* Set Slot present 0x5A*/ + pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24); + + //PCIE-GPP1 TXCLK Clock Gating In L1 Late Core sttting - Maybe move somewhere else? */ + set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0); + /* Enable powering down PLLs in L1 or L23 Ready states. + * Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */ + set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009); + /* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */ + set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6); + + /* Step 21: Register Locking PCIE Misc. Late Core sttting - Must move somewhere do PciInitLate FIXME */ + /* Lock HWInit Register */ + //set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 0, 1 << 0); + + /* Step 27: LCLK Gating */ + //EnableLclkGating(dev); + + /* Set Common Clock */ + /* If dev present, set PcieCapPtr+0x10, BIT6); + * set dev 0x68,bit 6 + * retrain link, set dev, 0x68 bit 5; + * wait dev 0x6B bit3 clear + */ + + if (port == 8){ + PciePowerOffGppPorts(nb_dev, dev, port); /* , This should be run for all ports that are not hotplug and don't detect devices */ + } +} + +/***************************************** +* Compliant with CIM_33's PCIEConfigureGPPCore +*****************************************/ +void config_gpp_core(device_t nb_dev, device_t sb_dev) +{ + u32 reg; + struct southbridge_amd_sr5650_config *cfg = + (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; + + reg = nbmisc_read_index(nb_dev, 0x20); + if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP) + reg &= 0xfffffffd; /* set bit1 = 0 */ + else + reg |= 0x2; /* set bit1 = 1 */ + nbmisc_write_index(nb_dev, 0x20, reg); + + /* Must perform PCIE-GPP1, GPP2, GPP3a global reset anyway */ + reg = nbmisc_read_index(nb_dev, 0x8); + reg |= (1 << 31) | (1 << 15) | (1 << 13); //asserts + nbmisc_write_index(nb_dev, 0x8, reg); + reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-aserts + nbmisc_write_index(nb_dev, 0x8, reg); + + reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */ + if (cfg->gpp3a_configuration != (reg & 0x1F)) + switching_gpp3a_configurations(nb_dev, sb_dev); + reg = nbmisc_read_index(nb_dev, 0x8); /* get MULTIPORT_CONFIG_GPP1 MULTIPORT_CONFIG_CONFIG_GPP2 at bit 8,9 */ + if ((cfg->gpp1_configuration << 8) != (reg & (1 << 8))) + switching_gpp1_configurations(nb_dev, sb_dev); + if ((cfg->gpp2_configuration << 9) != (reg & (1 << 9))) + switching_gpp2_configurations(nb_dev, sb_dev); + ValidatePortEn(nb_dev); +} + +/***************************************** +* Compliant with CIM_33's PCIEMiscClkProg +*****************************************/ +void pcie_config_misc_clk(device_t nb_dev) +{ + u32 reg; + //struct bus pbus; /* fake bus for dev0 fun1 */ + + reg = pci_read_config32(nb_dev, 0x4c); + reg |= 1 << 0; + pci_write_config32(nb_dev, 0x4c, reg); + +#if 0 /* TODO: Check the mics clock later. */ + if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) { + /* TXCLK Clock Gating */ + set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0); + set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); + set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); + + /* LCLK Clock Gating */ + reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg &= ~(1 << 16); + pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + } + + if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { + /* TXCLK Clock Gating */ + set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4); + set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22); + set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6); + + /* LCLK Clock Gating */ + reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg &= ~(1 << 24); + pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + } +#endif + + reg = pci_read_config32(nb_dev, 0x4c); + reg &= ~(1 << 0); + pci_write_config32(nb_dev, 0x4c, reg); +} Added: trunk/src/southbridge/amd/sr5650/rev.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/rev.h Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SR5650_REV_H__ +#define __SR5650_REV_H__ + +#define REV_SR5650_A11 0 +#define REV_SR5650_A12 1 +#define REV_SR5650_A21 2 + +#endif /* __SR5650_REV_H__ */ Added: trunk/src/southbridge/amd/sr5650/sr5650.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/sr5650.c Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,432 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <delay.h> +#include "sr5650.h" +#include "cmn.h" + +/* + * extern function declaration + */ +extern void set_pcie_dereset(void); +extern void set_pcie_reset(void); + +/* extension registers */ +u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) +{ + /*get BAR3 base address for nbcfg0x1c */ + u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; + printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + dev->path.pci.devfn); + addr |= dev->bus->secondary << 20 | /* bus num */ + dev->path.pci.devfn << 12 | reg; + return *((u32 *) addr); +} + +void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val) +{ + u32 reg_old, reg; + + /*get BAR3 base address for nbcfg0x1c */ + u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; + /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + dev->path.pci.devfn);*/ + addr |= dev->bus->secondary << 20 | /* bus num */ + dev->path.pci.devfn << 12 | reg_pos; + + reg = reg_old = *((u32 *) addr); + reg &= ~mask; + reg |= val; + if (reg != reg_old) { + *((u32 *) addr) = reg; + } +} + +u32 nbpcie_p_read_index(device_t dev, u32 index) +{ + return nb_read_index((dev), NBPCIE_INDEX, (index)); +} + +void nbpcie_p_write_index(device_t dev, u32 index, u32 data) +{ + nb_write_index((dev), NBPCIE_INDEX, (index), (data)); +} + +u32 nbpcie_ind_read_index(device_t nb_dev, u32 index) +{ + return nb_read_index((nb_dev), NBPCIE_INDEX, (index)); +} + +void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data) +{ + nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); +} + +/*********************************************************** +* To access bar3 we need to program PCI MMIO 7 in K8. +* in_out: +* 1: enable/enter k8 temp mmio base +* 0: disable/restore +***********************************************************/ +void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) +{ + /* K8 Function1 is address map */ + device_t k8_f1; + device_t np = dev_find_slot(0, PCI_DEVFN(0x19, 1)); + u16 node; + + for (node = 0; node < CONFIG_MAX_PHYSICAL_CPUS; node++) { + k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); + if (!k8_f1) { + break; + } + + if (in_out) { + /* Fill MMIO limit/base pair. */ + pci_write_config32(k8_f1, 0xbc, + (((pcie_base_add + 0x10000000 - + 1) >> 8) & 0xffffff00) | 0x8 | (np ? 2 << 4 : 0 << 4)); + pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); + pci_write_config32(k8_f1, 0xb4, + ((mmio_base_add + 0x10000000 - + 1) >> 8) | (np ? 2 << 4 : 0 << 4)); + pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); + } else { + pci_write_config32(k8_f1, 0xb8, 0); + pci_write_config32(k8_f1, 0xbc, 0); + pci_write_config32(k8_f1, 0xb0, 0); + pci_write_config32(k8_f1, 0xb4, 0); + } + } +} + +void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) +{ + switch (port) { + case 2: /* GPP1, bit4-5 */ + case 3: + set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, + 1 << (port + 2), 0 << (port + 2)); + break; + case 4: /* GPP3a, bit20-24 */ + case 5: + case 6: + case 7: + set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, + 1 << (port + 17), 0 << (port + 17)); + break; + case 9: /* GPP3a, bit25,26 */ + case 10: + set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, + 1 << (port + 16), 0 << (port + 16)); + break; + case 11: /* GPP2, bit6-7 */ + case 12: + set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, + 1 << (port - 5), 0 << (port - 5)); + break; + case 13: /* GPP3b, bit4 of NBMISCIND:0x2A */ + set_nbmisc_enable_bits(nb_dev, 0x2A, + 1 << 4, 0 << 4); + break; + } +} + +/******************************************************************************************************** +* Output: +* 0: no device is present. +* 1: device is present and is trained. +********************************************************************************************************/ +u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) +{ + u16 count = 5000; + u32 lc_state, reg, current_link_width, lane_mask; + u8 current, res = 0; + u32 gpp_sb_sel = 0; + + switch (port) { + case 2: + case 3: + gpp_sb_sel = PCIE_CORE_INDEX_GPP1; + break; + case 4 ... 7: + case 9: + case 10: + gpp_sb_sel = PCIE_CORE_INDEX_GPP3a; + break; + case 11: + case 12: + gpp_sb_sel = PCIE_CORE_INDEX_GPP2; + break; + case 13: + gpp_sb_sel = PCIE_CORE_INDEX_GPP3b; + break; + } + + while (count--) { + udelay(40200); + lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ + printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", + port, lc_state); + current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ + + switch (current) { + /* 0x00-0x04 means no device is present */ + case 0x06: + /* read back current link width [6:4]. */ + current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; + /* 4 means 7:4 and 15:12 + * 3 means 7:2 and 15:10 + * 2 means 7:1 and 15:9 + * egnoring the reversal case + */ + lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; + reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel); + reg |= lane_mask << 8 | lane_mask; + /* NOTE: See the comments in rs780_pcie.c + * switching_gppsb_configurations + * In CIMx 4.5.0 and RPR, 4c is done before 5 & 6. + * But in this way, a x4 device in port B (dev 4) of + * Configuration B can only be detected as x1, instead + * of x4. When the port B is being trained, the + * LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1. + * We have to set the PCIEIND:0x65 as 0xE0E0 and reset + * the slot. Then the card seems to work in x1 mode. + */ + reg = 0xE0E0; /*I think that the lane_mask calc above is wrong, and this can't be hardcoded because the configuration changes.*/ + nbpcie_ind_write_index(nb_dev, 0x65 | gpp_sb_sel, reg); + printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", + current_link_width, lane_mask); + set_pcie_reset(); + mdelay(1); + set_pcie_dereset(); + break; + case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */ + res = 1; + count = 0; + break; + case 0x10: + reg = + pci_ext_read_config32(nb_dev, dev, + PCIE_VC0_RESOURCE_STATUS); + printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); + /* check bit1 */ + if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ + /* set bit8=1, bit0-2=bit4-6 */ + u32 tmp; + reg = + nbpcie_p_read_index(dev, + PCIE_LC_LINK_WIDTH); + tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + reg &= 0xfff8; /* clear bit0-2 */ + reg += tmp; /* merge */ + reg |= 1 << 8; + count++; /* CIM said "keep in loop"? */ + } else { + res = 1; + count = 0; + } + break; + default: + /* CIMx Unknown Workaround - There is a device that won't train. Try to reset it. */ + /* if there are no device resets and nothing works, CIMx does a cf9 system reset (yikes!) */ + set_pcie_reset(); + mdelay(1); + set_pcie_dereset(); + res = 0; + count = 0; /* break loop */ + break; + } + } + return res; +} + +/* +* Compliant with CIM_33's ATINB_SetToms. +* Set Top Of Memory below and above 4G. +*/ +void sr5650_set_tom(device_t nb_dev) +{ + extern u64 uma_memory_base; + + /* set TOM */ + pci_write_config32(nb_dev, 0x90, uma_memory_base); +} + +u32 get_vid_did(device_t dev) +{ + return pci_read_config32(dev, 0); +} + +void sr5650_nb_pci_table(device_t nb_dev) +{ /* NBPOR_InitPOR function. */ + u8 temp8; + u16 temp16; + u32 temp32; + + /* Program NB PCI table. */ + temp16 = pci_read_config16(nb_dev, 0x04); + printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); + temp32 = pci_read_config32(nb_dev, 0x84); + printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); + //Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + //Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation + pci_write_config8(nb_dev, 0x4c, 0x42); + temp8 = pci_read_config8(nb_dev, 0x4e); + temp8 |= 0x05; /* BAR1_ENABLE */ + pci_write_config8(nb_dev, 0x4e, temp8); + + temp32 = pci_read_config32(nb_dev, 0x4c); + printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); + + /* disable GFX debug. */ + temp8 = pci_read_config8(nb_dev, 0x8d); + temp8 &= ~(1<<1); + pci_write_config8(nb_dev, 0x8d, temp8); + + /* set temporary NB TOM to 0x40000000. */ + sr5650_set_tom(nb_dev); + + /* Program NB HTIU table. */ + //set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9); + set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202); + //set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001); + set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27); + set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000); + set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3); + set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31)); + set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10); + set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28); +} + +/*********************************************** +* 0:00.0 NBCFG : +* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default +* 0:01.0 P2P Internal: +* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 +* case 0 will be called twice, one is by cpu in hypertransport.c line458, +* the other is by sr5650. +***********************************************/ +void sr5650_enable(device_t dev) +{ + device_t nb_dev = 0, sb_dev = 0; + int dev_ind; + + printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); + nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!nb_dev) { + die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n"); + /* NOT REACHED */ + } + + /* sb_dev (dev 8) is a bridge that links to southbridge. */ + sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + if (!sb_dev) { + die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n"); + /* NOT REACHED */ + } + + dev_ind = dev->path.pci.devfn >> 3; + switch (dev_ind) { + case 0: /* bus0, dev0, fun0; */ + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); + enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ + + config_gpp_core(nb_dev, sb_dev); + sr5650_gpp_sb_init(nb_dev, sb_dev, 8); + + sr5650_nb_pci_table(nb_dev); + break; + + case 2: /* bus0, dev2,3 GPP1 */ + case 3: + printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, + (dev->enabled ? 0 : 1) << dev_ind); + if (dev->enabled) + sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Note, dev 2,3 are generic PCIe ports. */ + break; + case 4: /* bus0, dev4-7, four GPP3a */ + case 5: + case 6: + case 7: + enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ + printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", + dev->enabled); + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, + (dev->enabled ? 0 : 1) << dev_ind); + if (dev->enabled) + sr5650_gpp_sb_init(nb_dev, dev, dev_ind); + break; + case 8: /* bus0, dev8, SB */ + printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); + set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, + (dev->enabled ? 1 : 0) << 6); + if (dev->enabled) + sr5650_gpp_sb_init(nb_dev, dev, dev_ind); + disable_pcie_bar3(nb_dev); + break; + case 9: /* bus 0, dev 9,10, GPP3a */ + case 10: + printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", + dev->enabled); + enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), + (dev->enabled ? 0 : 1) << (7 + dev_ind)); + if (dev->enabled) + sr5650_gpp_sb_init(nb_dev, dev, dev_ind); + /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ + break; + case 11: + case 12: /* bus 0, dev 11,12, GPP2 */ + printk(BIOS_INFO, "Bus-0, Dev-11,12, Fun-0. enable=%d\n", dev->enabled); + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), + (dev->enabled ? 0 : 1) << (7 + dev_ind)); + if (dev->enabled) + sr5650_gpp_sb_init(nb_dev, dev, dev_ind); + break; + case 13: /* bus 0, dev 12, GPP3b */ + set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), + (dev->enabled ? 0 : 1) << (7 + dev_ind)); + if (dev->enabled) + sr5650_gpp_sb_init(nb_dev, dev, dev_ind); + break; + default: + printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); + } +} + +struct chip_operations southbridge_amd_sr5650_ops = { + CHIP_NAME("ATI SR5650") + .enable_dev = sr5650_enable, +}; Added: trunk/src/southbridge/amd/sr5650/sr5650.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sr5650/sr5650.h Sun Mar 27 18:39:58 2011 (r6462) @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SR5650_H__ +#define __SR5650_H__ + +#include <stdint.h> +#include <device/pci_ids.h> +#include "chip.h" +#include "rev.h" + +typedef struct __PCIE_CFG__ { + u16 Config; + u8 ResetReleaseDelay; + u8 Gfx0Width; + u8 Gfx1Width; + u8 GfxPayload; + u8 GppPayload; + u16 PortDetect; + u8 PortHp; /* hot plug */ + u16 DbgConfig; + u32 DbgConfig2; + u8 GfxLx; + u8 GppLx; + u8 NBSBLx; + u8 PortSlotInit; + u8 Gfx0Pwr; + u8 Gfx1Pwr; + u8 GppPwr; +} PCIE_CFG; + +/* PCIE config flags */ +#define PCIE_DUALSLOT_CONFIG (1 << 0) +#define PCIE_OVERCLOCK_ENABLE (1 << 1) +#define PCIE_GPP_CLK_GATING (1 << 2) +#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3) +#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4) +#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5) +#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7) +#define PCIE_GFX_CLK_GATING (1 << 11) +#define PCIE_GFX_COMPLIANCE (1 << 14) +#define PCIE_GPP_COMPLIANCE (1 << 15) + +/* -------------------- ---------------------- +* NBMISCIND + ------------------- -----------------------*/ +#define PCIE_LINK_CFG 0x8 +#define PCIE_NBCFG_REG7 0x37 +#define STRAPS_OUTPUT_MUX_7 0x67 +#define STRAPS_OUTPUT_MUX_A 0x6a + +/* -------------------- ---------------------- +* PCIEIND + ------------------- -----------------------*/ +#define PCIE_CI_CNTL 0x20 +#define PCIE_LC_LINK_WIDTH 0xa2 +#define PCIE_LC_STATE0 0xa5 +#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ + +#define PCIE_CORE_INDEX_SB (0x05 << 16) /* see rpr 4.3.2.2, bdg 2.1 */ +#define PCIE_CORE_INDEX_GPP1 (0x04 << 16) +#define PCIE_CORE_INDEX_GPP2 (0x06 << 16) +#define PCIE_CORE_INDEX_GPP1_GPP2 (0x00 << 16) +#define PCIE_CORE_INDEX_GPP3a (0x07 << 16) +#define PCIE_CORE_INDEX_GPP3b (0x03 << 16) + +/* contents of PCIE_VC0_RESOURCE_STATUS */ +#define VC_NEGOTIATION_PENDING (1 << 1) + +#define LC_STATE_RECONFIG_GPPSB 0x10 + +/* ------------------------------------------------ +* Global variable +* ------------------------------------------------- */ +extern PCIE_CFG AtiPcieCfg; + +/* ----------------- export funtions ----------------- */ +u32 nbpcie_p_read_index(device_t dev, u32 index); +void nbpcie_p_write_index(device_t dev, u32 index, u32 data); +u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); +void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); +u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); +void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); +void sr5650_set_tom(device_t nb_dev); + +void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); +void enable_pcie_bar3(device_t nb_dev); +void disable_pcie_bar3(device_t nb_dev); + +void sr5650_enable(device_t dev); +void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port); +void sr5650_gfx_init(device_t nb_dev, device_t dev, u32 port); +void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev); +void config_gpp_core(device_t nb_dev, device_t sb_dev); +void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); +u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); +void pcie_config_misc_clk(device_t nb_dev); +void fam10_optimization(void); +void disable_pcie_bridge(void); +u32 get_vid_did(device_t dev); +void sr5650_nb_pci_table(device_t nb_dev); +void init_gen2(device_t nb_dev, device_t dev, u8 port); +#endif /* SR5650_H */

1 0

[commit] r6461 - in trunk/src/superio: . nuvoton nuvoton/wpcm450
by repository service 27 Mar '11

27 Mar '11

Author: zbao Date: Sun Mar 27 18:33:09 2011 New Revision: 6461 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6461 Log: This is for board Supermicro H8scm. The code was done by existing chips and superiotool. WPCM450 is more like an EC. SuperIO is just a part of multi-features. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/superio/nuvoton/ trunk/src/superio/nuvoton/Kconfig trunk/src/superio/nuvoton/Makefile.inc trunk/src/superio/nuvoton/wpcm450/ trunk/src/superio/nuvoton/wpcm450/Makefile.inc trunk/src/superio/nuvoton/wpcm450/chip.h trunk/src/superio/nuvoton/wpcm450/early_init.c trunk/src/superio/nuvoton/wpcm450/superio.c trunk/src/superio/nuvoton/wpcm450/wpcm450.h Modified: trunk/src/superio/Kconfig trunk/src/superio/Makefile.inc Modified: trunk/src/superio/Kconfig ============================================================================== --- trunk/src/superio/Kconfig Fri Mar 25 17:54:38 2011 (r6460) +++ trunk/src/superio/Kconfig Sun Mar 27 18:33:09 2011 (r6461) @@ -21,6 +21,7 @@ source src/superio/intel/Kconfig source src/superio/ite/Kconfig source src/superio/nsc/Kconfig +source src/superio/nuvoton/Kconfig source src/superio/renesas/Kconfig source src/superio/serverengines/Kconfig source src/superio/smsc/Kconfig Modified: trunk/src/superio/Makefile.inc ============================================================================== --- trunk/src/superio/Makefile.inc Fri Mar 25 17:54:38 2011 (r6460) +++ trunk/src/superio/Makefile.inc Sun Mar 27 18:33:09 2011 (r6461) @@ -21,6 +21,7 @@ subdirs-y += intel subdirs-y += ite subdirs-y += nsc +subdirs-y += nuvoton subdirs-y += renesas #subdirs-y += serverengines subdirs-y += smsc Added: trunk/src/superio/nuvoton/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/Kconfig Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SUPERIO_NUVOTON_WPCM450 + bool Added: trunk/src/superio/nuvoton/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/Makefile.inc Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += wpcm450 Added: trunk/src/superio/nuvoton/wpcm450/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/wpcm450/Makefile.inc Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c + Added: trunk/src/superio/nuvoton/wpcm450/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/wpcm450/chip.h Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_WPCM450_CHIP_H +#define SUPERIO_NUVOTON_WPCM450_CHIP_H + +struct chip_operations; +extern struct chip_operations superio_nuvoton_wpcm450_ops; + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct superio_nuvoton_wpcm450_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; + +#endif Added: trunk/src/superio/nuvoton/wpcm450/early_init.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/wpcm450/early_init.c Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> +#include "wpcm450.h" + +static void wpcm450_pnp_set_logical_device(u8 dev, u16 port) +{ + outb(0x7, port); + outb(dev, port+1); +} + +static void wpcm450_pnp_set_enable(u8 dev, u16 port, u8 enable) +{ + outb(0x30, port); + outb(enable, port+1); +} + +static void wpcm450_pnp_set_iobase(u8 dev, u16 port, u8 index, u16 iobase) +{ + outb(index, port); + outb((iobase>>8)&0xFF, port+1); + outb(index+1, port); + outb(iobase&0xFF, port+1); +} + +static void wpcm450_enable_dev(u8 dev, u16 port, u16 iobase) +{ + wpcm450_pnp_set_logical_device(dev, port); + wpcm450_pnp_set_enable(dev, port, 0); + if (iobase) + wpcm450_pnp_set_iobase(dev, port, PNP_IDX_IO0, iobase); + wpcm450_pnp_set_enable(dev, port, 1); +} Added: trunk/src/superio/nuvoton/wpcm450/superio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/wpcm450/superio.c Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "wpcm450.h" + +static void init(device_t dev) +{ + struct superio_nuvoton_wpcm450_config *conf = dev->chip_info; + struct resource *res0; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case WPCM450_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case WPCM450_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + case WPCM450_KBCK: + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, WPCM450_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, WPCM450_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, WPCM450_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_wpcm450_ops = { + CHIP_NAME("NUVOTON WPCM450 Super I/O") + .enable_dev = enable_dev, +}; Added: trunk/src/superio/nuvoton/wpcm450/wpcm450.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/nuvoton/wpcm450/wpcm450.h Sun Mar 27 18:33:09 2011 (r6461) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_WPCM450_WPCM450_H +#define SUPERIO_NUVOTON_WPCM450_WPCM450_H + +#define WPCM450_SP2 0x02 /* Com2 */ +#define WPCM450_SP1 0x03 /* Com1 */ +#define WPCM450_KBCK 0x06 /* Keyboard */ + +#endif

1 0

[GSoC] Coreboot Spice Payload
by Leandro Dorileo 27 Mar '11

27 Mar '11

Hi Guys! I saw coreboot was accepted as mentoring organization for GSoC this year once again. I want to participate this year again as student and I came with the idea of a Coreboot Spice Payload. I wrote a small text[1] describing the idea. I would like to hear from you what you think. I have discussed with some guys already but would like to open it a bit more. [1] - http://vps.dorilex.net/~dorileo/coreboot-spice-payload.txt Thanks.... -- Leandro Dorileo

5 7

Mainboard supported?
by Igor 27 Mar '11

27 Mar '11

Hello, I wonder if my board is supported, or by any chance, will be supported in the future? I've got the MSI G41M-P25 board. It runs with a Core2Duo Socket 775 and DDR3 RAM. The chipsets: Intel G41 and ICH7. Outputs of important commands are in the attachment. There is no visible BIOS chip on the board. When I go into the BIOS I see it's from Amercian Megatrends, v02.61 Thanks in advance! Sent to you using Uebimiau Webmail version 3.11 Developed by Dave and Todd at http://www.manvel.net and http://www.tdah.us

2 1

emulating coreboot with qemu
by pronoyc＠gmail.com 25 Mar '11

25 Mar '11

Hello, I am new to coreboot and I've been using this tutorial as guidance: http://www.coreboot.org/QEMU_Build_Tutorial I've had help from the IRC channel as well and I think it will be a good idea to get help here as well: here's the log of what I've done: 1. downloaded qemu coreboot filo libpayload 2. Built qemu 3. built libpayload > error in make menuconfig (this was definitely an ncurses.h error so the terminal graphics were the problem)

3 3

[commit] r6460 - trunk/util/superiotool
by repository service 25 Mar '11

25 Mar '11

Author: mjones Date: Fri Mar 25 17:54:38 2011 New Revision: 6460 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6460 Log: I noticed some registers of Winbond W83627DHG, which the datasheet mentions, were not dumped by superiotool. This patch adds those registers to the dump. Signed-off-by: Prakash Punnoor <prakash(a)punnoor.de> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/util/superiotool/winbond.c Modified: trunk/util/superiotool/winbond.c ============================================================================== --- trunk/util/superiotool/winbond.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/util/superiotool/winbond.c Fri Mar 25 17:54:38 2011 (r6460) @@ -214,11 +214,11 @@ {0x00,0x00,0x00,0x00,EOT}}, {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, - 0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xfe, - EOT}, + 0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8, + 0xf9,0xfa,0xfe,EOT}, {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00, 0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00, - EOT}}, + 0x00,0x00,0x00,EOT}}, {0xa, "ACPI", {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, 0xe8,0xe9,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, @@ -228,10 +228,10 @@ {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x81,0x00,0x00,EOT}}, {0xc, "PECI, SST", - {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe8,0xf1,0xfe,0xff, - EOT}, - {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00, - EOT}}, + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe8,0xf1,0xf2,0xf3, + 0xfe,0xff,EOT}, + {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x50,0x10, + 0x00,0x00,EOT}}, {EOT}}}, {0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */ {EOT}}},

1 0

[PATCH 6/7] SuperMicro H8SCM support (SuperI/O WPCM450)
by Bao, Zheng 25 Mar '11

25 Mar '11

This is for board Supermicro H8scm. The code was done by existing chips and superiotool. WPCM450 is more like an EC. SuperIO is just a part of multi-features. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>

2 1

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coreboot March 2011