coreboot November 2011

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Patch set updated for coreboot: 3c9771a k8 raminit: fix bug, improve clock selection, add clock limit for sock754
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit 3c9771aad068611f3fedb8506c4ac2faafbf250c Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 338 ++++++++++++++++------------------- 1 files changed, 156 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..f618a53 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,182 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + + #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) { - int ranks = 4; - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1680,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask;

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Patch set updated for coreboot: b4dc640 support for setting the Memory DQ Drive Strength register in amdk8 raminit
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit b4dc6403bb1ab307ab331ea1b0a985d61d9d2f4a Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index f618a53..a016fec 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2192,6 +2192,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err;

1 0

Patch set updated for coreboot: 514140a add support for setting the vt8237 to uncond. power on after loss of power
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 514140a110bb009a5d6398e9214ead97fea35324 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 4b3064a..ad0327a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -511,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43);

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Patch set updated for coreboot: 97b52bd mark w83697hf_set_clksel_48() as potentially unused
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit 97b52bd86de0d75edf466eacd71a21cd3d3aa8da Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8;

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Patch set updated for coreboot: 3466ecc add support for 1106:3188 (host controller of the old version of k8t800)
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 3466ecc1be4c32f4399ddb206a7a821eb501e575 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include <console/console.h> #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA,

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Patch merged into coreboot/master: d1f7cf4 buildgcc: Update coreboot reference toolchain to gcc 4.6.2
by gerrit＠coreboot.org 02 Nov '11

02 Nov '11

the following patch was just integrated into master: commit d1f7cf4195bf3b1cca86f2b78eb0625411479706 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Nov 1 22:39:41 2011 +0100 buildgcc: Update coreboot reference toolchain to gcc 4.6.2 In addition: - drop some unneeded patches - make the scripting support depend on SKIPPYTHON not SKIPGDB so it is possible to build GDB with and without scripting support - rename the repository checkout version of GCC trunk, not X+1 so we don't have to change it on every version upgrade. Change-Id: I1b7d5b8921187c1c1d39b04f20bb715ddba72fe8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Nov 2 10:51:01 2011, giving +2 See http://review.coreboot.org/367 for details. -gerrit

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Patch merged into coreboot/master: f07282e don't scan beyond end of CBFS
by gerrit＠coreboot.org 02 Nov '11

02 Nov '11

the following patch was just integrated into master: commit f07282efab87037a54cf0f48c0ab835cbbd39efe Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:11 2011 +0100 don't scan beyond end of CBFS Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Nov 2 10:49:24 2011, giving +2 See http://review.coreboot.org/369 for details. -gerrit

1 0

Patch set updated for coreboot: 38c32d5 some black magic for initializing the old version of the k8t800
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 38c32d5ebe74a0c7980849f5998bdc2597ea366d Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */

1 0

Patch set updated for coreboot: 75198d8 copied asus a8v-e_se to k8v-x
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/389 -gerrit commit 75198d8342a20c7e4590dcc461b25d2f4fa52a2f Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:40 2011 +0100 copied asus a8v-e_se to k8v-x Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/mainboard/asus/k8v-x/Kconfig | 73 ++++++++++ src/mainboard/asus/k8v-x/acpi_tables.c | 175 ++++++++++++++++++++++ src/mainboard/asus/k8v-x/chip.h | 22 +++ src/mainboard/asus/k8v-x/cmos.layout | 98 +++++++++++++ src/mainboard/asus/k8v-x/devicetree.cb | 97 +++++++++++++ src/mainboard/asus/k8v-x/dsdt.asl | 249 ++++++++++++++++++++++++++++++++ src/mainboard/asus/k8v-x/mainboard.c | 28 ++++ src/mainboard/asus/k8v-x/mptable.c | 116 +++++++++++++++ src/mainboard/asus/k8v-x/romstage.c | 225 +++++++++++++++++++++++++++++ 9 files changed, 1083 insertions(+), 0 deletions(-) diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig new file mode 100644 index 0000000..4975cfa --- /dev/null +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -0,0 +1,73 @@ +if BOARD_ASUS_A8V_E_SE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_WINBOND_W83627EHG + select HAVE_OPTION_TABLE + select HAVE_ACPI_TABLES + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select QRANK_DIMM_SUPPORT + select SET_FIDVID + +config MAINBOARD_DIR + string + default asus/a8v-e_se + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +endif # BOARD_ASUS_A8V_E_SE diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c new file mode 100644 index 0000000..218f3bb --- /dev/null +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer <stepan(a)openbios.org>. + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2005 Nick Barker <nick.barker9(a)btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/acpi.h" +#include <cpu/amd/model_fxx_powernow.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* If we want to use HPET timers Linux wants it in MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h new file mode 100644 index 0000000..c2849ef --- /dev/null +++ b/src/mainboard/asus/k8v-x/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout new file mode 100644 index 0000000..fc13a3c --- /dev/null +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb new file mode 100644 index 0000000..3da93fe --- /dev/null +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -0,0 +1,97 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl new file mode 100644 index 0000000..16ad92c --- /dev/null +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) +{ + #include "northbridge/amd/amdk8/util.asl" + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */ + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */ + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + }) + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } + } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } + + } + } +} diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c new file mode 100644 index 0000000..b70f396 --- /dev/null +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS A8V-E SE Mainboard") +}; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c new file mode 100644 index 0000000..999dd6c --- /dev/null +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdint.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + mptable_lintsrc(mc, bus_isa); + /* There is no extension information... */ + + /* Compute the checksums. */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c new file mode 100644 index 0000000..4e08859 --- /dev/null +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -0,0 +1,225 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI) + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "superio/winbond/w83627ehg/early_serial.c" +#include "southbridge/via/vt8237r/early_smbus.c" +#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) +#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) + +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include <reset.h> +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset \n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +#include "southbridge/via/k8t890/early_car.c" +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/dualcore/dualcore.c" +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +static void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + /* We have 24MHz input. */ + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); + /* We have GPIO for KB/MS pin. */ + reg = pnp_read_config(SERIAL_DEV, 0x2a); + pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); + /* We have all RESTOUT and even some reserved bits, too. */ + reg = pnp_read_config(SERIAL_DEV, 0x2c); + pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(ACPI_DEV); + pnp_set_logical_device(ACPI_DEV); + /* + * Set the delay rising time from PWROK_LP to PWROK_ST to + * 300 - 600ms, and 0 to vice versa. + */ + reg = pnp_read_config(ACPI_DEV, 0xe6); + pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); + /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ + reg = pnp_read_config(ACPI_DEV, 0xe4); + pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); + pnp_exit_ext_func_mode(ACPI_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ + pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ + pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ + pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ + pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ + pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ + pnp_exit_ext_func_mode(GPIO_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + + print_info("now booting... fallback\n"); + + /* Is this a CPU only reset? Or is this a secondary CPU? */ + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0. */ + /* Allow the HT devices to be found. */ + enumerate_ht_chain(); + } + + // FIXME why is this executed again? ---> + sio_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + enable_rom_decode(); + // <--- FIXME why is this executed again? + + print_info("now booting... real_main\n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + print_info("now booting... Core0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= k8t890_early_setup_ht(); + + if (needs_reset) { + print_debug("ht reset -\n"); + soft_reset(); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + enable_fid_change(); + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +}

1 0

Patch set updated for coreboot: 34309c9 adding support for the Asus K8V-X
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/390 -gerrit commit 34309c971d1f513b90b5964319378d69a40d9617 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:41 2011 +0100 adding support for the Asus K8V-X This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/k8v-x/Kconfig | 22 +++++--- src/mainboard/asus/k8v-x/acpi_tables.c | 2 +- src/mainboard/asus/k8v-x/devicetree.cb | 51 ++++++++++--------- src/mainboard/asus/k8v-x/dsdt.asl | 87 ++++--------------------------- src/mainboard/asus/k8v-x/mainboard.c | 38 +++++++++++++- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 69 +++++++++---------------- 8 files changed, 117 insertions(+), 157 deletions(-) diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..46c4ac1 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" config BOARD_ASUS_A8V_E_DELUXE bool "A8V-E Deluxe" +config BOARD_ASUS_K8V_X + bool "K8V-X" config BOARD_ASUS_M2N_E bool "M2N-E" config BOARD_ASUS_M2V @@ -61,6 +63,7 @@ endchoice source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/a8v-e_deluxe/Kconfig" +source "src/mainboard/asus/k8v-x/Kconfig" source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4975cfa..31d8564 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -1,26 +1,26 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_K8V_X config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_939 - select K8_HT_FREQ_1G_SUPPORT + select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 - select SUPERIO_WINBOND_W83627EHG + select SOUTHBRIDGE_VIA_K8T800_OLD + select SUPERIO_WINBOND_W83697HF select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select QRANK_DIMM_SUPPORT select SET_FIDVID + select K8_DQ_DRIVE_STRENGTH_0 + select VT8237R_ON_AFTER_POWER_LOSS config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/k8v-x config DCACHE_RAM_BASE hex @@ -44,7 +44,11 @@ config SB_HT_CHAIN_ON_BUS0 config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "K8V-X" + +config AGP_APERTURE_SIZE + hex + default 0x10000000 config HW_MEM_HOLE_SIZEK hex @@ -70,4 +74,4 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_K8V_X diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c index 218f3bb..571d136 100644 --- a/src/mainboard/asus/k8v-x/acpi_tables.c +++ b/src/mainboard/asus/k8v-x/acpi_tables.c @@ -30,7 +30,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" #include "northbridge/amd/amdk8/acpi.h" #include <cpu/amd/model_fxx_powernow.h> diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 3da93fe..20d1959 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,6 +1,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU + chip cpu/amd/socket_754 # CPU device lapic 0 on end # APIC end end @@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 register "fn_ctrl_lo" = "0" # Enable SB functions register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "no_int_efgh" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" device pci 0.0 on end # HT device pci f.1 on end # IDE + device pci 10.4 on end # USB2 device pci 11.0 on # LPC chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end @@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 4 end device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 end - device pnp 2e.007 off # GPIO 1 + device pnp 2e.6 off # CIR end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 + device pnp 2e.7 off # Game port/GPIO 1 end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa + device pnp 2e.8 off # MIDI/GPIO 5 end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 + device pnp 2e.009 off # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO 5 - end device pnp 2e.a off # ACPI end device pnp 2e.b on # Hardware monitor diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 16ad92c..25b7460 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) /* PCI Routing Table */ Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */ + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */ Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, @@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */ + Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */ + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */ Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */ Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */ Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, - Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */ - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */ - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */ - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */ - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */ + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */ }) - Device (PEGG) - { - Name (_ADR, 0x00020000) - Name (_UID, 0x00) - Name (_BBN, 0x02) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, - }) - } - - Device (PEX0) - { - Name (_ADR, 0x00030000) - Name (_UID, 0x00) - Name (_BBN, 0x03) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, - }) - } - - Device (PEX1) - { - Name (_ADR, 0x00030001) - Name (_UID, 0x00) - Name (_BBN, 0x04) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, - }) - } - - Device (PEX2) - { - Name (_ADR, 0x00030002) - Name (_UID, 0x00) - Name (_BBN, 0x05) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, - }) - } - - Device (PEX3) - { - Name (_ADR, 0x00030003) - Name (_UID, 0x00) - Name (_BBN, 0x06) - Name (_PRT, Package () { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */ - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, - }) - } - Device (ISA) { Name (_ADR, 0x00110000) diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index b70f396..3e294b8 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,43 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <arch/io.h> +#include "southbridge/via/vt8237r/vt8237r.h" #include "chip.h" +u32 vt8237_ide_80pin_detect(struct device *dev) +{ + device_t lpc_dev; + u16 acpi_io_base; + u32 gpio_in; + u32 res; + + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!lpc_dev) + return 0; + + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) + return 0; + + /* select function GPIO29 for pin AB9 */ + pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08); + + gpio_in = inl(acpi_io_base + 0x48); + /* bit 29 for primary port, clear if unconnected or 80-pin cable */ + res = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE; + /* bit 8 for secondary port, clear if unconnected or 80-pin cable */ + res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE; + + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); + printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); + + return res; +} + struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS K8V-X Mainboard") }; diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 999dd6c..673dfbe 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -22,7 +22,7 @@ #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include "southbridge/via/vt8237r/vt8237r.h" -#include "southbridge/via/k8t890/k8t890.h" +#include "southbridge/via/k8t890/k8x8xx.h" static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4e08859..014ce68 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83627ehg/early_serial.c" +#include "superio/winbond/w83697hf/early_serial.c" #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/mtrr/earlymtrr.c" @@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) -#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -105,52 +103,25 @@ static void sio_init(void) u8 reg; pnp_enter_ext_func_mode(SERIAL_DEV); - /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); - pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); - /* We have GPIO for KB/MS pin. */ - reg = pnp_read_config(SERIAL_DEV, 0x2a); - pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); - /* We have all RESTOUT and even some reserved bits, too. */ - reg = pnp_read_config(SERIAL_DEV, 0x2c); - pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); - - pnp_enter_ext_func_mode(ACPI_DEV); - pnp_set_logical_device(ACPI_DEV); - /* - * Set the delay rising time from PWROK_LP to PWROK_ST to - * 300 - 600ms, and 0 to vice versa. - */ - reg = pnp_read_config(ACPI_DEV, 0xe6); - pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); - /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ - reg = pnp_read_config(ACPI_DEV, 0xe4); - pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ - pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ - pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ - pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ - pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ - pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + /* 4 Mbit flash */ + reg = (reg & ~0x30) | 0x20; + /* We have 24MHz input. */ + reg &= ~0x40; + /* enable MEMW#, so flash can be written */ + reg |= 0x08; + pnp_write_config(SERIAL_DEV, 0x24, reg); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM1, DIMM2, 0, + 0, 0, 0, 0, // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; @@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // FIXME why is this executed again? ---> sio_init(); - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? @@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) soft_reset(); } - /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ + vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); @@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); + + /* this seems to be some GPIO on the SMBus--in any case, setting these + * two bits reduces the pullup impedance of the bus lines and is required + * in order to be able to read SPD info */ + smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); + smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }

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coreboot November 2011