coreboot November 2011

coreboot@coreboot.org

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Patch set updated for coreboot: f9ea54d rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit f9ea54db581318930f864e50c2ee3b3e813468da Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#ifndef __PRE_RAM__ +#include <device/device.h> +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */

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Patch set updated for coreboot: 679ebf7 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 679ebf74463706fef8d91cdf05bc816af2730d73 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333)

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Patch set updated for coreboot: da28c9e k8 raminit: fix bug, improve clock selection, add clock limit for sock754
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit da28c9eb48fb76a142566fc595614bbe9e265914 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 339 ++++++++++++++++------------------- 1 files changed, 157 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..11288da 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,183 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +// well, there are socket 940 boards supported which obviously fail to compile with this +// #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) { - int ranks = 4; - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1681,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask;

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Patch set updated for coreboot: c8e6c0d support for setting the Memory DQ Drive Strength register in amdk8 raminit
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit c8e6c0dbff35eaa9b4ebe7ef4103ecf75ca7172b Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 11288da..d8dcab8 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2193,6 +2193,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err;

1 0

Patch set updated for coreboot: 275c049 add support for setting the vt8237 to uncond. power on after loss of power
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 275c04970eda963c76188c88968f08d1b508da0e Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43);

1 0

Patch set updated for coreboot: b728c65 mark w83697hf_set_clksel_48() as potentially unused
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit b728c65becdaec4d1d1c57876d104cace8ee6fa5 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8;

1 0

Patch set updated for coreboot: f76086e add support for 1106:3188 (host controller of the old version of k8t800)
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit f76086e6289c3aa50ca9f50116984d150e6a5544 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include <console/console.h> #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA,

1 0

Patch merged into coreboot/master: 0d22c91 simplify IDE cable detection for Asus M2V
by gerrit＠coreboot.org 02 Nov '11

02 Nov '11

the following patch was just integrated into master: commit 0d22c9143f78aad039a364b15e651baf98e37a2f Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:13 2011 +0100 simplify IDE cable detection for Asus M2V Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Build-Tested: build bot (Jenkins) at Wed Nov 2 10:27:32 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Nov 2 16:50:04 2011, giving +2 See http://review.coreboot.org/371 for details. -gerrit

1 0

How to change clockchip frequency?
by Oskar Enoksson 02 Nov '11

02 Nov '11

I have a chip called CDC960 on my motherboard. It is responsible for generating the bus frequency for the cpu, the pci bus etc. I downloaded the datasheet and noticed that I can change the base frequency by +/-10% by sending an smbus command to the cdc960. When I sent the smbus commands from a running linux the system froze for a few seconds and then rebooted. But after reboot the frequency was indeed changed (overclocked) and everything worked just fine. I tried to add the smbus command to romstage.c in my coreboot, but that didn't work. The boot process just hanged immediately after the smbus command had been sent. I guess the running CPU (or something else in the system) cannot handle the frequency change and needs to be reset immediately after the command is sent. Perhaps some watchdog under Linux resets the system after a few seconds of irresponsiveness. But what is the recommended way in coreboot?

2 1

Re: [coreboot] Coreboot and Epia M-II
by Elisenda Cuadros 02 Nov '11

02 Nov '11

Hello QingPei, This is the output of this command: Name Offset Type Size cmos_layout.bin 0x0 unknown 1159 pci1106,3122.rom 0x4c0 optionrom 57344 config 0xe500 raw 2581 bootorder 0xef40 raw 86 (empty) 0xefc0 null 3992 fallback/romstage 0xff80 stage 33837 fallback/coreboot_ram 0x18440 stage 36544 fallback/payload 0x21340 payload 51429 (empty) 0x2dc80 null 73878 Regards, Elisenda On 02/11/2011 7:55, QingPei Wang wrote: > what's the structure of cbfs? > how about the output of command: > ./build/cbfstool coreboot.rom print > ? > > > > Best wishes > QingPei Wang > Phone: 86+018930528086

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coreboot November 2011