coreboot November 2011

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New patch to review for coreboot: 099afa0 some black magic for initializing the old version of the k8t800
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/388 -gerrit commit 099afa03d6887be7c480584a5b6d9fbb3c4fecfd Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:38 2011 +0100 some black magic for initializing the old version of the k8t800 Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/bridge.c | 9 +++++++++ src/southbridge/via/k8t890/ctrl.c | 11 +++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 1b21b32..ecfdc35 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -33,9 +33,14 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x40, 0x91); writeback(dev, 0x41, 0x40); writeback(dev, 0x43, 0x44); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x42, 0x80); + writeback(dev, 0x44, 0x35); +#else writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet * says it is reserved */ +#endif writeback(dev, 0x45, 0x3a); writeback(dev, 0x46, 0x88); /* PCI ID lo */ writeback(dev, 0x47, 0xb1); /* PCI ID hi */ @@ -44,7 +49,11 @@ static void bridge_enable(struct device *dev) * (Forward VGA compatible memory and I/O cycles ) */ +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + writeback(dev, 0x3e, 0x0a); +#else writeback(dev, 0x3e, 0x16); +#endif dump_south(dev); /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index d68e03e..4a6428d 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -37,12 +37,21 @@ void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x70, 0xc2); /* PCI Control */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x72, 0xee); +#endif pci_write_config8(dev, 0x73, 0x01); +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + pci_write_config8(dev, 0x74, 0x64); + pci_write_config8(dev, 0x75, 0x3f); +#else pci_write_config8(dev, 0x74, 0x24); pci_write_config8(dev, 0x75, 0x0f); +#endif pci_write_config8(dev, 0x76, 0x50); +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x77, 0x08); +#endif pci_write_config8(dev, 0x78, 0x01); /* APIC on HT */ pci_write_config8(dev, 0x7c, 0x7f); @@ -137,7 +146,9 @@ static void ctrl_init(struct device *dev) /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD pci_write_config8(dev, 0x47, 0x30); +#endif /* VT8237R specific configuration other SB are done in their own directories */

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New patch to review for coreboot: e31e5e0 make GPIOs and misc configurable via devicetree
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit e31e5e0554f44c4ac22438e5d6ae2212ea51303b Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index baf3f93..c7d1378 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */

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New patch to review for coreboot: ecbe2b0 make INT[EFGH]# of vt8237 configurable via devicetree
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit ecbe2b0979711d5de7dfccafbf375f4d6e8eeeac Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ad0327a..baf3f93 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -509,7 +520,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */

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New patch to review for coreboot: 3e27bde implement usb2 termination and dpll delay setting for vt8237r
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385 -gerrit commit 3e27bdedf8802738e72ab531bbc37296bce02430 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:35 2011 +0100 implement usb2 termination and dpll delay setting for vt8237r Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 18 ++++++++++++++++++ 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..35530b4 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" #include "vt8237r.h" #if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8; @@ -112,6 +114,22 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif + cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, (pci_read_config8(dev, 0x5c) & ~0x70) | (cfg->usb2_dpll_delay << 4)); + } + } } static void vt8237_usb_ii_read_resources(struct device *dev)

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New patch to review for coreboot: d3b9110 implement hwmon fan divisor setting for w83697hf
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/384 -gerrit commit d3b91106c06225c2bb179326ff2bbcda9ce8d6fd Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:06 2011 +0100 implement hwmon fan divisor setting for w83697hf Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/superio/winbond/w83697hf/chip.h | 3 +- src/superio/winbond/w83697hf/superio.c | 33 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/chip.h b/src/superio/winbond/w83697hf/chip.h index 1a1cbcc..2359b66 100644 --- a/src/superio/winbond/w83697hf/chip.h +++ b/src/superio/winbond/w83697hf/chip.h @@ -26,7 +26,8 @@ extern struct chip_operations superio_winbond_w83697hf_ops; struct superio_winbond_w83697hf_config { - + unsigned int hwmon_fan1_divisor; + unsigned int hwmon_fan2_divisor; }; #endif diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index d2cbcbd..a7f4f67 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -41,10 +41,43 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, dev->path.pnp.port); } +static void hwmon_set_fan_divisor(unsigned int base, int num, unsigned int divisor) { + unsigned char enc, buf; + + if (divisor) { + enc = log2(divisor); + if (1 << enc != divisor || enc > 7) + die("invalid fan divisor"); + outb(0x4e, base + 5); + outb(0x00, base + 6); + outb(0x47, base + 5); + outb((inb(base + 6) & ~(0x30 << (num * 2))) | ((enc & 3) << (4 + num * 2)), base + 6); + outb(0x5d, base + 5); + buf = inb(base + 6); + outb(0x5d, base + 5); // the above inb() auto-increments the address pointer ... + outb((buf & ~(0x20 << num)) | ((enc & 4) << (3 + num)), base + 6); + } +} + static void w83697hf_init(device_t dev) { + struct resource *res0; + struct superio_winbond_w83697hf_config *cfg; + if (!dev->enabled) return; + + cfg = dev->chip_info; + + switch (dev->path.pnp.device) { + case W83697HF_HWM: + if (cfg) { + res0 = find_resource(dev, PNP_IDX_IO0); + hwmon_set_fan_divisor(res0->base, 0, cfg->hwmon_fan1_divisor); + hwmon_set_fan_divisor(res0->base, 1, cfg->hwmon_fan2_divisor); + } + break; + } } static void w83697hf_pnp_set_resources(device_t dev)

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New patch to review for coreboot: 39c11a8 add support for setting the vt8237 to uncond. power on after loss of power
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 39c11a8aa6da368436a48f183764c26eb63096ba Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 4b3064a..ad0327a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -511,6 +511,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43);

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New patch to review for coreboot: c5a14a9 support for setting the Memory DQ Drive Strength register in amdk8 raminit
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit c5a14a9500962628913ed77d52fe86b16d500b04 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 944517b..9fdda2a 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2192,6 +2192,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err;

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New patch to review for coreboot: 33c753a add support for 1106:3188 (host controller of the old version of k8t800)
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 33c753a26a73e60b3df9914473e21b4b2d2327d4 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include <console/console.h> #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA,

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New patch to review for coreboot: f600317 mark w83697hf_set_clksel_48() as potentially unused
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit f60031755fb2867bebb3ed62ee9bca1599f5dac3 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 mark w83697hf_set_clksel_48() as potentially unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/superio/winbond/w83697hf/early_serial.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..cc647a7 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +static void __attribute__ ((unused)) w83697hf_set_clksel_48(device_t dev) { u8 reg8;

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New patch to review for coreboot: 6398991 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit 639899110fc22d60e45a6e59bc9275bffcf5932a Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#ifndef __PRE_RAM__ +#include <device/device.h> +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */

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coreboot November 2011