coreboot November 2011

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New patch to review for coreboot: 7c82505 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 7c82505931f249435fe89bf03a596ffb87488802 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */

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New patch to review for coreboot: b1c91b4 k8 raminit: fix bug, improve clock selection, add clock limit for sock754
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit b1c91b40a96724587a147b6f3f97dc92a10fe5e7 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 338 ++++++++++++++++------------------- 1 files changed, 156 insertions(+), 182 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..944517b 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1231,7 +1231,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 25, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,10 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) { #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1440,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos =0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1474,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1483,182 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table are to be understood: */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ +#else /* CONFIG_CPU_AMD_SOCKET_* */ + + #error load dependent memory clock limiting is not implemented for this socket + + /* see BKDG 4.1.3--if you just want to test a setup that doesn't require + * limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what would be + * intuitive. 200 MHz has the lowest constant, 100 MHz the highest. Thus, all + * comparisons and traversal directions having to do with frequencies are/ + * have to be the opposite of what would be intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); // the CLs supported by the controller + memset(cl_at_freq, 0x00, (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) { - int ranks = 4; - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle shorter, select that + * (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#ifdef CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1680,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask;

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New patch to review for coreboot: 36dc86c fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit 36dc86c3f86adcb9df2f64752c3ceccb334e6b58 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333)

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New patch to review for coreboot: 861b306 configure VT8237R ROM decode according to CONFIG_ROM_SIZE
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/375 -gerrit commit 861b306c9f63f5a7ff075a94d07c21fb2645cf5f Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:27 2011 +0100 configure VT8237R ROM decode according to CONFIG_ROM_SIZE Change-Id: I217813f42a52f759bf1010f4c5af62f3c6e5ec6b Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/lpc.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..4b3064a 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -447,7 +447,10 @@ static void vt8237_common_init(struct device *dev) * 0 FFC00000h-FFC7FFFFh * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. */ - pci_write_config8(dev, 0x41, 0x7f); +#if CONFIG_ROM_SIZE > 0x400000 +#error ROMs larger than 4MB are not supported by VT8237 +#endif + pci_write_config8(dev, 0x41, (~(0xff>>((CONFIG_ROM_SIZE+(512*1024-1))/(512*1024))))&0x7f); #endif /*

1 0

New patch to review for coreboot: 7706088 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 77060882c64143228a6058b4686fb102bc6526d7 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */

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New patch to review for coreboot: 309034f support for different location of HT registers in old version of K8T800
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit 309034f5a0fa9f90cc725be2b5e8f5da9692dcb8 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */

1 0

New patch to review for coreboot: c77d232 add support for reading from SMBus with vt8237
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/372 -gerrit commit c77d2321f5dd78f70b591c995aeb28beac45c2b3 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:13 2011 +0100 add support for reading from SMBus with vt8237 Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/early_smbus.c | 31 +++++++++++++++++++--------- src/southbridge/via/vt8237r/vt8237r.h | 1 + 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index a298e84..0caf93d 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -87,17 +87,12 @@ static void smbus_reset(void) PRINT_DEBUG("\n"); } -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) +static u8 smbus_transaction(u8 dimm, u8 offset, int data) { u8 val; - PRINT_DEBUG("DIMM "); + PRINT_DEBUG((data < 0) ? "RD: " : "WR: "); + PRINT_DEBUG("ADDR "); PRINT_DEBUG_HEX16(dimm); PRINT_DEBUG(" OFFSET "); PRINT_DEBUG_HEX16(offset); @@ -106,13 +101,13 @@ u8 smbus_read_byte(u8 dimm, u8 offset) smbus_reset(); /* Clear host data port. */ - outb(0x00, SMBHSTDAT0); + outb((data < 0) ? 0x00 : data, SMBHSTDAT0); SMBUS_DELAY(); smbus_wait_until_ready(); /* Actual addr to reg format. */ dimm = (dimm << 1); - dimm |= 1; + dimm |= (data < 0); outb(dimm, SMBXMITADD); outb(offset, SMBHSTCMD); @@ -132,6 +127,22 @@ u8 smbus_read_byte(u8 dimm, u8 offset) return val; } +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u8 dimm, u8 offset) +{ + return smbus_transaction(dimm, offset, -1); +} + +void smbus_write_byte(u8 dimm, u8 offset, u8 data) +{ + smbus_transaction(dimm, offset, data); +} + #define PSONREADY_TIMEOUT 0x7fffffff static device_t get_vt8237_lpc(void) diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index 94b1840..9d5a1fc 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -148,6 +148,7 @@ __attribute__ ((packed)) #ifdef __PRE_RAM__ #ifndef __ROMCC__ u8 smbus_read_byte(u8 dimm, u8 offset); +void smbus_write_byte(u8 dimm, u8 offset, u8 data); void enable_smbus(void); void smbus_fixup(const struct mem_controller *ctrl); // these are in vt8237_early_smbus.c - do they really belong there?

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New patch to review for coreboot: 0d22c91 simplify IDE cable detection for Asus M2V
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/371 -gerrit commit 0d22c9143f78aad039a364b15e651baf98e37a2f Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:13 2011 +0100 simplify IDE cable detection for Asus M2V Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/mainboard/asus/m2v/mainboard.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 76d3cf6..2f20fe0 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -37,10 +37,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev) if (!lpc_dev) return 0; - acpi_io_base = pci_read_config16(lpc_dev, 0x88); - if (!acpi_io_base || (acpi_io_base & ~1) == 0) + acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1; + if (!acpi_io_base) return 0; - acpi_io_base &= ~1; gpio_in = inl(acpi_io_base + 0x48); /* bit 9 for primary port, clear if unconnected or 80-pin cable */ @@ -49,9 +48,9 @@ u32 vt8237_ide_80pin_detect(struct device *dev) res |= gpio_in & (1<<4) ? 0 : VT8237R_IDE1_80PIN_CABLE; printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary", - gpio_in & (1<<9) ? 40 : 80); + res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40); printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary", - gpio_in & (1<<4) ? 40 : 80); + res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40); return res; }

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New patch to review for coreboot: e47de27 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370 -gerrit commit e47de274deb976f8953101d5894910a8bf1956ab Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b..dc3addb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl;

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New patch to review for coreboot: f07282e don't scan beyond end of CBFS
by Florian Zumbiehl 02 Nov '11

02 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/369 -gerrit commit f07282efab87037a54cf0f48c0ab835cbbd39efe Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:11 2011 +0100 don't scan beyond end of CBFS Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- payloads/libpayload/libcbfs/cbfs_core.c | 3 ++- src/lib/cbfs_core.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 596fa3f..4bf755b 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -97,6 +97,7 @@ struct cbfs_file *cbfs_find(const char *name) data = (void*)phys_to_virt(romstart()) + ntohl(header->offset); dataend = (void*)phys_to_virt(romstart()) + ntohl(header->romsize); } + dataend -= ntohl(header->bootblocksize); int align = ntohl(header->align); @@ -106,7 +107,7 @@ struct cbfs_file *cbfs_find(const char *name) if (memcmp(CBFS_FILE_MAGIC, file->magic, strlen(CBFS_FILE_MAGIC)) != 0) { // no file header found. corruption? // proceed in aligned steps to resynchronize - LOG("No file header found at %p, searching for header\n", data); + LOG("ERROR: No file header found at %p, attempting to recover by searching for header\n", data); data = phys_to_virt(CBFS_ALIGN_UP(virt_to_phys(data), align)); continue; } diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 596fa3f..4bf755b 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -97,6 +97,7 @@ struct cbfs_file *cbfs_find(const char *name) data = (void*)phys_to_virt(romstart()) + ntohl(header->offset); dataend = (void*)phys_to_virt(romstart()) + ntohl(header->romsize); } + dataend -= ntohl(header->bootblocksize); int align = ntohl(header->align); @@ -106,7 +107,7 @@ struct cbfs_file *cbfs_find(const char *name) if (memcmp(CBFS_FILE_MAGIC, file->magic, strlen(CBFS_FILE_MAGIC)) != 0) { // no file header found. corruption? // proceed in aligned steps to resynchronize - LOG("No file header found at %p, searching for header\n", data); + LOG("ERROR: No file header found at %p, attempting to recover by searching for header\n", data); data = phys_to_virt(CBFS_ALIGN_UP(virt_to_phys(data), align)); continue; }

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coreboot November 2011