coreboot November 2011

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Patch set updated for coreboot: 33220b1 make INT[EFGH]# of vt8237 configurable via devicetree
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/386 -gerrit commit 33220b1e4080177f5f78810ab2e0c0630b9e2ebd Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:36 2011 +0100 make INT[EFGH]# of vt8237 configurable via devicetree Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/chip.h | 2 ++ src/southbridge/via/vt8237r/lpc.c | 21 ++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index 2e24fac..be5e7fc 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_set; u8 usb2_dpll_delay; + + u8 no_int_efgh; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 0e757fe..d4f7820 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -67,6 +67,8 @@ static void pci_routing_fixup(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; +#else + struct southbridge_via_vt8237r_config *cfg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */ @@ -124,8 +126,14 @@ static void pci_routing_fixup(struct device *dev) pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); #else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); + cfg = dev->chip_info; + + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x46, 0x00); + } else { + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + } /* PCI Interrupt Polarity */ pci_write_config8(dev, 0x54, 0x00); @@ -421,6 +429,9 @@ static void vt8237s_init(struct device *dev) static void vt8237_common_init(struct device *dev) { u8 enables, byte; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; /* Enable addr/data stepping. */ byte = pci_read_config8(dev, PCI_COMMAND); @@ -506,7 +517,11 @@ static void vt8237_common_init(struct device *dev) * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ - pci_write_config8(dev, 0x5b, 0xb); + if (cfg && cfg->no_int_efgh) { + pci_write_config8(dev, 0x5b, 0x9); + } else { + pci_write_config8(dev, 0x5b, 0xb); + } #if CONFIG_VT8237R_ON_AFTER_POWER_LOSS /* make it so the board unconditionally powers on after loss of power */

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Patch set updated for coreboot: 919545c make GPIOs and misc configurable via devicetree
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 919545cd90723e21927793dbd0da9c42e6e2ef61 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index d4f7820..7d7326c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */

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Patch set updated for coreboot: 1b45f67 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/378 -gerrit commit 1b45f67513650eb6ef3885b244422c86bcc1dff4 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:30 2011 +0100 factor out common config for k8x8xx's dram_enable() and vt8237r_cfg() Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/ctrl.c | 49 ++++++---------------------------- src/southbridge/via/k8t890/dram.c | 18 ++++++------ src/southbridge/via/k8t890/k8x8xx.h | 25 ++++++++++++++++++ 3 files changed, 43 insertions(+), 49 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 42676b1..7363510 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -31,31 +31,8 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - if(!devfun3) - die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); + u8 regm3; + struct k8x8xx_vt8237_mirrored_regs mregs; pci_write_config8(dev, 0x70, 0xc2); @@ -71,21 +48,14 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) pci_write_config8(dev, 0x7c, 0x7f); pci_write_config8(dev, 0x7f, 0x02); - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); + k8x8xx_vt8237_mirrored_regs_fill(&mregs); - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); + pci_write_config8(dev, 0x57, mregs.shadow_mem_ctrl); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x61, mregs.rom_shadow_ctrl_pg_c); /* Shadow page C */ + pci_write_config8(dev, 0x62, mregs.rom_shadow_ctrl_pg_d); /* Shadow page D */ + pci_write_config8(dev, 0xe6, mregs.smm_apic_decoding); /* SMM and APIC decoding */ - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + regm3 = mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding; /* Shadow page E */ /* * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! @@ -98,8 +68,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) regm3 = 0x0; /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + pci_write_config8(dev, 0x63, regm3 | (mregs.rom_shadow_ctrl_pg_f_memhole & 0x3F)); } diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 9b43a5e..294e387 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -30,14 +30,15 @@ static void dram_enable(struct device *dev) { - msr_t msr; u16 reg; + struct k8x8xx_vt8237_mirrored_regs mregs; + k8x8xx_vt8237_mirrored_regs_fill(&mregs); /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC * decoding, MSI support, no SMRAM, compatible SMM. */ - pci_write_config8(dev, 0x86, 0x19); + pci_write_config8(dev, 0x86, mregs.smm_apic_decoding); /* * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if @@ -48,23 +49,22 @@ static void dram_enable(struct device *dev) /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for * C0000-C3FFF etc. */ - pci_write_config8(dev, 0x80, 0xff); + pci_write_config8(dev, 0x80, mregs.rom_shadow_ctrl_pg_c); /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); + pci_write_config8(dev, 0x81, mregs.rom_shadow_ctrl_pg_d); /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); + pci_write_config8(dev, 0x82, mregs.rom_shadow_ctrl_pg_e_memhole_smi_decoding); + pci_write_config8(dev, 0x83, mregs.rom_shadow_ctrl_pg_f_memhole); - msr = rdmsr(TOP_MEM); reg = pci_read_config16(dev, 0x84); reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + pci_write_config16(dev, 0x84, mregs.low_top_address | reg); reg = pci_read_config16(dev, 0x88); reg &= 0xf800; /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl); print_debug(" VIA_X_3 device dump:\n"); dump_south(dev); diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index a0fb57a..425aaeb 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -21,6 +21,31 @@ #ifndef SOUTHBRIDGE_VIA_K8T890_K8X8XX_H #define SOUTHBRIDGE_VIA_K8T890_K8X8XX_H +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> #include "k8t890.h" +struct k8x8xx_vt8237_mirrored_regs { + u16 low_top_address; + u8 rom_shadow_ctrl_pg_c, + rom_shadow_ctrl_pg_d, + rom_shadow_ctrl_pg_e_memhole_smi_decoding, + rom_shadow_ctrl_pg_f_memhole, + smm_apic_decoding, + shadow_mem_ctrl; +}; + +static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){ + msr_t msr; + + regs->rom_shadow_ctrl_pg_c = 0xff; + regs->rom_shadow_ctrl_pg_d = 0xff; + regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff; + regs->rom_shadow_ctrl_pg_f_memhole = 0x30; + regs->smm_apic_decoding = 0x19; + msr = rdmsr(TOP_MEM); + regs->shadow_mem_ctrl = msr.lo >> 24; + regs->low_top_address = msr.lo >> 16; +} + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */

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Patch set updated for coreboot: 5bce613 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/379 -gerrit commit 5bce613dc0082308c8d7212acee73d640ae8ebcd Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:01 2011 +0100 rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/ctrl.c | 4 ++-- src/southbridge/via/k8t890/k8x8xx.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index 7363510..d68e03e 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -29,7 +29,7 @@ * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) */ -static void vt8237r_cfg(struct device *dev, struct device *devsb) +void k8x8xx_vt8237r_cfg(struct device *dev, struct device *devsb) { u8 regm3; struct k8x8xx_vt8237_mirrored_regs mregs; @@ -145,7 +145,7 @@ static void ctrl_init(struct device *dev) PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); + k8x8xx_vt8237r_cfg(dev, devsb); } else { print_debug("VT8237R LPC not found !\n"); return; diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h index 425aaeb..c61c984 100644 --- a/src/southbridge/via/k8t890/k8x8xx.h +++ b/src/southbridge/via/k8t890/k8x8xx.h @@ -23,6 +23,9 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#ifndef __PRE_RAM__ +#include <device/device.h> +#endif #include "k8t890.h" struct k8x8xx_vt8237_mirrored_regs { @@ -48,4 +51,8 @@ static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrore regs->low_top_address = msr.lo >> 16; } +#ifndef __PRE_RAM__ +void k8x8xx_vt8237r_cfg(struct device *, struct device *); +#endif + #endif /* SOUTHBRIDGE_VIA_K8T890_K8X8XX_H */

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Patch set updated for coreboot: c4442b0 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/376 -gerrit commit c4442b09fe86633117fb38de81ab9a4a0b27a2ed Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:28 2011 +0100 fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 3583dc3..237272c 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1399,7 +1399,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) #define DDR400 (NBCAP_MEMCLK_200MHZ + 1) #define DDR_2T 0x80 -#define DDR_MASK 0x3 +#define DDR_MASK 0x7 #define DDR200_2T (DDR_2T | DDR200) #define DDR333_2T (DDR_2T | DDR333)

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Patch set updated for coreboot: 8b31a0a k8 raminit: fix bug, improve clock selection, add clock limit for sock754
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/377 -gerrit commit 8b31a0acc8ee489c2020dfa4d48da3623e8e8d76 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:18:29 2011 +0100 k8 raminit: fix bug, improve clock selection, add clock limit for sock754 in amdk8 raminit: - fix DDR SPD offset for (CLX - 1) (25 instead of 26) - improve clock/CL selection algorithm - implement load-dependent clock limiting for socket 754 Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/raminit.c | 349 +++++++++++++++++------------------ 1 files changed, 166 insertions(+), 183 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 237272c..02c764d 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1230,8 +1230,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma 17, /* *Logical Banks */ 18, /* *Supported CAS Latencies */ 21, /* *SDRAM Module Attributes */ - 23, /* *Cycle time at CAS Latnecy (CLX - 0.5) */ - 26, /* *Cycle time at CAS Latnecy (CLX - 1.0) */ + 23, /* *Cycle time at CAS Latency (CLX - 0.5) */ + 25, /* *Cycle time at CAS Latency (CLX - 1.0) */ 27, /* *tRP Row precharge time */ 28, /* *Minimum Row Active to Row Active Delay (tRRD) */ 29, /* *tRCD RAS to CAS */ @@ -1301,11 +1301,11 @@ struct mem_param { char name[9]; }; -static const struct mem_param *get_mem_param(unsigned min_cycle_time) +static const struct mem_param *get_mem_param(int freq) { static const struct mem_param speed[] = { - { - .name = "100Mhz", + [NBCAP_MEMCLK_100MHZ] = { + .name = "100MHz", .cycle_time = 0xa0, .divisor = (10 <<1), .tRC = 0x46, @@ -1318,8 +1318,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) } }, - { - .name = "133Mhz", + [NBCAP_MEMCLK_133MHZ] = { + .name = "133MHz", .cycle_time = 0x75, .divisor = (7<<1)+1, .tRC = 0x41, @@ -1332,8 +1332,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 2, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) } }, - { - .name = "166Mhz", + [NBCAP_MEMCLK_166MHZ] = { + .name = "166MHz", .cycle_time = 0x60, .divisor = (6<<1), .tRC = 0x3C, @@ -1346,8 +1346,8 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_trwt = { { 3, 2, 3 }, { 3, 3, 4 }, { 4, 3, 4 }}, .rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) } }, - { - .name = "200Mhz", + [NBCAP_MEMCLK_200MHZ] = { + .name = "200MHz", .cycle_time = 0x50, .divisor = (5<<1), .tRC = 0x37, @@ -1359,20 +1359,11 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) .dtl_twtr = 2, .dtl_trwt = { { 0, 2, 3 }, { 3, 3, 4 }, { 3, 3, 4 }}, .rdpreamble = { ((7 << 1) + 0), ((5 << 1) + 0), ((5 << 1) + 1), ((5 << 1) + 1) } - }, - { - .cycle_time = 0x00, - }, + } }; const struct mem_param *param; - for (param = &speed[0]; param->cycle_time ; param++) { - if (min_cycle_time > (param+1)->cycle_time) { - break; - } - } - if (!param->cycle_time) { - die("min_cycle_time to low"); - } + + param = speed + freq; printk(BIOS_SPEW, "%s\n", param->name); return param; } @@ -1382,18 +1373,11 @@ struct spd_set_memclk_result { long dimm_mask; }; -static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ -}; +static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t) +{ #if CONFIG_CPU_AMD_SOCKET_939 -/* return the minimum cycle time and set 2T accordingly */ -static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { - /* + 1 raise so we detect 0 as bad field */ #define DDR200 (NBCAP_MEMCLK_100MHZ + 1) #define DDR333 (NBCAP_MEMCLK_166MHZ + 1) @@ -1457,7 +1441,7 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl }; /*The dpos matches channel positions defined in BKDG and above arrays The rpos is bitmask of dual rank dimms in same order as dpos */ - unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + unsigned int dloading = 0, i, rpos = 0, dpos = 0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; uint32_t dcl; @@ -1491,8 +1475,6 @@ static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl #endif hw_error: if (dloading != 0) { - /* map it back to cycle load times */ - dloading_cycle_time = min_cycle_times[dloading - 1]; /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; @@ -1502,189 +1484,190 @@ hw_error: dcl |= DCL_DualDIMMen; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + return dloading - 1; } else { /* if we don't find it we se it to DDR400 */ printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); - dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + return NBCAP_MEMCLK_200MHZ; } - return dloading_cycle_time; -} +#elif CONFIG_CPU_AMD_SOCKET_754 + +#define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1)) + +#define EMPTY 0 +#define X8S_X16 1 +#define X8D 2 + +#define DDR200 NBCAP_MEMCLK_100MHZ +#define DDR333 NBCAP_MEMCLK_166MHZ +#define DDR400 NBCAP_MEMCLK_200MHZ + + /* this is table 42 from the BKDG, ignoring footnote 4, + * with the EMPTY, EMPTY, EMPTY row added */ + static const unsigned char cfgtable[][2] = { + [CFGIDX(EMPTY, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(EMPTY, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, X8D, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8S_X16, EMPTY, X8D )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8S_X16, EMPTY )] = { DDR400, DDR400 }, + [CFGIDX(X8D, X8D, EMPTY )] = { DDR333, DDR333 }, + [CFGIDX(X8D, EMPTY, X8S_X16 )] = { DDR400, DDR400 }, + [CFGIDX(X8D, EMPTY, X8D )] = { DDR333, DDR333 }, + [CFGIDX(EMPTY, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(EMPTY, X8S_X16, X8D )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8S_X16 )] = { DDR200, DDR400 }, + [CFGIDX(EMPTY, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8S_X16, X8S_X16 )] = { DDR333, DDR400 }, + [CFGIDX(X8S_X16, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8S_X16, X8D, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8S_X16 )] = { DDR333, DDR333 }, + [CFGIDX(X8D, X8S_X16, X8D )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8S_X16 )] = { DDR200, DDR333 }, + [CFGIDX(X8D, X8D, X8D )] = { DDR200, DDR333 } + }; + + int i, rank, width, dimmtypes[3]; + const unsigned char *cfg; + + for (i = 0; i < 3; i++) { + if (dimm_mask & (1 << i)) { + rank = spd_read_byte(ctrl->channel0[i], 5); + width = spd_read_byte(ctrl->channel0[i], 13); + if (rank < 0 || width < 0) die("failed to read SPD"); + width &= 0x7f; + /* this is my guess as to how the criteria in the table + * are to be understood: + */ + dimmtypes[i] = width >= (rank == 1 ? 8 : 16) ? X8S_X16 : X8D; + } else { + dimmtypes[i] = EMPTY; + } + } + cfg = cfgtable[CFGIDX(dimmtypes[0], dimmtypes[1], dimmtypes[2])]; + *freq_1t = cfg[0]; + return is_cpu_c0() ? cfg[0] : cfg[1]; + +#else /* CONFIG_CPU_AMD_SOCKET_* */ + +// well, there are socket 940 boards supported which obviously fail to +// compile with this +// #error load dependent memory clock limiting is not implemented for this socket -#endif /* #if CONFIG_CPU_AMD_SOCKET_939 */ + /* see BKDG 4.1.3--if you just want to test a setup that doesn't + * require limiting, you may use the following code */ + + *freq_1t = NBCAP_MEMCLK_200MHZ; + return NBCAP_MEMCLK_200MHZ; + +#endif /* CONFIG_CPU_AMD_SOCKET_* */ + +} static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { - /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; - unsigned min_cycle_time, min_latency, bios_cycle_time; -#if CONFIG_CPU_AMD_SOCKET_939 - unsigned dloading_cycle_time; -#endif - int i; + unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; + int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; uint32_t value; - static const uint8_t latency_indicies[] = { 26, 23, 9 }; - - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - - min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - bios_cycle_time = min_cycle_times[ - read_option(max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { - min_cycle_time = bios_cycle_time; - } - min_latency = 2; + static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const unsigned char cycle_time_at_freq[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ + }; - /* Compute the least latency with the fastest clock supported - * by both the memory controller and the dimms. + /* BEWARE that the constants for frequencies order in reverse of what + * would be intuitive. 200 MHz has the lowest constant, 100 MHz the + * highest. Thus, all comparisons and traversal directions having to + * do with frequencies are/have to be the opposite of what would be + * intuitive. */ - for (i = 0; i < DIMM_SOCKETS; i++) { - int new_cycle_time, new_latency; - int index; - int latencies; - int latency; - if (!(dimm_mask & (1 << i))) { - continue; - } + // the CLs supported by the controller: + memset(cl_at_freq, 0x1c, sizeof(cl_at_freq)); + memset(cl_at_freq, 0x00, + (pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >> + NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK); + max_freq_bios = read_option(max_mem_clock, 0); + if (max_freq_bios <= NBCAP_MEMCLK_100MHZ) + memset(cl_at_freq, 0x00, max_freq_bios); + for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { + int x,i,spd_cls,cl,spd_min_cycle_time; + unsigned char cl_at_freq_mask[sizeof(cl_at_freq)]; - /* First find the supported CAS latencies - * Byte 18 for DDR SDRAM is interpreted: + if (!(dimm_mask & (1 << dimm))) + continue; + /* Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 * bit 1 == CAS Latency = 1.5 * bit 2 == CAS Latency = 2.0 * bit 3 == CAS Latency = 2.5 * bit 4 == CAS Latency = 3.0 * bit 5 == CAS Latency = 3.5 - * bit 6 == TBD + * bit 6 == CAS Latency = 4.0 * bit 7 == TBD */ - new_cycle_time = 0xa0; - new_latency = 5; - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies <= 0) continue; - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - int spd_value; - if ((latency < 2) || (latency > 4) || - (!(latencies & (1 << latency)))) { + spd_cls = spd_read_byte(ctrl->channel0[dimm], 18); + if (spd_cls <= 0) + goto hw_error; + memset(cl_at_freq_mask, 0x00, sizeof(cl_at_freq_mask)); + for (cl = 1 << log2(spd_cls), i = 0; i < 3; cl >>= 1, i++) { + if (!(spd_cls & cl)) continue; - } - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) { + spd_min_cycle_time = spd_read_byte(ctrl->channel0[dimm], + spd_min_cycle_time_indices[i]); + if (spd_min_cycle_time < 0) goto hw_error; - } - - /* Only increase the latency if we decreas the clock */ - if ((spd_value >= min_cycle_time) && (spd_value < new_cycle_time)) { - new_cycle_time = spd_value; - new_latency = latency; - } - } - if (new_latency > 4){ - continue; - } - /* Does min_latency need to be increased? */ - if (new_cycle_time > min_cycle_time) { - min_cycle_time = new_cycle_time; - } - /* Does min_cycle_time need to be increased? */ - if (new_latency > min_latency) { - min_latency = new_latency; - } - } - /* Make a second pass through the dimms and disable - * any that cannot support the selected memclk and cas latency. - */ - - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int latencies; - int latency; - int index; - int spd_value; - if (!(dimm_mask & (1 << i))) { - continue; - } - - latencies = spd_read_byte(ctrl->channel0[i], 18); - if (latencies < 0) goto hw_error; - if (latencies == 0) { - goto dimm_err; - } - - /* Compute the lowest cas latency supported */ - latency = log2(latencies) -2; - - /* Walk through searching for the selected latency */ - for (index = 0; index < 3; index++, latency++) { - if (!(latencies & (1 << latency))) { + if ((!spd_min_cycle_time) || (spd_min_cycle_time & 0x0f) > 9) continue; - } - if (latency == min_latency) - break; - } - /* If I can't find the latency or my index is bad error */ - if ((latency != min_latency) || (index >= 3)) { - goto dimm_err; + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + if (cycle_time_at_freq[x] >= spd_min_cycle_time) + cl_at_freq_mask[x] |= cl; } + for (x = 0; x < sizeof(cl_at_freq_mask); x++) + cl_at_freq[x] &= cl_at_freq_mask[x]; + } - /* Read the min_cycle_time for this latency */ - spd_value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - if (spd_value < 0) goto hw_error; + freq = NBCAP_MEMCLK_200MHZ; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; - /* All is good if the selected clock speed - * is what I need or slower. - */ - if (spd_value <= min_cycle_time) { - continue; - } - /* Otherwise I have an error, disable the dimm */ - dimm_err: - dimm_mask = disable_dimm(ctrl, i, dimm_mask); + max_freq_dloading = spd_dimm_loading_socket(ctrl, dimm_mask, &max_freq_1t); + if (max_freq_dloading > freq) { + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + freq = max_freq_dloading; + while (freq < sizeof(cl_at_freq) && !cl_at_freq[freq]) + freq++; } -#if 0 -//down speed for full load 4 rank support -#if CONFIG_QRANK_DIMM_SUPPORT - if (dimm_mask == (3|(3<<DIMM_SOCKETS)) ) { - int ranks = 4; - for (i = 0; (i < 4) && (ctrl->channel0[i]); i++) { - int val; - if (!(dimm_mask & (1 << i))) { - continue; - } - val = spd_read_byte(ctrl->channel0[i], 5); - if (val!=ranks) { - ranks = val; - break; - } - } - if (ranks==4) { - if (min_cycle_time <= 0x50 ) { - min_cycle_time = 0x60; - } - } - } -#endif -#endif + /* if the next lower frequency gives a CL at least one whole cycle + * shorter, select that (see end of BKDG 4.1.1.1) */ + if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && + log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + freq++; -#if CONFIG_CPU_AMD_SOCKET_939 - dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); - if (dloading_cycle_time > min_cycle_time) { - min_cycle_time = dloading_cycle_time; - printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + if (freq == sizeof(cl_at_freq)) + goto hw_error; + +#if CONFIG_CPU_AMD_SOCKET_754 + if (freq < max_freq_1t) { + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, + pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } #endif - - /* Now that I know the minimum cycle time lookup the memory parameters */ - result.param = get_mem_param(min_cycle_time); + result.param = get_mem_param(freq); /* Update DRAM Config High with our selected memory speed */ value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); @@ -1706,7 +1689,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; + value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask;

1 0

Patch set updated for coreboot: caf6207 support for setting the Memory DQ Drive Strength register in amdk8 raminit
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382 -gerrit commit caf6207137afddd79b7d3051ccf4139a958f16b5 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit make sure DRAM drive strength is not reduced Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 02c764d..e09075f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2201,6 +2201,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + + if (!is_cpu_pre_e0()) { + uint32_t dch; + + // see also erratum 114, essentially: never ever + // set to anything but 0 + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= DCH_DQ_DRV_STRENGTH_0 << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err;

1 0

Patch set updated for coreboot: 74e888f add support for setting the vt8237 to uncond. power on after loss of power
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383 -gerrit commit 74e888f9402d11d52a4053df475cd6c9731c167d Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:04 2011 +0100 add support for setting the vt8237 to uncond. power on after loss of power Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/Kconfig | 4 ++++ src/southbridge/via/vt8237r/lpc.c | 9 +++++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..e4f73da 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/via/vt8237r/bootblock.c" depends on SOUTHBRIDGE_VIA_VT8237R + +config VT8237R_ON_AFTER_POWER_LOSS + bool + diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b1e1afe..0e757fe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev) */ pci_write_config8(dev, 0x5b, 0xb); +#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS + /* make it so the board unconditionally powers on after loss of power */ + enables = pci_read_config8(dev, 0x58); + pci_write_config8(dev, 0x58, enables & ~0x02); + outb(0x0d, 0x70); + outb(0x00, 0x71); + pci_write_config8(dev, 0x58, enables); +#endif + /* Set 0x58 to 0x43 APIC and RTC. */ pci_write_config8(dev, 0x58, 0x43);

1 0

Patch set updated for coreboot: c4c21e6 make w83697hf_set_clksel_48() non-static and add a prototype
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/380 -gerrit commit c4c21e6701b72830ce291197d92e9aeef5395297 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 make w83697hf_set_clksel_48() non-static and add a prototype make w83697hf_set_clksel_48() non-static and add a prototype so as to get rid of warnings about it being unused Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/superio/winbond/w83697hf/early_serial.c | 2 +- src/superio/winbond/w83697hf/w83697hf.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 7731804..2825eeb 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -35,7 +35,7 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(device_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 0eeb37c..6488dd3 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -32,4 +32,8 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ +#ifndef __ROMCC__ +void w83697hf_set_clksel_48(device_t); +#endif + #endif

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Patch set updated for coreboot: 68c5545 add support for 1106:3188 (host controller of the old version of k8t800)
by Florian Zumbiehl 03 Nov '11

03 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/381 -gerrit commit 68c554550f59bd96caace96260ae2e30ed55ceb4 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/host.c | 45 +++++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index 13bd693..700a637 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -25,6 +25,36 @@ #include <console/console.h> #include "k8x8xx.h" +static void host_old_enable(struct device *dev) +{ + int agp3; + + /* some HT tweaking */ + pci_write_config8(dev, 0x50, 0x03); + pci_write_config8(dev, 0x55, 0x2c); + + /* AGP setup */ + pci_write_config8(dev, 0xac, 0x06); + pci_write_config8(dev, 0xad, 0x08); + pci_write_config8(dev, 0xfd, 0x02); + pci_write_config8(dev, 0x85, 0xb0); + pci_write_config8(dev, 0x87, 0x07); + pci_write_config8(dev, 0xfd, 0x06); // this is required for the following write to work + pci_write_config8(dev, 0xaf, 0x88); + pci_write_config8(dev, 0xfd, 0x04); // select AGP 3.0 + agp3 = pci_read_config8(dev, 0x84) & 0x08; + pci_write_config8(dev, 0xb1, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb3, agp3 ? 0x00 : 0x9B); + pci_write_config8(dev, 0xb0, 0x40); + pci_write_config8(dev, 0xb2, 0x11); + pci_write_config8(dev, 0xed, 0x40); +} + +static void host_old_init(struct device *dev) +{ + k8x8xx_vt8237r_cfg(dev, NULL); +} + static void host_enable(struct device *dev) { /* Multiple function control */ @@ -56,6 +86,15 @@ static void host_init(struct device *dev) } +static const struct device_operations host_ops_old = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_old_enable, + .init = host_old_init, + .ops_pci = 0, +}; + static const struct device_operations host_ops_t = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -73,6 +112,12 @@ static const struct device_operations host_ops_m = { .ops_pci = 0, }; +static const struct pci_driver northbridge_driver_t800_old __pci_driver = { + .ops = &host_ops_old, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_AGP, +}; + static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA,

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coreboot November 2011