Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383
-gerrit
commit 70d2309014db84e3cdd0a19eeb0a69416ac8c90a
Author: Florian Zumbiehl <florz(a)florz.de>
Date: Tue Nov 1 20:19:04 2011 +0100
add support for setting the vt8237 to uncond. power on after loss of power
Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63
Signed-off-by: Florian Zumbiehl <florz(a)florz.de>
---
src/southbridge/via/vt8237r/Kconfig | 4 ++++
src/southbridge/via/vt8237r/lpc.c | 9 +++++++++
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig
index d0a6deb..e4f73da 100644
--- a/src/southbridge/via/vt8237r/Kconfig
+++ b/src/southbridge/via/vt8237r/Kconfig
@@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/via/vt8237r/bootblock.c"
depends on SOUTHBRIDGE_VIA_VT8237R
+
+config VT8237R_ON_AFTER_POWER_LOSS
+ bool
+
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index b1e1afe..0e757fe 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev)
*/
pci_write_config8(dev, 0x5b, 0xb);
+#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS
+ /* make it so the board unconditionally powers on after loss of power */
+ enables = pci_read_config8(dev, 0x58);
+ pci_write_config8(dev, 0x58, enables & ~0x02);
+ outb(0x0d, 0x70);
+ outb(0x00, 0x71);
+ pci_write_config8(dev, 0x58, enables);
+#endif
+
/* Set 0x58 to 0x43 APIC and RTC. */
pci_write_config8(dev, 0x58, 0x43);
Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370
-gerrit
commit 3e13da8aa63cd8ec6e4657e7bbc0a23b45a76257
Author: Florian Zumbiehl <florz(a)florz.de>
Date: Tue Nov 1 20:17:12 2011 +0100
Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz(a)florz.de>
---
src/northbridge/amd/amdk8/raminit_f.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 319293b..dc3addb 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
18, /* *Supported CAS Latencies */
9, /* *Cycle time at highest CAS Latency CL=X */
23, /* *Cycle time at CAS Latency (CLX - 1) */
- 26, /* *Cycle time at CAS Latency (CLX - 2) */
+ 25, /* *Cycle time at CAS Latency (CLX - 2) */
};
u32 dcl, dcm;
u8 common_cl;