Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/383
-gerrit
commit e8b777ea30ccfdc2e9d3028ac1e74a4dd8796aa4
Author: Florian Zumbiehl <florz(a)florz.de>
Date: Tue Nov 1 20:19:04 2011 +0100
add support for setting the vt8237 to uncond. power on after loss of power
Change-Id: Iccc0dcd9f82e525c6c3abcec9f4ed0f2de581e63
Signed-off-by: Florian Zumbiehl <florz(a)florz.de>
---
src/southbridge/via/vt8237r/Kconfig | 4 ++++
src/southbridge/via/vt8237r/lpc.c | 9 +++++++++
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig
index d0a6deb..e4f73da 100644
--- a/src/southbridge/via/vt8237r/Kconfig
+++ b/src/southbridge/via/vt8237r/Kconfig
@@ -31,3 +31,7 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/via/vt8237r/bootblock.c"
depends on SOUTHBRIDGE_VIA_VT8237R
+
+config VT8237R_ON_AFTER_POWER_LOSS
+ bool
+
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index b1e1afe..0e757fe 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -508,6 +508,15 @@ static void vt8237_common_init(struct device *dev)
*/
pci_write_config8(dev, 0x5b, 0xb);
+#if CONFIG_VT8237R_ON_AFTER_POWER_LOSS
+ /* make it so the board unconditionally powers on after loss of power */
+ enables = pci_read_config8(dev, 0x58);
+ pci_write_config8(dev, 0x58, enables & ~0x02);
+ outb(0x0d, 0x70);
+ outb(0x00, 0x71);
+ pci_write_config8(dev, 0x58, enables);
+#endif
+
/* Set 0x58 to 0x43 APIC and RTC. */
pci_write_config8(dev, 0x58, 0x43);
Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370
-gerrit
commit c593fc823a5a2bc3de327fea5f1d44cfec8aec15
Author: Florian Zumbiehl <florz(a)florz.de>
Date: Tue Nov 1 20:17:12 2011 +0100
Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz(a)florz.de>
---
src/northbridge/amd/amdk8/raminit_f.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 319293b..dc3addb 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
18, /* *Supported CAS Latencies */
9, /* *Cycle time at highest CAS Latency CL=X */
23, /* *Cycle time at CAS Latency (CLX - 1) */
- 26, /* *Cycle time at CAS Latency (CLX - 2) */
+ 25, /* *Cycle time at CAS Latency (CLX - 2) */
};
u32 dcl, dcm;
u8 common_cl;
Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368
-gerrit
commit 16f7f242b6f4c7d3bdd8d4f41a1f2366a861d06f
Author: Florian Zumbiehl <florz(a)florz.de>
Date: Tue Nov 1 20:16:16 2011 +0100
in vt8237r_enable(), write function enables only to ISA bridge config space
vt8237r_enable() so far wrote the function enable values to the same
offset in the config space of every one of the vt8237's functions,
even though the register is located in the ISA bridge only.
Change-Id: I639586dc238132f5b8d2f320b794948718281b9c
Signed-off-by: Florian Zumbiehl <florz(a)florz.de>
---
src/southbridge/via/vt8237r/vt8237r.c | 14 ++++++++++++--
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 5ba3815..586df66 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -66,11 +66,21 @@ void dump_south(device_t dev)
static void vt8237r_enable(struct device *dev)
{
+ u16 vid, did;
struct southbridge_via_vt8237r_config *sb =
(struct southbridge_via_vt8237r_config *)dev->chip_info;
- pci_write_config8(dev, 0x50, sb->fn_ctrl_lo);
- pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
+ if (dev->path.type == DEVICE_PATH_PCI) {
+ vid = pci_read_config16(dev, PCI_VENDOR_ID);
+ did = pci_read_config16(dev, PCI_DEVICE_ID);
+ if (vid == PCI_VENDOR_ID_VIA &&
+ (did == PCI_DEVICE_ID_VIA_VT8237R_LPC ||
+ did == PCI_DEVICE_ID_VIA_VT8237A_LPC ||
+ did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) {
+ pci_write_config8(dev, 0x50, sb->fn_ctrl_lo);
+ pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
+ }
+ }
/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
}
Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374
-gerrit
commit 8509f2694fd0b03a15eadcbfe10e3c07e0d63cb3
Author: Florian Zumbiehl <florz(a)florz.de>
Date: Tue Nov 1 20:17:41 2011 +0100
compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
Signed-off-by: Florian Zumbiehl <florz(a)florz.de>
---
src/southbridge/via/k8t890/romstrap.inc | 2 +-
src/southbridge/via/vt8237r/lpc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index 5b24948..a3814b0 100644
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -33,7 +33,7 @@ __romstrap_start:
* Below are some Dev0 Func2 HT control registers values,
* depending on strap pin, one of below lines is used.
*/
-#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800
+#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
tblpointer:
.long 0x50220000, 0X619707C2
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index e599517..b1e1afe 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x0c);
#else
- #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+ #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
/* It seems that when we pair with the K8T800, we need to disable
* the A2 mask
*/