coreboot November 2011

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Patch set updated for coreboot: 5efd84c in vt8237r_enable(), write function enables only to ISA bridge config space
by Florian Zumbiehl 04 Nov '11

04 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/368 -gerrit commit 5efd84c282f8f82ab562577c9efbb78c21a0e799 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:16:16 2011 +0100 in vt8237r_enable(), write function enables only to ISA bridge config space vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/vt8237r.c | 14 ++++++++++++-- 1 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815..586df66 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -66,11 +66,21 @@ void dump_south(device_t dev) static void vt8237r_enable(struct device *dev) { + u16 vid, did; struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI) { + vid = pci_read_config16(dev, PCI_VENDOR_ID); + did = pci_read_config16(dev, PCI_DEVICE_ID); + if (vid == PCI_VENDOR_ID_VIA && + (did == PCI_DEVICE_ID_VIA_VT8237R_LPC || + did == PCI_DEVICE_ID_VIA_VT8237A_LPC || + did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ }

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Patch set updated for coreboot: 96dfc09 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
by Florian Zumbiehl 04 Nov '11

04 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/374 -gerrit commit 96dfc09211bb3353570754ca67f3820cf0b50ec0 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:41 2011 +0100 compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/romstrap.inc | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc index 5b24948..a3814b0 100644 --- a/src/southbridge/via/k8t890/romstrap.inc +++ b/src/southbridge/via/k8t890/romstrap.inc @@ -33,7 +33,7 @@ __romstrap_start: * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ -#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD tblpointer: .long 0x50220000, 0X619707C2 diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index e599517..b1e1afe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x48, 0x0c); #else - #if CONFIG_SOUTHBRIDGE_VIA_K8T800 + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */

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Patch set updated for coreboot: 82354c2 support for different location of HT registers in old version of K8T800
by Florian Zumbiehl 04 Nov '11

04 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/373 -gerrit commit 82354c2cd625874c92657024e5d2d0c3c4e5e3b9 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:14 2011 +0100 support for different location of HT registers in old version of K8T800 Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/k8t890/early_car.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index c554c49..da7b4db 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -35,6 +35,12 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; +#if CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD +#define K8X8XX_HT_CFG_BASE 0xc0 +#else +#define K8X8XX_HT_CFG_BASE 0x60 +#endif + /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init. * This will not work for K8T800_OLD, which has a slightly different @@ -43,10 +49,13 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; u8 k8t890_early_setup_ht(void) { - u8 awidth, afreq, cldtfreq, reg; + u8 awidth, afreq, cldtfreq; u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; u16 vldtcaps; +#if !CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + u8 reg; + /* hack, enable NVRAM in chipset */ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); @@ -58,6 +67,7 @@ u8 k8t890_early_setup_ht(void) reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); reg |= 0x1; pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); +#endif /* check if connected non coherent, initcomplete (find the SB on K8 side) */ ldtnr = 0; @@ -73,6 +83,10 @@ u8 k8t890_early_setup_ht(void) print_debug("K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD + print_debug("K8T800_OLD found at LDT "); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_K8M890 @@ -87,19 +101,19 @@ u8 k8t890_early_setup_ht(void) /* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7; width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); print_debug(" Agreed on width: "); print_debug_hex8(width); - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7); /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ width = (width == 0x01) ? 0x11 : 0x00; - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7, width); /* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; @@ -107,15 +121,15 @@ u8 k8t890_early_setup_ht(void) print_debug_hex8(cldtfreq); print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); print_debug_hex16(vldtcaps); if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); } - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); + pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); print_debug("\n"); /* no reset needed */

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Patch set updated for coreboot: c60b3f5 w83627hf: drop Scope(\_SB) from ASL include
by Christoph Grenz 04 Nov '11

04 Nov '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/298 -gerrit commit c60b3f56365d089cd3aa2c744d8944efd49360a2 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Fri Nov 4 01:11:27 2011 +0100 w83627hf: drop Scope(\_SB) from ASL include Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO to appear as child of the root device. devtree.asl then needs to be included at a reasonable position inside the \_SB device tree. Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/devtree.asl | 2496 +++++++++++++++--------------- 1 files changed, 1246 insertions(+), 1250 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl index aa18841..ddac22e 100644 --- a/src/superio/winbond/w83627hf/devtree.asl +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -18,8 +18,8 @@ */ /* - * include this file into a mainboard's DSDT and it will expose the W83627HF - * SuperIO and its functionality in the _SB device tree. + * include this file into a mainboard's DSDT _SB device tree and it will expose the + * W83627HF SuperIO and its functionality. * * Devices are marked as nonexistant if they got 0x00000000 as I/O base address * (compatibility with legacy bios, which disables logical devices that way) @@ -56,960 +56,827 @@ * http://www.itox.com/pages/support/wdt/W83627HF.pdf */ -Scope (\_SB) -{ +Device(SIO) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Winbond W83627HF SuperIO")) + Name (_UID, "w83627hf") - Device(SIO) { - Name (_HID, EisaId("PNP0A05")) - Name (_STR, Unicode("Winbond W83627HF SuperIO")) - Name (_UID, "w83627hf") + /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ + Mutex(CRMX, 1) - /* Mutex for accesses to the configuration ports (prolog and epilog commands are used, so synchronization is useful) */ - Mutex(CRMX, 1) + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, 0x2E, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + RST, 1, /* Soft reset */ + , 7, + Offset (0x07), + LDN, 8, /* Logical device selector */ + Offset (0x20), + DID, 8, /* Device ID */ + DREV, 8, /* Device Revision */ + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + , 1, + IPD, 1, /* Immediate Chip Power Down */ + , 7, + PNPS, 1, /* PnP Address Select Register Default Value Mode */ + , 1, + KBCR, 1, /* KBC enabled after system reset (read-only) */ + , 3, + CLKS, 1, /* Clock select */ + AQ16, 1, /* 16bit Address Qualification */ + FDCT, 1, /* Tristate FDC (?) */ + , 2, + PRTT, 1, /* Tristate parallel port (?) */ + URAT, 1, /* Tristate UART A (?) */ + URBT, 1, /* Tristate UART B (?) */ + , 2, + URAI, 1, /* UART A Legacy IRQ Select Disable */ + URBI, 1, /* UART B Legacy IRQ Select Disable */ + PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ + FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ + , 1, + LCKC, 1, /* Lock Configuration Registers */ + Offset (0x29), + IO3S, 8, /* GPIO3 pin selection register */ + ACTR, 1, /* Logical device activation */ + ACT1, 1, /* Logical part activation 1 (mostly unused) */ + ACT2, 1, /* Logical part activation 2 (mostly unused) */ + , 5, + Offset (0x60), + IO1H, 8, /* First I/O port base - high byte */ + IO1L, 8, /* First I/O port base - low byte */ + IO2H, 8, /* Second I/O port base - high byte */ + IO2L, 8, /* Second I/O port base - low byte */ + Offset (0x70), + IRQ0, 8, /* First IRQ */ + Offset (0x72), + IRQ1, 8, /* First IRQ */ + Offset (0x74), + DMA0, 8, /* DMA */ + Offset (0xE0), + /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + CRE0, 8, + CRE1, 8, + CRE2, 8, + CRE3, 8, + CRE4, 8, + Offset (0xF0), + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8, + OPTA, 8 + } - /* SuperIO configuration ports */ - OperationRegion (CREG, SystemIO, 0x2E, 0x02) - Field (CREG, ByteAcc, NoLock, Preserve) - { - ADDR, 8, - DATA, 8 - } - IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) - { - Offset (0x02), - RST, 1, /* Soft reset */ - , 7, - Offset (0x07), - LDN, 8, /* Logical device selector */ - Offset (0x20), - DID, 8, /* Device ID */ - DREV, 8, /* Device Revision */ - FDPW, 1, /* FDC Power Down */ - , 2, - PRPW, 1, /* PRT Power Down */ - UAPW, 1, /* UART A Power Down */ - UBPW, 1, /* UART B Power Down */ - HWPW, 1, /* HWM Power Down */ - , 1, - IPD, 1, /* Immediate Chip Power Down */ - , 7, - PNPS, 1, /* PnP Address Select Register Default Value Mode */ - , 1, - KBCR, 1, /* KBC enabled after system reset (read-only) */ - , 3, - CLKS, 1, /* Clock select */ - AQ16, 1, /* 16bit Address Qualification */ - FDCT, 1, /* Tristate FDC (?) */ - , 2, - PRTT, 1, /* Tristate parallel port (?) */ - URAT, 1, /* Tristate UART A (?) */ - URBT, 1, /* Tristate UART B (?) */ - , 2, - URAI, 1, /* UART A Legacy IRQ Select Disable */ - URBI, 1, /* UART B Legacy IRQ Select Disable */ - PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ - FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ - , 1, - LCKC, 1, /* Lock Configuration Registers */ - Offset (0x29), - IO3S, 8, /* GPIO3 pin selection register */ - ACTR, 1, /* Logical device activation */ - ACT1, 1, /* Logical part activation 1 (mostly unused) */ - ACT2, 1, /* Logical part activation 2 (mostly unused) */ - , 5, - Offset (0x60), - IO1H, 8, /* First I/O port base - high byte */ - IO1L, 8, /* First I/O port base - low byte */ - IO2H, 8, /* Second I/O port base - high byte */ - IO2L, 8, /* Second I/O port base - low byte */ - Offset (0x70), - IRQ0, 8, /* First IRQ */ - Offset (0x72), - IRQ1, 8, /* First IRQ */ - Offset (0x74), - DMA0, 8, /* DMA */ - Offset (0xE0), - /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ - CRE0, 8, - CRE1, 8, - CRE2, 8, - CRE3, 8, - CRE4, 8, - Offset (0xF0), - /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ - OPT1, 8, - OPT2, 8, - OPT3, 8, - OPT4, 8, - OPT5, 8, - OPT6, 8, - OPT7, 8, - OPT8, 8, - OPT9, 8, - OPTA, 8 - } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ + IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ + }) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) /* Announce the used I/O ports to the OS */ - IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) /* this port is used in some configurations, so announce it to be sure */ - }) + /* Enter configuration mode (and aquire mutex) + Method must be run before accesssing the configuration region. + */ + Method (ENCM) + { + Acquire (CRMX, 0xFFFF) + Store (0x87, ADDR) + Store (0x87, ADDR) + } - /* Enter configuration mode (and aquire mutex) - Method must be run before accesssing the configuration region. - */ - Method (ENCM) - { - Acquire (CRMX, 0xFFFF) - Store (0x87, ADDR) - Store (0x87, ADDR) + /* Exit configuration mode (and release mutex) + Method must be run after accessing the configuration region. + */ + Method (EXCM) + { + Release (CRMX) + Store (0xAA, ADDR) + } + + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + Method (_PSC) { + ENCM () + Store (IPD, Local0) + EXCM () + If (Local0) { Return (2) } + Else { Return (0) } + } + + /* PM: Switch to D0 by setting IPD low */ + Method (_PS0) { + ENCM () + Store (Zero, IPD) + EXCM () + } + + /* PM: Switch to D2 by setting IPD high */ + Method (_PS2) { + ENCM () + Store (One, IPD) + EXCM () + } + + #ifndef NO_W83627HF_FDC + /* =================== Floppy Disk Controller ================ */ + Device (FDC0) { + Name (_HID, EisaId ("PNP0700")) + Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) + Name (_UID, "w83627hf-fdc") + + #ifndef NO_W83627HF_FDC_ENUM + /* Initialization method: Should be run once on boot + If FDC is active, enumerate all connected devices */ + Method (_INI) { + ENCM () + Store (0x00, LDN) + Store (ACTR, Local0) + Store (IO1H, Local1) + Store (IO1L, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or(Local1, Local2, Local1) + If (Local0) { + /* Try probing drives and save result in _FDE */ + PROB(Local1) + } } + #endif - /* Exit configuration mode (and release mutex) - Method must be run after accessing the configuration region. - */ - Method (EXCM) + Method (_STA) { - Release (CRMX) - Store (0xAA, ADDR) + Store (0x00, Local0) + ENCM () + Store (0x00, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) + } + EXCM () + Return (Local0) } - /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } ENCM () - Store (IPD, Local0) + Store (FDPW, Local0) EXCM () - If (Local0) { Return (2) } + If (Local0) { Return (1) } Else { Return (0) } } - - /* PM: Switch to D0 by setting IPD low */ Method (_PS0) { ENCM () - Store (Zero, IPD) + Store (Zero, FDPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, FDPW) EXCM () } - /* PM: Switch to D2 by setting IPD high */ - Method (_PS2) { + Method (_DIS) + { ENCM () - Store (One, IPD) + Store (0x00, LDN) + Store (Zero, ACTR) EXCM () } - #ifndef NO_W83627HF_FDC - /* =================== Floppy Disk Controller ================ */ - Device (FDC0) { - Name (_HID, EisaId ("PNP0700")) - Name (_STR, Unicode ("W83627HF Floppy Disk Controller")) - Name (_UID, "w83627hf-fdc") + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + ENCM () + Store (0x00, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - #ifndef NO_W83627HF_FDC_ENUM - /* Initialization method: Should be run once on boot - If FDC is active, enumerate all connected devices */ - Method (_INI) { - ENCM () - Store (0x00, LDN) - Store (ACTR, Local0) - Store (IO1H, Local1) - Store (IO1L, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or(Local1, Local2, Local1) - If (Local0) { - /* Try probing drives and save result in _FDE */ - PROB(Local1) - } - } - #endif + Return (CRS) + } - Method (_STA) + Name (_PRS, ResourceTemplate () + { + StartDependentFnNoPri () { - Store (0x00, Local0) - ENCM () - Store (0x00, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} } + EndDependentFn () + }) - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (FDPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, FDPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, FDPW) - EXCM () - } + #ifndef NO_W83627HF_FDC_ENUM + Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + #endif - Method (_DIS) + Method (PROB, 1) { + #ifndef NO_W83627HF_FDC_ENUM + /* Try probing drives and save result in _FDE + Probing is done through selecting and activating a drive + and reading 0x03F7 aka the "shared IDE and floppy register" + as any value there besides zero seems to indicate a + connected drive. + */ + OperationRegion (FIO1, SystemIO, Arg0, 0x06) + Field (FIO1, ByteAcc, NoLock, Preserve) { - ENCM () - Store (0x00, LDN) - Store (Zero, ACTR) - EXCM () + Offset(0x02), + SELE, 2, + RSTL, 1, + IDMA, 1, + ACT1, 1, + ACT2, 1, + ACT3, 1, + ACT4, 1, + Offset(0x04), + BSY1, 1, + BSY2, 1, + BSY3, 1, + BSY4, 1, + BUSY, 1, + NDMA, 1, + IODI, 1, + RDY, 1, + DATA, 8, } + OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x06, IO0) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - ENCM () - Store (0x00, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + CreateByteField (_FDE, 3, FD1) + CreateByteField (_FDE, 7, FD2) + CreateByteField (_FDE, 11, FD3) + CreateByteField (_FDE, 15, FD4) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + Store(One, ACT1) + Store(0, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD1) } - Return (CRS) - } + Store(Zero, ACT1) + Store(One, ACT2) + Store(1, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD2) } - Name (_PRS, ResourceTemplate () - { - StartDependentFnNoPri () - { - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - } - EndDependentFn () - }) + Store(Zero, ACT2) + Store(One, ACT3) + Store(2, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD3) } - #ifndef NO_W83627HF_FDC_ENUM - Name(_FDE, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}) + Store(Zero, ACT3) + Store(One, ACT4) + Store(3, SELE) + Sleep(0x64) + If (FIO2) { Store (One, FD4) } + Store(Zero, ACT4) + Store(Zero, SELE) #endif - - Method (PROB, 1) { - #ifndef NO_W83627HF_FDC_ENUM - /* Try probing drives and save result in _FDE - Probing is done through selecting and activating a drive - and reading 0x03F7 aka the "shared IDE and floppy register" - as any value there besides zero seems to indicate a - connected drive. - */ - OperationRegion (FIO1, SystemIO, Arg0, 0x06) - Field (FIO1, ByteAcc, NoLock, Preserve) - { - Offset(0x02), - SELE, 2, - RSTL, 1, - IDMA, 1, - ACT1, 1, - ACT2, 1, - ACT3, 1, - ACT4, 1, - Offset(0x04), - BSY1, 1, - BSY2, 1, - BSY3, 1, - BSY4, 1, - BUSY, 1, - NDMA, 1, - IODI, 1, - RDY, 1, - DATA, 8, - } - OperationRegion (FIO2, SystemIO, 0x3F7, 0x01) - - CreateByteField (_FDE, 3, FD1) - CreateByteField (_FDE, 7, FD2) - CreateByteField (_FDE, 11, FD3) - CreateByteField (_FDE, 15, FD4) - - Store(One, ACT1) - Store(0, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD1) } - - Store(Zero, ACT1) - Store(One, ACT2) - Store(1, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD2) } - - Store(Zero, ACT2) - Store(One, ACT3) - Store(2, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD3) } - - Store(Zero, ACT3) - Store(One, ACT4) - Store(3, SELE) - Sleep(0x64) - If (FIO2) { Store (One, FD4) } - Store(Zero, ACT4) - Store(Zero, SELE) - #endif - } + } - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQ0) {} - DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQ0._INT, IRQL) - CreateByteField (Arg0, DMA0._DMA, DMCH) + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQ0) {} + DMA (Compatibility, NotBusMaster, Transfer8, DMA0) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQ0._INT, IRQL) + CreateByteField (Arg0, DMA0._DMA, DMCH) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (0, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (One, ACTR) - EXCM () + ENCM () + Store (0, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (One, ACTR) + EXCM () - /* Try probing drives and save result in _FDE */ - PROB(IOA0) - } + /* Try probing drives and save result in _FDE */ + PROB(IOA0) } - #endif + } + #endif - #ifndef NO_W83627HF_PPORT - /* ======================== Parallel Port ======================== */ - /* Currently no ECP support */ - Device (PAR0) { - Name (_HID, EisaId ("PNP0400")) - Name (_DDN, "LPT1") - Name (_UID, "w83627hf-pport") + #ifndef NO_W83627HF_PPORT + /* ======================== Parallel Port ======================== */ + /* Currently no ECP support */ + Device (PAR0) { + Name (_HID, EisaId ("PNP0400")) + Name (_DDN, "LPT1") + Name (_UID, "w83627hf-pport") - Method (MODE, 1) { - And(Arg0, 0x07, Local0) - ENCM () - Store (0x01, LDN) - And(OPT1, 0x3, Local1) - Or(Local1, Local0, OPT1) - EXCM() - } + Method (MODE, 1) { + And(Arg0, 0x07, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + Or(Local1, Local0, OPT1) + EXCM() + } - Method (_INI) - { - /* Deactivate DMA, even if set by BIOS. We don't announce it - through _CRS and it's only useful in ECP mode which we - don't support at the moment. */ - ENCM () - Store (0x01, LDN) - Store (0x04, DMA0) - EXCM () - } + Method (_INI) + { + /* Deactivate DMA, even if set by BIOS. We don't announce it + through _CRS and it's only useful in ECP mode which we + don't support at the moment. */ + ENCM () + Store (0x01, LDN) + Store (0x04, DMA0) + EXCM () + } - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x01, LDN) - And(OPT1, 0x3, Local1) - If (ACTR) { - If (LNotEqual(Local1, 2)) { - Store (0x0D, Local0) - } Else { - Store (0x0D, Local0) - } - } - ElseIf (LOr (IO1H, IO1L)) - { + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x01, LDN) + And(OPT1, 0x3, Local1) + If (ACTR) { + If (LNotEqual(Local1, 2)) { + Store (0x0D, Local0) + } Else { Store (0x0D, Local0) } - EXCM () - Return (Local0) - } - - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (PRPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, PRPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, PRPW) - EXCM () } - - Method (_DIS) { - ENCM () - Store (0x01, LDN) - Store (Zero, ACTR) - EXCM () - } - - Method (_CRS) + ElseIf (LOr (IO1H, IO1L)) { - Name (CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (CRS, IO0._MIN, IOP0) - CreateWordField (CRS, IO0._MAX, IOR0) - CreateByteField (CRS, IO0._ALN, IOAL) - CreateByteField (CRS, IO0._LEN, IOLE) - CreateWordField (CRS, IRQX._INT, IRQW) - - ENCM () - Store (0x01, LDN) - Store (IO1L, Local0) - Store (IO1H, Local1) - Store (OPT1, Local2) - Store (IRQ0, Local5) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local1) + Store (0x0D, Local0) + } + EXCM () + Return (Local0) + } - And(Local2, 0x3, Local3) - And(Local2, 0x4, Local4) - If (Local4) { - Store(0x04, IOAL) - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (PRPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, PRPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, PRPW) + EXCM () + } - Store(Local1, IOP0) - Store(Local1, IOR0) + Method (_DIS) { + ENCM () + Store (0x01, LDN) + Store (Zero, ACTR) + EXCM () + } - If (LEqual (Local0, 0xBC)) - { - Store (0x04, IOLE) - } - Else - { - Store (0x08, IOLE) - } + Method (_CRS) + { + Name (CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x04, 0x08, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (CRS, IO0._MIN, IOP0) + CreateWordField (CRS, IO0._MAX, IOR0) + CreateByteField (CRS, IO0._ALN, IOAL) + CreateByteField (CRS, IO0._LEN, IOLE) + CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local0) - ShiftLeft (Local0, Local5, IRQW) + ENCM () + Store (0x01, LDN) + Store (IO1L, Local0) + Store (IO1H, Local1) + Store (OPT1, Local2) + Store (IRQ0, Local5) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local1) - Return (CRS) + And(Local2, 0x3, Local3) + And(Local2, 0x4, Local4) + If (Local4) { + Store(0x04, IOAL) } - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,1) - { - IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,1) - { - IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,1) - { - IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) - { - IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) - { - IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) - { - IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,1) - { - IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn () - }) + Store(Local1, IOP0) + Store(Local1, IOR0) - Method (_SRS, 1, Serialized) + If (LEqual (Local0, 0xBC)) { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 4, 4, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO0._MIN, IOA1) - CreateByteField (Arg0, IO0._ALN, IOAL) - CreateByteField (Arg0, IO0._LEN, IOLE) - CreateWordField (Arg0, IRQX._INT, IRQL) - - If (LEqual(IOAL, 4)) { - Store(0x0, Local2) - } else { - Store(0x1, Local2) - } + Store (0x04, IOLE) + } + Else + { + Store (0x08, IOLE) + } - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Store (One, Local0) + ShiftLeft (Local0, Local5, IRQW) - ENCM () - Store (0x01, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - /*Mode*/ - Store (OPT1, Local3) - And (Local3, 0xF8, Local3) - Or (Local2, Local3, OPT1) - /*DMA off*/ - Store (0x04, DMA0) - /*IRQ*/ - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - Store (Local3, IRQ0) - /*Activate*/ - Store (One, ACTR) - EXCM () - } + Return (CRS) } - #endif - - #ifndef NO_W83627HF_UARTA - /* =========================== UART A ============================ */ - Device (SER0) { - Name (_HID, EisaId ("PNP0501")) - Name (_UID, "w83627hf-uarta") - Name (_DDN, "COM1") - Method (_STA) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,1) { - Store (0x00, Local0) - ENCM () - Store (0x02, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + IO (Decode16, 0x0378, 0x0378, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UAPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } + StartDependentFn (0,1) + { + IO (Decode16, 0x0278, 0x0278, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - Method (_PS0) { - ENCM () - Store (Zero, UAPW) - EXCM () + StartDependentFn (0,1) + { + IO (Decode16, 0x03BC, 0x03BC, 0x04, 0x04) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - Method (_PS1) { - ENCM () - Store (One, UAPW) - EXCM () + StartDependentFn (0,0) + { + IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_DIS) + StartDependentFn (0,0) { - ENCM () - Store (0x02, LDN) - Store (Zero, ACTR) - EXCM () + IO (Decode16, 0x0278, 0x0278, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Method (_CRS) + StartDependentFn (2,0) { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x02, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - - Return (CRS) + IO (Decode16, 0x0100, 0x0FFC, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } - - Name (_PRS, ResourceTemplate () + StartDependentFn (2,1) { - StartDependentFn (0,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() - }) + IO (Decode16, 0x0100, 0x0FFC, 0x04, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn () + }) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 6, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 4, 4, IO0) + IRQNoFlags (IRQX) {} + }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO0._MIN, IOA1) + CreateByteField (Arg0, IO0._ALN, IOAL) + CreateByteField (Arg0, IO0._LEN, IOLE) + CreateWordField (Arg0, IRQX._INT, IRQL) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + If (LEqual(IOAL, 4)) { + Store(0x0, Local2) + } else { + Store(0x1, Local2) + } - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (2, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (0x01, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + /*Mode*/ + Store (OPT1, Local3) + And (Local3, 0xF8, Local3) + Or (Local2, Local3, OPT1) + /*DMA off*/ + Store (0x04, DMA0) + /*IRQ*/ + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) + Store (Local3, IRQ0) + /*Activate*/ + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_UARTB - /* =========================== UART B ============================ */ - Device (SER1) { - Name (_HID, EisaId ("PNP0501")) - Name (_UID, "w83627hf-uartb") - Name (_DDN, "COM2") + #ifndef NO_W83627HF_UARTA + /* =========================== UART A ============================ */ + Device (SER0) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uarta") + Name (_DDN, "COM1") - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x02, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) { - Store (0x00, Local0) - ENCM () - Store (0x03, LDN) - If (LNot(And(OPT2, 0x30))) - { - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UBPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, UBPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, UBPW) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UAPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UAPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UAPW) + EXCM () + } - Method (_DIS) - { - ENCM () - Store (0x03, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x02, LDN) + Store (Zero, ACTR) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x02, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 6, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) - - ENCM () - Store (3, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (2, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_IRDA - /* ======================== UART B (IRDA) ======================== */ - Device (IRDA) { - Name (_HID, EisaId ("PNP0510")) - Name (_UID, "w83627hf-irda") - Name (_STR, Unicode("IrDA Port")) + #ifndef NO_W83627HF_UARTB + /* =========================== UART B ============================ */ + Device (SER1) { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, "w83627hf-uartb") + Name (_DDN, "COM2") - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (LNot(And(OPT2, 0x30))) { - Store (0x00, Local0) - ENCM () - Store (0x03, LDN) - If (And(OPT2, 0x30)) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) { - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (LOr (IO1H, IO1L)) - { - Store (0x0D, Local0) - } + Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (UBPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, UBPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, UBPW) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } - Method (_DIS) - { - ENCM () - Store (0x03, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) - Return (CRS) + Return (CRS) + } + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (1,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (1,0) { - IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (0,0) { - IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - StartDependentFn (2,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) - - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - ENCM () - Store (3, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_CIR - /* ========================= Consumer IR ========================= */ - Device (CIR0) { - Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ - Name (_UID, "w83627hf-cir") - Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) + #ifndef NO_W83627HF_IRDA + /* ======================== UART B (IRDA) ======================== */ + Device (IRDA) { + Name (_HID, EisaId ("PNP0510")) + Name (_UID, "w83627hf-irda") + Name (_STR, Unicode("IrDA Port")) - Method (_STA) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x03, LDN) + If (And(OPT2, 0x30)) { - Store (0x00, Local0) - ENCM () - Store (0x06, LDN) If (ACTR) { Store (0x0F, Local0) } @@ -1017,508 +884,637 @@ Scope (\_SB) { Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_DIS) - { - ENCM () - Store (0x06, LDN) - Store (Zero, ACTR) - EXCM () - } + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } + ENCM () + Store (UBPW, Local0) + EXCM () + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, UBPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, UBPW) + EXCM () + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) - IRQNoFlags (IRQX) {6} - }) - ENCM () - Store (0x03, LDN) - Store(IO1H, Local1) - Store(IO1L, Local0) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local1, 8, Local1) - Or (Local1, Local0, Local0) + Method (_DIS) + { + ENCM () + Store (0x03, LDN) + Store (Zero, ACTR) + EXCM () + } - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (1,0) { + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + StartDependentFn (0,0) { + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + StartDependentFn (2,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} + } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) - IRQNoFlags () {3,4,5,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 8, IO0) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) - - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local3) - Subtract (Local3, 0x01, Local3) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - ENCM () - Store (6, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () - } + ENCM () + Store (3, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () } - #endif + } + #endif - #ifndef NO_W83627HF_KBC - /* ===================== Keyboard Controller ===================== */ - Device (KBD0) { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, 0x0B03D041) - Name (_UID, "w83627hf-kbc") + #ifndef NO_W83627HF_CIR + /* ========================= Consumer IR ========================= */ + Device (CIR0) { + Name (_HID, EisaId ("WEC1022")) /* Should be the correct one */ + Name (_UID, "w83627hf-cir") + Name (_STR, Unicode("Winbond Consumer Infrared Transceiver")) - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x05, LDN) - If (ACTR) { - Store (0x0F, Local0) - } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x06, LDN) + If (ACTR) { + Store (0x0F, Local0) } - - Method (_DIS) + ElseIf (LOr (IO1H, IO1L)) { - ENCM () - Store (0x05, LDN) - Store (Zero, ACTR) - EXCM () - Notify(PS2M, 1) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) - Store(IRQ0, Local4) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Method (_DIS) + { + ENCM () + Store (0x06, LDN) + Store (Zero, ACTR) + EXCM () + } - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) + IRQNoFlags (IRQX) {6} + }) + ENCM () + Store (0x03, LDN) + Store(IO1H, Local1) + Store(IO1L, Local0) + Store(IRQ0, Local2) + EXCM () + ShiftLeft(Local1, 8, Local1) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local5) - ShiftLeft (Local5, Local4, IRQW) + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0100, 0x0FF8, 0x08, 0x08) + IRQNoFlags () {3,4,5,7,9,10,11,12} } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 8, IO0) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IO (Decode16, 0, 0, 1, 1, IO0) - IO (Decode16, 0, 0, 1, 1, IO1) - IRQNoFlags (IRQX) {} - }) - CreateWordField (Arg0, IO0._MIN, IOA0) - CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - Divide(IOA0, 256, Local0, Local1) - ShiftRight(Local1, 8, Local1) + FindSetLeftBit (IRQL, Local3) + Subtract (Local3, 0x01, Local3) - Divide(IOA1, 256, Local2, Local3) - ShiftRight(Local1, 8, Local1) + ENCM () + Store (6, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #endif - FindSetLeftBit (IRQL, Local4) - Subtract (Local4, 0x01, Local4) + #ifndef NO_W83627HF_KBC + /* ===================== Keyboard Controller ===================== */ + Device (KBD0) { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, 0x0B03D041) + Name (_UID, "w83627hf-kbc") - ENCM () - Store (5, LDN) - Store (Local1, IO1H) - Store (Local0, IO1L) - Store (Local3, IO2H) - Store (Local2, IO2L) - Store (Local3, IRQ0) - Store (One, ACTR) - EXCM () + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (ACTR) { + Store (0x0F, Local0) } - } - #ifndef NO_W83627HF_PS2M - Device (PS2M) { - Name (_HID, EisaId ("PNP0F13")) - Name (_UID, "w83627hf-ps2m") - - Method (_STA) + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { - Store (0x00, Local0) - ENCM () - Store (0x05, LDN) - If (LAnd(ACTR, IRQ1) ) { - Store (0x0F, Local0) - } - ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) - { - Store (0x0D, Local0) - } - EXCM () - Return (Local0) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } - Method (_DIS) - { - ENCM () - Store (0x05, LDN) - Store (Zero, IRQ1) - EXCM () - } + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, ACTR) + EXCM () + Notify(PS2M, 1) + } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IRQNoFlags (IRQX) {} - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) - }) - ENCM () - Store (0x05, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IO2H, Local2) - Store(IO2L, Local3) - Store(IRQ1, Local4) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ0, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) - ShiftLeft(Local2, 8, Local2) - Or (Local1, Local0, Local0) + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - CreateWordField (CRS, IO1._MIN, I1MI) - Store (Local2, I1MI) - CreateWordField (CRS, IO1._MAX, I1MA) - Store (Local2, I1MA) + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local5) - ShiftLeft (Local5, Local4, IRQW) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) + + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} } + EndDependentFn() + }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0,0) { - IRQNoFlags () {12} - } - StartDependentFn (2,0) { - IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} - } - EndDependentFn() + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IO (Decode16, 0, 0, 1, 1, IO0) + IO (Decode16, 0, 0, 1, 1, IO1) + IRQNoFlags (IRQX) {} }) + CreateWordField (Arg0, IO0._MIN, IOA0) + CreateWordField (Arg0, IO1._MIN, IOA1) + CreateByteField (Arg0, IRQX._INT, IRQL) - Method (_SRS, 1, Serialized) - { - Name (TMPL, ResourceTemplate () { - IRQNoFlags (IRQX) {} - }) - CreateByteField (Arg0, IRQX._INT, IRQL) + Divide(IOA0, 256, Local0, Local1) + ShiftRight(Local1, 8, Local1) - FindSetLeftBit (IRQL, Local0) - Subtract (Local0, 0x01, Local0) + Divide(IOA1, 256, Local2, Local3) + ShiftRight(Local1, 8, Local1) - ENCM () - Store (5, LDN) - Store (Local0, IRQ1) - /* Only activates if KBD is active */ - Store (One, ACTR) - EXCM () - } - } - #endif - #endif + FindSetLeftBit (IRQL, Local4) + Subtract (Local4, 0x01, Local4) - #ifndef NO_W83627HF_GAME - /* ========================== Game Port ========================== */ - Device (GAME) { - Name (_HID, EisaId ("PNPB02F")) - Name (_STR, Unicode ("Joystick/Game Port")) - Name (_UID, "w83627hf-game") + ENCM () + Store (5, LDN) + Store (Local1, IO1H) + Store (Local0, IO1L) + Store (Local3, IO2H) + Store (Local2, IO2L) + Store (Local3, IRQ0) + Store (One, ACTR) + EXCM () + } + } + #ifndef NO_W83627HF_PS2M + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, "w83627hf-ps2m") - Method (_STA) { - ENCM () - Store(0, Local0) - Store (0x07, LDN) - If (LOr(IO1L, IO1H)) { - If (LOr(ACTR, ACT1)) { - Store (0x0F, Local0) - } - Else { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x05, LDN) + If (LAnd(ACTR, IRQ1) ) { + Store (0x0F, Local0) } - - Method (_CRS) + ElseIf (Lor(LOr (IO1H, IO1L), LOr (IO2H, IO2L))) { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x07, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IRQ0, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) - - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) - - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } - - Return (CRS) + Store (0x0D, Local0) } + EXCM () + Return (Local0) + } + Method (_DIS) + { + ENCM () + Store (0x05, LDN) + Store (Zero, IRQ1) + EXCM () } - #endif - #ifndef NO_W83627HF_MIDI - /* ========================== MIDI Port ========================== */ - Device (MIDI) { - Name (_HID, EisaId ("PNPB006")) - Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) - Name (_UID, "w83627hf-midi") + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IRQNoFlags (IRQX) {} + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO1) + }) + ENCM () + Store (0x05, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IO2H, Local2) + Store(IO2L, Local3) + Store(IRQ1, Local4) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + ShiftLeft(Local2, 8, Local2) + Or (Local1, Local0, Local0) - Method (_STA) { - ENCM () - Store(0, Local0) - Store (0x07, LDN) - If (LOr(IO2L, IO2H)) { - If (LOr(ACTR, ACT2)) { - Store (0x0F, Local0) - } - Else { - Store (0x0D, Local0) - } - } - EXCM () - Return (Local0) - } + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x07, LDN) - Store(IO2H, Local0) - Store(IO2L, Local1) - Store(IRQ1, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + CreateWordField (CRS, IO1._MIN, I1MI) + Store (Local2, I1MI) + CreateWordField (CRS, IO1._MAX, I1MA) + Store (Local2, I1MA) - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local5) + ShiftLeft (Local5, Local4, IRQW) - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } + Return (CRS) + } - Return (CRS) + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0,0) { + IRQNoFlags () {12} + } + StartDependentFn (2,0) { + IRQNoFlags () {1,3,4,5,6,7,9,10,11,12} } + EndDependentFn() + }) + + Method (_SRS, 1, Serialized) + { + Name (TMPL, ResourceTemplate () { + IRQNoFlags (IRQX) {} + }) + CreateByteField (Arg0, IRQX._INT, IRQL) + FindSetLeftBit (IRQL, Local0) + Subtract (Local0, 0x01, Local0) + + ENCM () + Store (5, LDN) + Store (Local0, IRQ1) + /* Only activates if KBD is active */ + Store (One, ACTR) + EXCM () } - #endif + } + #endif + #endif + + #ifndef NO_W83627HF_GAME + /* ========================== Game Port ========================== */ + Device (GAME) { + Name (_HID, EisaId ("PNPB02F")) + Name (_STR, Unicode ("Joystick/Game Port")) + Name (_UID, "w83627hf-game") - /* ==== Suspend LED control if it is connected to the SuperIO ==== */ - Method (SLED, 1) { + Method (_STA) { ENCM () - Store (9, LDN) - Store(OPT4, Local0) - And(Local0, 63, Local0) - Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO1L, IO1H)) { + If (LOr(ACTR, ACT1)) { + Store (0x0F, Local0) + } + Else { + Store (0x0D, Local0) + } + } EXCM () + Return (Local0) } - /* ===== Power LED control if it is connected to the SuperIO ===== */ - Method (PLED, 1) { + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x01, IO0) + IRQNoFlags (IRQX) {} + }) ENCM () - Store (8, LDN) - Store(OPT4, Local0) - And(Local0, 63, Local0) - Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + Store (0x07, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ0, Local2) EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + + Return (CRS) } - #ifndef NO_W83627HF_HWMON - /* ====================== Hardware Monitor ======================= */ - Device (HMON) { - Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID - Name (_STR, Unicode("W83627 Hardware Monitor")) - Name (_UID, "w83627hf-hwmon") + } + #endif + + #ifndef NO_W83627HF_MIDI + /* ========================== MIDI Port ========================== */ + Device (MIDI) { + Name (_HID, EisaId ("PNPB006")) + Name (_STR, Unicode ("MPU-401 Compatible MIDI Port")) + Name (_UID, "w83627hf-midi") - Method (_STA) - { - Store (0x00, Local0) - ENCM () - Store (0x0B, LDN) - If (ACTR) { + Method (_STA) { + ENCM () + Store(0, Local0) + Store (0x07, LDN) + If (LOr(IO2L, IO2H)) { + If (LOr(ACTR, ACT2)) { Store (0x0F, Local0) } - ElseIf (LOr (IO1H, IO1L)) - { + Else { Store (0x0D, Local0) } - EXCM () - Return (Local0) } + EXCM () + Return (Local0) + } - Method (_PSC) { - Store(^^_PSC (), Local0) - If (Local0) { Return (Local0) } - ENCM () - Store (HWPW, Local0) - EXCM () - If (Local0) { Return (1) } - Else { Return (0) } - } - Method (_PS0) { - ENCM () - Store (Zero, HWPW) - EXCM () - } - Method (_PS1) { - ENCM () - Store (One, HWPW) - EXCM () + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x02, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x07, LDN) + Store(IO2H, Local0) + Store(IO2L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) } - Method (_CRS) - { - Name (CRS, ResourceTemplate () { - IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) - IRQNoFlags (IRQX) {} - }) - ENCM () - Store (0x0B, LDN) - Store(IO1H, Local0) - Store(IO1L, Local1) - Store(IRQ1, Local2) - EXCM () - ShiftLeft(Local0, 8, Local0) - Or (Local1, Local0, Local0) + Return (CRS) + } - CreateWordField (CRS, IO0._MIN, IMIN) - Store (Local0, IMIN) - CreateWordField (CRS, IO0._MAX, IMAX) - Store (Local0, IMAX) + } + #endif - If (Local2) { - CreateWordField (CRS, IRQX._INT, IRQW) - Store (One, Local3) - ShiftLeft (Local3, Local2, IRQW) - } - Return (CRS) + /* ==== Suspend LED control if it is connected to the SuperIO ==== */ + Method (SLED, 1) { + ENCM () + Store (9, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + /* ===== Power LED control if it is connected to the SuperIO ===== */ + Method (PLED, 1) { + ENCM () + Store (8, LDN) + Store(OPT4, Local0) + And(Local0, 63, Local0) + Or(Local0, ShiftLeft(And(Arg0, 0x03), 6), OPT4) + EXCM () + } + + #ifndef NO_W83627HF_HWMON + /* ====================== Hardware Monitor ======================= */ + Device (HMON) { + Name (_HID, EisaId ("PNP0C02")) // TODO: find better matching ID + Name (_STR, Unicode("W83627 Hardware Monitor")) + Name (_UID, "w83627hf-hwmon") + + Method (_STA) + { + Store (0x00, Local0) + ENCM () + Store (0x0B, LDN) + If (ACTR) { + Store (0x0F, Local0) + } + ElseIf (LOr (IO1H, IO1L)) + { + Store (0x0D, Local0) } + EXCM () + Return (Local0) } - #endif - /* Returns the wake source register. - It is cleared after reading. - Bit 0: Keyboard wake-up event - Bit 1: Mouse wake-up event - Bit 2: Power button event - Bit 3: CIR wake-up event - Bit 4: Power loss event - Bit 5: VSB power loss status - */ - Method (WAKS) { + Method (_PSC) { + Store(^^_PSC (), Local0) + If (Local0) { Return (Local0) } ENCM () - Store (0x0A, LDN) - Store (CRE3, Local0) + Store (HWPW, Local0) EXCM () - Return (Local0) + If (Local0) { Return (1) } + Else { Return (0) } + } + Method (_PS0) { + ENCM () + Store (Zero, HWPW) + EXCM () + } + Method (_PS1) { + ENCM () + Store (One, HWPW) + EXCM () + } + + Method (_CRS) + { + Name (CRS, ResourceTemplate () { + IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0) + IRQNoFlags (IRQX) {} + }) + ENCM () + Store (0x0B, LDN) + Store(IO1H, Local0) + Store(IO1L, Local1) + Store(IRQ1, Local2) + EXCM () + ShiftLeft(Local0, 8, Local0) + Or (Local1, Local0, Local0) + + CreateWordField (CRS, IO0._MIN, IMIN) + Store (Local0, IMIN) + CreateWordField (CRS, IO0._MAX, IMAX) + Store (Local0, IMAX) + + If (Local2) { + CreateWordField (CRS, IRQX._INT, IRQW) + Store (One, Local3) + ShiftLeft (Local3, Local2, IRQW) + } + Return (CRS) } } + #endif + + /* Returns the wake source register. + It is cleared after reading. + Bit 0: Keyboard wake-up event + Bit 1: Mouse wake-up event + Bit 2: Power button event + Bit 3: CIR wake-up event + Bit 4: Power loss event + Bit 5: VSB power loss status + */ + Method (WAKS) { + ENCM () + Store (0x0A, LDN) + Store (CRE3, Local0) + EXCM () + Return (Local0) + } }

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Patch merged into coreboot/master: 1eebc29 add support for writing to SMBus with vt8237
by gerrit＠coreboot.org 03 Nov '11

03 Nov '11

the following patch was just integrated into master: commit 1eebc2948d93462056bfd2690132e18f2e1ed0dc Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:17:13 2011 +0100 add support for writing to SMBus with vt8237 Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Build-Tested: build bot (Jenkins) at Thu Nov 3 07:06:02 2011, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Thu Nov 3 21:39:03 2011, giving +2 See http://review.coreboot.org/372 for details. -gerrit

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Patch merged into coreboot/master: 68c5545 add support for 1106:3188 (host controller of the old version of k8t800)
by gerrit＠coreboot.org 03 Nov '11

03 Nov '11

the following patch was just integrated into master: commit 68c554550f59bd96caace96260ae2e30ed55ceb4 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:02 2011 +0100 add support for 1106:3188 (host controller of the old version of k8t800) Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> Build-Tested: build bot (Jenkins) at Thu Nov 3 07:37:29 2011, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Thu Nov 3 21:32:39 2011, giving +2 See http://review.coreboot.org/381 for details. -gerrit

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Patch merged into coreboot/master: 02418b7 libpayload: Reduce verbosity in USB stack
by gerrit＠coreboot.org 03 Nov '11

03 Nov '11

the following patch was just integrated into master: commit 02418b7f4316fc8b3f0ba48a853d5dce702cff08 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Jun 8 15:36:55 2011 +0200 libpayload: Reduce verbosity in USB stack The USB stack is pretty noisy. Reduce the output to a sane level. Change-Id: I250949e5cf74a8c6d43822b2e7487143b2ae1c65 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Thu Nov 3 12:28:35 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Nov 3 19:14:06 2011, giving +2 See http://review.coreboot.org/393 for details. -gerrit

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Patch merged into coreboot/master: 2daa28a libpayload: Put coreboot version into lib_sysinfo
by gerrit＠coreboot.org 03 Nov '11

03 Nov '11

the following patch was just integrated into master: commit 2daa28a3b187d92eb9ad11534f6b96e65e83225f Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Thu Oct 20 14:06:26 2011 +0200 libpayload: Put coreboot version into lib_sysinfo Change-Id: I22319efe90e475c66b9556f734a7a5e54f7c59bc Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Thu Nov 3 12:38:56 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Nov 3 19:02:52 2011, giving +2 See http://review.coreboot.org/394 for details. -gerrit

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Re: [coreboot] Coreboot and Epia M-II
by Elisenda Cuadros 03 Nov '11

03 Nov '11

Hi, I´m using the default seabios config. I think it has debug level set to 8. Now I compiled Seabios with debug set to 10. I attach you a new log. I tried compiling coreboot with FILO (from menuconfig) and it works perfect. I can boot linux with this rom. I tried to compile seabios outside coreboot menuconfig, adding it like an elf executable. Same problem. The problem for me it´s that I want to use this board with FreeBSD and If I´m not wrong Seabios is the only way to do it. Thanks for all. Regards, Elisenda On 02/11/2011 16:19, QingPei Wang wrote: > the coreboot.rom seems fine, do you use the default seabios config, > try to set the debug level of seabios to 8 to show more messages. >

2 1

Patch set updated for coreboot: d7775ef Add support for A-Open DXPL Plus-U motherboard
by Kyösti Mälkki 03 Nov '11

03 Nov '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/303 -gerrit commit d7775efdcbeb08dcc24f9f145f2020f1310b768c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 3 15:22:01 2011 +0200 Add support for A-Open DXPL Plus-U motherboard This is an old (pre-2005) entry-level server mainboard. The code is adapted from mainboard/intel/xe7501devkit. Featured chips: - Dual socket604 - E7505 northbridge - 82801DB southbridge (with EHCI debug port) - 82870p2 PCI-X bridge - LPC47M102S-MC super-io - 512kB FWH flash (flashrom does the job well) What works: - Dual-Xeon P4/HT boot with microcode update - RAM: registered ECC DDR266 in dual-channel - PCI-X slot interrupts with ACPI and I/O apic - On-board PCI-X GbE and SCSI - ACPI power-off and wakeup with PME# Notes : - Current ACPI is more or less a mess - Interrupts do not route correctly with PIRQ - MP-table is not implemented - Issues with reboots remain (cold and warm) - Many superio devices are disabled by default - Audio codec is not investigated Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/Kconfig | 3 + src/mainboard/aopen/Kconfig | 17 ++ src/mainboard/aopen/dxplplusu/Kconfig | 63 ++++++++ src/mainboard/aopen/dxplplusu/Makefile.inc | 1 + src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl | 86 ++++++++++ src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl | 70 ++++++++ src/mainboard/aopen/dxplplusu/acpi/i82801db.asl | 171 ++++++++++++++++++++ src/mainboard/aopen/dxplplusu/acpi/p64h2.asl | 97 ++++++++++++ src/mainboard/aopen/dxplplusu/acpi/power.asl | 95 +++++++++++ src/mainboard/aopen/dxplplusu/acpi/scsi.asl | 63 ++++++++ src/mainboard/aopen/dxplplusu/acpi/superio.asl | 183 ++++++++++++++++++++++ src/mainboard/aopen/dxplplusu/acpi_tables.c | 163 +++++++++++++++++++ src/mainboard/aopen/dxplplusu/bus.h | 42 +++++ src/mainboard/aopen/dxplplusu/chip.h | 4 + src/mainboard/aopen/dxplplusu/devicetree.cb | 87 ++++++++++ src/mainboard/aopen/dxplplusu/dsdt.asl | 113 +++++++++++++ src/mainboard/aopen/dxplplusu/fadt.c | 166 ++++++++++++++++++++ src/mainboard/aopen/dxplplusu/irq_tables.c | 76 +++++++++ src/mainboard/aopen/dxplplusu/mainboard.c | 7 + src/mainboard/aopen/dxplplusu/romstage.c | 103 ++++++++++++ 20 files changed, 1610 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 13032a6..549962f 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -14,6 +14,8 @@ config VENDOR_ADVANTECH bool "Advantech" config VENDOR_AMD bool "AMD" +config VENDOR_AOPEN + bool "AOpen" config VENDOR_ARIMA bool "Arima" config VENDOR_ARTEC_GROUP @@ -131,6 +133,7 @@ source "src/mainboard/abit/Kconfig" source "src/mainboard/advansus/Kconfig" source "src/mainboard/advantech/Kconfig" source "src/mainboard/amd/Kconfig" +source "src/mainboard/aopen/Kconfig" source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" source "src/mainboard/asi/Kconfig" diff --git a/src/mainboard/aopen/Kconfig b/src/mainboard/aopen/Kconfig new file mode 100644 index 0000000..5b5497c --- /dev/null +++ b/src/mainboard/aopen/Kconfig @@ -0,0 +1,17 @@ +if VENDOR_AOPEN + +choice + prompt "Mainboard model" + +config BOARD_AOPEN_DXPLPLUSU + bool "DXPL Plus-U" + +endchoice + +source "src/mainboard/aopen/dxplplusu/Kconfig" + +config MAINBOARD_VENDOR + string + default "AOpen" + +endif # VENDOR_AOPEN diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig new file mode 100644 index 0000000..c3025d1 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -0,0 +1,63 @@ +if BOARD_AOPEN_DXPLPLUSU + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7505 + select SOUTHBRIDGE_INTEL_I82870 + select SOUTHBRIDGE_INTEL_I82801DX + select SUPERIO_SMSC_LPC47M10X + select ROMCC + select HAVE_HARD_RESET +# select HAVE_PIRQ_TABLE +# select PIRQ_ROUTE + select UDELAY_TSC + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_512 + +config MAINBOARD_DIR + string + default aopen/dxplplusu + +config MAINBOARD_PART_NUMBER + string + default "DXPL Plus-U" + +config DCACHE_RAM_BASE + hex + default 0xcf000 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + +config IRQ_SLOT_COUNT + int + default 12 + +config BOARD_HAS_FADT + bool + default y + +config LOGICAL_CPUS + bool + default n + +config MAX_CPUS + int + default 4 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x0 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x0 + +endif # BOARD_AOPEN_DXPLPLUSU diff --git a/src/mainboard/aopen/dxplplusu/Makefile.inc b/src/mainboard/aopen/dxplplusu/Makefile.inc new file mode 100644 index 0000000..0f285cd --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/Makefile.inc @@ -0,0 +1 @@ +ROMCCFLAGS := -mcpu=p4 -O2 diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl new file mode 100644 index 0000000..0e84d44 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (MBRS) +{ + Name (_HID, EisaId ("PNP0C01")) + Name (_UID, 0x01) + Name (MSBF, ResourceTemplate () + { + /* System memory */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, + MaxNotFixed, Prefetchable, ReadWrite, + 0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C, + AddressRangeMemory, TypeStatic) + + /* Top Of Low Memory */ + Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D) + + /* 640kB who wants more? */ + Memory32Fixed (ReadWrite, 0x0, 0xA0000, ) + + /* 64k BIOS bootblock */ + Memory32Fixed (ReadOnly, 0xF0000, 0x10000,) + + /* ISA memory hole 15-16 MB ? */ + /* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */ + /* ISA memory hole 14-15 MB ? */ + /* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */ + + /* Local APIC */ + Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML) + CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM) + CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM) + + And (\_SB.PCI0.RLAR, 0x03FF, Local1) + Increment (Local1) + If (LGreater (Local1, 0x40)) + { + ShiftLeft (Local1, 0x1A, LELM) + } + + + CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00) + CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01) + CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2) + And (\_SB.PCI0.TOLM, 0xF800, Local1) + ShiftRight (Local1, 0x04, Local1) + Decrement (Local1) + If (LGreater (Local1, 0x10)) + { + Subtract (Local1, 0x0F, Local1) + Store (ShiftLeft (Local1, 0x14), MEM2) + Store (0x01000000, MS00) + Store (MS00, MS01) + } + + Return (MSBF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl new file mode 100644 index 0000000..0effe93 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name (PBRS, ResourceTemplate () +{ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, ) + + /* System IO */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic) + IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, ) + + /* Video RAM */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000A0000, 0x000BFFFF, + 0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic) + + /* Video ROM */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000C0000, 0x000C7FFF, + 0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic) + + /* Option ROMs ? */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x000C8000, 0x000DFFFF, + 0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic) + + /* Top Of Lowmemory to IOAPIC */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, 0x02000000, 0xFEBFFFFF, + 0x00000000, 0xFCC00000, ,, _Y08, AddressRangeMemory, TypeStatic) +}) + + +Method (_CRS, 0, NotSerialized) +{ + + /* Top Of Lowmemory to IOAPIC */ + CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML) + CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM) + And (\_SB.PCI0.TOLM, 0xF800, Local1) + ShiftRight (Local1, 0x04, Local1) + ShiftLeft (Local1, 0x14, MEML) + Subtract (0xFEC00000, MEML, LENM) + + Return (PBRS) +} + +Method (_STA, 0, NotSerialized) +{ + Return (0x0F) +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl new file mode 100644 index 0000000..bb8c321 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (USB0) +{ + Name (_ADR, 0x001D0000) + Name (_PRW, Package () { 0x03, 0x05 }) + + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB1) +{ + Name (_ADR, 0x001D0001) + Name (_PRW, Package () { 0x04, 0x05 }) + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB2) +{ + Name (_ADR, 0x001D0002) + Name (_PRW, Package () { 0x0C, 0x05 }) + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device (USB3) +{ + Name (_ADR, 0x001D0007) + Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */ + OperationRegion (USBS, PCI_Config, 0x00, 0x0100) + Field (USBS, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), URES, 8 + } +} + +Device(PCI5) +{ + Name (_ADR, 0x001E0000) + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + Name (_PRT, Package() { + Package() { 0x0003ffff, 0, 0, 20 }, + Package() { 0x0003ffff, 1, 0, 21 }, + Package() { 0x0003ffff, 2, 0, 22 }, + Package() { 0x0003ffff, 3, 0, 23 }, + }) +} + +Device (ICH0) +{ + Name (_ADR, 0x001F0000) + OperationRegion (D310, PCI_Config, 0x00, 0xFF) + Field (D310, ByteAcc, NoLock, Preserve) + { + Offset (0x40), PBAR, 16, + Offset (0x58), GBAR, 16, + } + + OperationRegion (ACPI, SystemIO, 0x0400, 0xC0) + Field (ACPI, ByteAcc, NoLock, Preserve) + { + Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8, + Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8, + Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8, + Offset (0xB8), GPLV,8 + } + + Name (MSBF, ResourceTemplate () + { + /* IOAPIC 0 */ + Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000,) + + IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO) + IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO) + + /* 8254 legacy irq */ + IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,) + + /* reset generator */ + IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, ) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1) + CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2) + CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL) + + Store (PBAR, Local0) + If ( Land(Local0, 0x01) ) + { + And (Local0, 0xFFFE, Local0) + Store (Local0, IOA1) + Store (Local0, IOA2) + Store (0x80, IOAL) + } Else { + Store (0x00, IOAL) + } + + CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1) + CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2) + CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL) + + Store (GBAR, Local0) + If ( Land(Local0, 0x01) ) { + And (Local0, 0xFFFE, Local0) + Store (Local0, IOS1) + Store (Local0, IOS2) + Store (0x40, IOSL) + } Else { + Store (0x00, IOSL) + } + Return (MSBF) + } + + Device (FWH) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + + Name (MSBG, ResourceTemplate () { + Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,) + Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,) + }) + + Method (_CRS, 0, NotSerialized) + { + Return (MSBG) + } + } + + Device (SMSC) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) + #include "acpi/superio.asl" + } + +} + + + diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl new file mode 100644 index 0000000..3958699 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Interrupt routing for PCI 03:xx.x */ + +/* I/O APIC id 0x3 */ +Device(PBIO) +{ + Name (_HID, "ACPI000A") + Name (_ADR, 0x001c0000) +} + +/* PCI-X bridge */ +Device(P64B) +{ + Name (_ADR, 0x001d0000) + Name (_PRT, Package() { + Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */ + Package() { 0x0002ffff, 1, 0, 25 }, + Package() { 0x0002ffff, 2, 0, 26 }, + Package() { 0x0002ffff, 3, 0, 27 }, + Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */ + Package() { 0x0003ffff, 1, 0, 29 }, + Package() { 0x0003ffff, 2, 0, 30 }, + Package() { 0x0003ffff, 3, 0, 31 }, + Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */ + }) + + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) + Field (PBPC, ByteAcc, NoLock, Preserve) + { + Offset (0x3E), BCRL, 8, BCRH, 8 + } + + + Device (ETH0) + { + Name (_ADR, 0x00040000) + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + } +} + + +/* Interrupt routing for PCI 04:xx.x */ + +/* I/O APIC id 0x4 */ +Device(PAIO) +{ + Name (_HID, "ACPI000A") + Name (_ADR, 0x001e0000) +} + +/* PCI-X bridge */ +Device(P64A) +{ + Name (_ADR, 0x001f0000) + Name (_PRT, Package() { + Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */ + Package() { 0x0002ffff, 1, 0, 49 }, + Package() { 0x0002ffff, 2, 0, 50 }, + Package() { 0x0002ffff, 3, 0, 51 }, + Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */ + Package() { 0x0003ffff, 1, 0, 53 }, + Package() { 0x0003ffff, 2, 0, 54 }, + Package() { 0x0003ffff, 3, 0, 55 }, + Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */ + Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */ + }) + + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) + Field (PBPC, ByteAcc, NoLock, Preserve) + { + Offset (0x3E), BCRL, 8, BCRH, 8 + } + + #include "acpi/scsi.asl" +} + + diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl new file mode 100644 index 0000000..92db59e --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/power.asl @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Board powers on with button or PME# from on-board GbE wake-on-lan. + * Board shuts down to S5/G2. Any other power management is untested. + */ + +Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) +Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) +Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 }) +Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 }) +Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 }) + +Scope (\_GPE) +{ + Method (_L03, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB0, 0x02) + } + Method (_L04, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB1, 0x02) + } + + /* WOL header */ + Method (_L08, 0, NotSerialized) + { + Notify (\_SB.PCI0.PCI5, 0x02) + Notify (\_SB.SLBT, 0x02) + } + + /* PME# */ + Method (_L0B, 0, NotSerialized) + { +#if 1 + Notify (\_SB.LID0, 0x02) +#else + Notify (\_SB.PCI0.HLIB.P64B.ETH0, 0x02) + Notify (\_SB.PCI0.HLIB.P64B, 0x02) + Notify (\_SB.PCI0.HLIB.P64A, 0x02) +#endif + } + + Method (_L0C, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB2, 0x02) + } + + /* PME_B0_STS# */ + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.USB3, 0x02) + } +} + +/* Clear power buttons */ +Method (\_INI, 0, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H) + Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H) +} + +/* Prepare To Sleep */ +Method (\_PTS, 1, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H) + Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L) +} + +/* System Wake */ +Method (\_WAK, 1, NotSerialized) +{ + Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H) + Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L) + + Return ( Package() { 0x0, 0x0 } ) +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl new file mode 100644 index 0000000..7215a33 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W + * U320 SCSI dual-channel controller + */ + +Device (SCS0) +{ + Name (_ADR, 0x00040000) + OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) + Field (SCSC, ByteAcc, NoLock, Preserve) + { + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 + } +} + +Device (SCS1) +{ + Name (_ADR, 0x00040001) + OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) + Field (SCSC, ByteAcc, NoLock, Preserve) + { + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 + } +} + +#if 0 +/* Set subsystem id for both SCSI devices. + * It may require some delay on wake-up before this can be done. + */ + Method ( ) + { + Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW) + Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID) + And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW) + + Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW) + Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID) + And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW) + } +#endif + diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl new file mode 100644 index 0000000..15b5e08 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* SuperIO GPIO configuration via logical device 0x0A */ + +Name (MSBF, ResourceTemplate () +{ + IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B) +}) + +OperationRegion (LPC0, SystemIO, 0x0E00, 0x60) +Field (LPC0, ByteAcc, NoLock, Preserve) +{ + PME0, 8, + Offset (0x02), PME2,8, + Offset (0x04), PME4,8, + Offset (0x0A), PMEA,8, + Offset (0x23), + GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8, + GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8, + GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8, + GC40,8, GC41,8, GC42,8, GC43,8, + + Offset (0x3F), + GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8, + GC60,8, GC61,8, + + Offset (0x4B), + GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8, + Offset (0x56), FAN1,8, + Offset (0x5D), LED1,8, LED2,8, +} + +OperationRegion (SMC1, SystemIO, 0x2E, 0x02) +Field (SMC1, ByteAcc, NoLock, Preserve) +{ + INDX, 8, DATA, 8 +} + +IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) +{ + Offset (0x07), LDN, 8, + Offset (0x22), PWRC, 8, + Offset (0x30), ACTR, 8, + Offset (0x60), + IOAH, 8, IOAL, 8, + IOBH, 8, IOBL, 8, + + Offset (0x70), INTR, 8, + Offset (0x72), INT1, 8, + Offset (0x74), DMCH, 8, + Offset (0xB2), SPS1, 8, SPS2, 8, + Offset (0xB8), D2TS, 8, + Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8, + Offset (0xF4), WDTC, 8, + Offset (0xF6), GP01, 8, GP02, 8, GP04, 8 +} + +Method (ECFG, 0, NotSerialized) +{ + Store (0x55, INDX) +} +Method (XCFG, 0, NotSerialized) +{ + Store (0xAA, INDX) +} + +Method (_CRS, 0, NotSerialized) +{ + CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1) + CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2) + CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML) + + ECFG () + Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN) + Store (0x00, IOM1) + Store (0x00, IOM2) + Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1) + ShiftLeft (IOM1, 0x08, IOM1) + Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1) + Store (IOM1, IOM2) + If (LNotEqual (IOM1, 0x00)) + { + Store (0x80, IOML) + } + XCFG () + + Return (MSBF) +} + + +Method (_INI, 0, NotSerialized) +{ + /* GPIO configuration */ + Store (0x00, GC10) + Store (0x81, GC11) + Store (0x00, GC17) + Store (0x0c, GC21) + Store (0x00, GC22) + Store (0x04, GC27) + Store (0x04, GC30) + Store (0x01, GC31) + Store (0x01, GC32) + Store (0x01, GC33) + Store (0x01, GC34) /* GPI password jumper */ + Store (0x01, GC35) /* GPI scsi enable jumper */ +#if 1 + Store (0x01, GC42) /* GPI */ +#else + Store (0x84, GC42) /* nIO_PME */ +#endif + Store (0x86, GC60) /* led 1 */ + Store (0x81, GC61) /* led 2 ?? */ + + /* GPIO initial output levels */ + Store (GP_1, Local0) + And( Local0, 0x7C, Local0) + Or ( Local0, 0x81, Local0) + Store (Local0, GP_1) + + Store (GP_2, Local0) + And( Local0, 0xFE, Local0) + Or ( Local0, 0x00, Local0) + Store (Local0, GP_2) + + Store (GP_3, Local0) + And( Local0, 0x7F, Local0) + Or ( Local0, 0x80, Local0) + Store (Local0, GP_3) + + Store (GP_4, Local0) + And( Local0, 0x7F, Local0) + Or ( Local0, 0x00, Local0) + Store (Local0, GP_4) + + /* Power Led */ + Store (LED1, Local0) + And( Local0, 0xfc, Local0) + Or ( Local0, 0x01, Local0) + Store (Local0, LED1) + +} + +Method (MLED, 1, NotSerialized) +{ + If (LEqual (Arg0, 0x00)) + { + Store (0x00, LED1) + } + + If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02))) + { + Store (0x01, LED1) + } + + If (LEqual (Arg0, 0x03)) + { + Store (0x02, LED1) + } + + If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05))) + { + Store (0x03, LED1) + } +} + diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c new file mode 100644 index 0000000..b7c789a --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer <stepan(a)openbios.org> + * (C) 2005 Stefan Reinauer + * (C) 2005 Digital Design Corporation + * + * Ported to Intel XE7501DEVKIT by Agami Aruma + * Ported to AOpen DXPL Plus-U by Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <assert.h> +#include "bus.h" + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int irq_start = 0; + device_t dev = 0; + struct resource* res = NULL; + + // SJM: Hard-code CPU LAPIC entries for now + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); + + // Southbridge IOAPIC + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + // P64H2 Bus B IOAPIC + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); + if (!dev) + BUG(); // Config.lb error? + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + // P64H2 Bus A IOAPIC + dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); + if (!dev) + BUG(); // Config.lb error? + res = find_resource(dev, PCI_BASE_ADDRESS_0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start); + irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + + + // Map ISA IRQ 0 to IRQ 2 + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0); + + // IRQ9 differs from ISA standard - ours is active high, level-triggered + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD); + + return current; +} + +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_madt_t *madt; + acpi_facs_t *facs; + acpi_fadt_t *fadt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + memcpy(dsdt,(void *)AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + ALIGN_CURRENT; + memcpy(dsdt,(void *)AmlCode, dsdt->length); + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt,dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdp,fadt); + + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp,madt); + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} + diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h new file mode 100644 index 0000000..7cb188d --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/bus.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DXPLPLUSU_BUS_H_INCLUDED +#define DXPLPLUSU_BUS_H_INCLUDED + +// These were determined by seeing how coreboot enumerates the various +// PCI (and PCI-like) buses on the board. + +#define PCI_BUS_ROOT 0 +#define PCI_BUS_AGP 1 // AGP +#define PCI_BUS_E7501_HI_B 2 // P64H2#1 +#define PCI_BUS_P64H2_B 3 // P64H2#1 bus B +#define PCI_BUS_P64H2_A 4 // P64H2#1 bus A +#define PCI_BUS_ICH4 5 // ICH4 + +// IOAPIC addresses determined by coreboot enumeration. +// Someday add functions to get APIC IDs and versions from the chips themselves. + +#define IOAPIC_ICH4 2 +#define IOAPIC_P64H2_BUS_B 3 // IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 +#define IOAPIC_P64H2_BUS_A 4 // IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 + +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-4 and P64-H2 + +#endif diff --git a/src/mainboard/aopen/dxplplusu/chip.h b/src/mainboard/aopen/dxplplusu/chip.h new file mode 100644 index 0000000..06f11d0 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations mainboard_ops; + +struct mainboard_config { +}; diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb new file mode 100644 index 0000000..d465a82 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -0,0 +1,87 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/e7505 + + device lapic_cluster 0 on + chip cpu/intel/socket_mPGA604 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 0.0 on end # Chipset host controller + device pci 0.1 on end # Host RASUM controller + device pci 2.0 on # Hub interface B + chip southbridge/intel/i82870 # P64H2 + device pci 1c.0 on end # IOAPIC - bus B + device pci 1d.0 on end # Hub to PCI-B bridge + device pci 1e.0 on end # IOAPIC - bus A + device pci 1f.0 on end # Hub to PCI-A bridge + end + end + device pci 4.0 off end # (undocumented) + device pci 6.0 off end # (undocumented) + chip southbridge/intel/i82801dx + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.7 on end # USB EHCI + device pci 1e.0 on # Hub to PCI bridge + device pci 2.0 off end + end + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m10x + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.a on # ACPI + io 0x60 = 0x0e00 + end + end + end + device pci 1f.1 on end # IDE + device pci 1f.3 on end # SMBus + device pci 1f.5 on end # AC97 Audio + device pci 1f.6 off end # AC97 Modem + end # SB + end # PCI_DOMAIN +end diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl new file mode 100644 index 0000000..31cfa88 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/dsdt.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x04, // DSDT revision: ACPI v4.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20111103 // OEM revision +) { + +Scope(\_SB) +{ + Device(PCI0) { + Name (_HID, EISAID("PNP0A03")) + Name (_ADR, 0x00) + Name (_PRT, Package() { + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 23 }, + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 17 }, + }) + + #include "acpi/e7505_sec.asl" + + OperationRegion (I750, PCI_Config, 0x00, 0x0100) + Field (I750, ByteAcc, NoLock, Preserve) + { + Offset (0xC4), + TOLM, 16, /* Top of Low Memory */ + RBAR, 16, /* REMAP_BASE */ + RLAR, 16 /* REMAP_LIMIT */ + } + } + + #include "acpi/e7505_pri.asl" + + + Device (PWBT) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x08, 0x05 }) + } + + Device (SLBT) + { + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x0B, 0x05 }) + } + + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x0B, 0x05 }) + } + +} + +Scope(\_SB.PCI0) +{ + + Device(PCI1) + { + Name (_ADR, 0x00010000) + Name (_PRT, Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + }) + } + + Device(HLIB) + { + Name (_ADR, 0x00020000) + Name (_PRT, Package() { + Package() { 0x001dffff, 0, 0, 18 }, + Package() { 0x001dffff, 1, 0, 18 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 18 }, + Package() { 0x001fffff, 0, 0, 18 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 18 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + + #include "acpi/p64h2.asl" + } + + #include "acpi/i82801db.asl" +} + +#include "acpi/power.asl" + +} + diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c new file mode 100644 index 0000000..9707b9d --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> + +/* FIXME: This needs to go into a separate .h file + * to be included by the ich7 smi handler, ich7 smi init + * code and the mainboard fadt. + */ +#define APM_CNT 0x0 /* ACPI mode only */ +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x0 +#define ACPI_DISABLE 0xAA +#define ACPI_ENABLE 0x55 +#define S4_BIOS 0x77 +#define GNVS_UPDATE 0xea + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 4; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = ACPI_ENABLE; + fadt->acpi_disable = ACPI_DISABLE; + fadt->s4bios_req = S4_BIOS; + fadt->pstate_cnt = PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x28; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + // XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; /* CST_CONTROL; */ + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 85; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = 0x03; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x28; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c new file mode 100644 index 0000000..9f3315b --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/irq_tables.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include "bus.h" + +#define UNUSED_INTERRUPT {0, 0} +#define PIRQ_A 0x60 +#define PIRQ_B 0x61 +#define PIRQ_C 0x62 +#define PIRQ_D 0x63 +#define PIRQ_E 0x68 +#define PIRQ_F 0x69 +#define PIRQ_G 0x6A +#define PIRQ_H 0x6B + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, // Size of this struct in bytes + 0, // PCI bus number on which the interrupt router resides + PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router + 0, // PCI-exclusive IRQ bitmap + PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router + PCI_DEVICE_ID_INTEL_82801DB_LPC, // Device ID of compatible PCI interrupt router + 0, // Additional miniport information + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero + 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) + { + // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space + // This was determined from linux-2.6.11/arch/i386/pci/irq.c + // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 + // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 + // Not sure why IRQ9 isn't routable (inherited from Tyan S2735) + + // INTA# INTB# INTC# INTD# + // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu + + {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus + {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1 + + {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE + + {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI + + {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // 32-bit slot + + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/aopen/dxplplusu/mainboard.c b/src/mainboard/aopen/dxplplusu/mainboard.c new file mode 100644 index 0000000..2d41509 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/mainboard.c @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("AOpen DXPL Plus-U Mainboard") +}; + diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c new file mode 100644 index 0000000..92ce896 --- /dev/null +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> +#include <stdlib.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> + +#include "southbridge/intel/i82801dx/i82801dx.h" +#include "southbridge/intel/i82801dx/early_smbus.c" +#include "southbridge/intel/i82801dx/reset.c" +#include "northbridge/intel/e7505/raminit.h" +#include "northbridge/intel/e7505/debug.c" +#include "superio/smsc/lpc47m10x/early_serial.c" + +#if !CONFIG_CACHE_AS_RAM +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#endif +#include "cpu/x86/bist.h" + +#include <spd.h> + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +/* Cache-As-Ram compiles for this board, but with the CPUs I have, + * it halts on boot while in Local Apic ID negotiation. + */ + +#if CONFIG_CACHE_AS_RAM +#define BOARD_MAIN(x) void main(x) +#define early_mtrr_init() do {} while (0) +#else +#define BOARD_MAIN(x) static void main(x) +#endif + +#include "northbridge/intel/e7505/raminit.c" +#include "northbridge/intel/e7505/reset_test.c" +#include "lib/generic_sdram.c" + +// This function MUST appear last (ROMCC limitation) +BOARD_MAIN(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { 0x50, 0x52, 0, 0 }, + .channel1 = { 0x51, 0x53, 0, 0 }, + }, + }; + + if (bist == 0) { + // Skip this if there was a built in self test failure + early_mtrr_init(); + enable_lapic(); + } + + // Get the serial port running and print a welcome banner + lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + // Halt if there was a built in self test failure + report_bist_failure(bist); + + // If this is a warm boot, some initialization can be skipped + if (!bios_reset_detected()) { + enable_smbus(); + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + } + + // NOTE: ROMCC dies with an internal compiler error + // if the following line is removed. + print_debug("SDRAM is up.\r\n"); + +}

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coreboot November 2011