coreboot October 2011

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501 discussions

Sun Ultra 40 M2 port - TrainDQSPos: MutualCSPassW[48] then reboot
by Nick 31 Oct '11

31 Oct '11

Hello, I'm working on a coreboot port to the Sun Ultra 40 M2. This is an MCP55 based dual socket Opteron system with two memory banks per node (four slots each.) It's currently in a dual dualcore configuration with 8GB of DDR2 memory, two 2GB sticks per bank. I'm using the Tyan s2912 mainboard definition as a base (not fam10.) I've observed a couple different behaviours. 1) Upon cold boot, the system will sometimes (not always) reboot itself approx every 2 seconds before getting to raminit - it always passes the first stage of HT negotiation but (after the soft-reset) fails on the line "dev1 output ln_width1=0x" (then resets without completing the value) 2) The system usually gets to raminit at least initially. Memory detection goes very quickly until "TrainDQSPos: MutualCSPassW[48]" where it then slows to a crawl. After this, issue 1 reoccurs over and over - http://pastebin.com/aNUZf1Hr (issues 2, followed by issue 1) 3) When the system is booted to linux and the vendor code is (hot) swapped for coreboot and warm rebooted initiated, the system will slowly move past "TrainDQSPos: MutualCSPassW[48]" without rebooting (issues #2 is always followed by a reboot) and has completed cache to ram, then rebooted. This is the furthest it has gotten - http://pastebin.com/5vQPgWQn Any advice would be greatly appreciated! Regards, Nick

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Patch merged into coreboot/master: d39d04c Fix usb debug dongle support
by gerrit＠coreboot.org 30 Oct '11

30 Oct '11

the following patch was just integrated into master: commit d39d04c45dd0a66b7d7349fd38012abe4a5b76bf Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 30 09:57:35 2011 +0100 Fix usb debug dongle support - move enable_usbdebug() declaration to usbdebug.h - reinitialize debug driver in ramstage, as copying the data structure from romstage doesn't work right now. This way of copying data from romstage to ramstage is really board/cpu specific, and is likely to break often. So don't do it. Change-Id: I394678ded6679c1803e29eb691b926182bdcab68 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sun Oct 30 12:47:32 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Oct 31 04:06:10 2011, giving +2 See http://review.coreboot.org/355 for details. -gerrit

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Patch merged into coreboot/master: 23e3aa2 crossgcc: Fix colors with dash
by gerrit＠coreboot.org 30 Oct '11

30 Oct '11

the following patch was just integrated into master: commit 23e3aa28c92fc2072584584d59a9c9a65ae8f64f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Oct 29 00:00:19 2011 +0200 crossgcc: Fix colors with dash Ubuntu (and probably other distros) have dash as /bin/sh, which doesn't display colors by itself. If /usr/bin/printf is found, it's used instead of the internal printf to re-enable colors. Change-Id: I3e6d413cd0c8a46ef91821d8c07e88166de58af4 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Oct 29 00:16:01 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Oct 30 21:58:41 2011, giving +2 See http://review.coreboot.org/352 for details. -gerrit

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Patch merged into coreboot/master: b403fdf Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
by gerrit＠coreboot.org 30 Oct '11

30 Oct '11

the following patch was just integrated into master: commit b403fdfcb1e44dddee30be9820e7e1db5a41764c Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Oct 30 18:06:58 2011 +0100 Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9 It is meant to be a address and not a dereference. Otherwise MTRR is filled with code and not with the address. This is what I hate at most on the AT&T syntax. Instead of taking the address, it was a dereference. Not greatly visible, except I wondered why opcode is not 0xb4 but 0xa1 and it took another half an our to see it. Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Build-Tested: build bot (Jenkins) at Sun Oct 30 21:25:01 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Oct 30 21:02:23 2011, giving +2 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Oct 30 21:24:13 2011, giving +2 See http://review.coreboot.org/358 for details. -gerrit

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Patch set updated for coreboot: b403fdf Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
by Stefan Reinauer 30 Oct '11

30 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/358 -gerrit commit b403fdfcb1e44dddee30be9820e7e1db5a41764c Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Oct 30 18:06:58 2011 +0100 Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9 It is meant to be a address and not a dereference. Otherwise MTRR is filled with code and not with the address. This is what I hate at most on the AT&T syntax. Instead of taking the address, it was a dereference. Not greatly visible, except I wondered why opcode is not 0xb4 but 0xa1 and it took another half an our to see it. Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram.inc | 2 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 2 +- src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +- src/cpu/intel/model_6fx/cache_as_ram.inc | 2 +- src/cpu/via/car/cache_as_ram.inc | 6 +++--- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 9d2b400..b9e02f3 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -290,7 +290,7 @@ clear_fixed_var_mtrr_out: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 4ad2fce..26fec6e 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -241,7 +241,7 @@ clear_fixed_var_mtrr_out: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index b45599a..9f7ceaf 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -106,7 +106,7 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index fa35fc9..3a12cf6 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -106,7 +106,7 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index a869011..2ba1872 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -113,7 +113,7 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index d0c43c9..ad2805e 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -120,7 +120,7 @@ clear_fixed_var_mtrr_out: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr @@ -166,7 +166,7 @@ clear_fixed_var_mtrr_out: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %esi + movl $copy_and_run, %esi andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei movl %esi, %edi movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx @@ -247,7 +247,7 @@ testok: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl copy_and_run, %eax + movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRBACK, %eax wrmsr

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Patch merged into coreboot/master: 8713588 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.
by gerrit＠coreboot.org 30 Oct '11

30 Oct '11

the following patch was just integrated into master: commit 87135886bc6558aaa43da2189da863362a488e45 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Oct 30 20:30:48 2011 +0100 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c. Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sun Oct 30 20:41:17 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Oct 30 20:31:55 2011, giving +2 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Oct 30 20:49:13 2011, giving +2 See http://review.coreboot.org/360 for details. -gerrit

1 0

New patch to review for coreboot: 8713588 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.
by Stefan Reinauer 30 Oct '11

30 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/360 -gerrit commit 87135886bc6558aaa43da2189da863362a488e45 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Oct 30 20:30:48 2011 +0100 Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c. Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/amd/sr5650/pcie.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 37743ca..eebe711 100755 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -370,8 +370,8 @@ static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) slave_cpl = (u8 *)&pGpp111111; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "buggy gpp3a_configuration\n"); - break; + printk(BIOS_WARNING, "buggy gpp3a_configuration\n"); + return; } value = slave_cpl[dev_index - 4];

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jenkins fails on 3aade48 on unrelated file (was Re: Change in coreboot[master]: w83627hf: drop Scope(\_SB) from ASL include)
by Christoph Grenz 30 Oct '11

30 Oct '11

Hello, jenkins: > [...] > Patch Set 4: Fails > > Build Failed > > http://qa.coreboot.org/job/coreboot-gerrit/671/ : FAILURE jenkins log: > CC cpu/amd/model_10xxx/processor_name.ramstage.o > src/southbridge/amd/sr5650/pcie.c: In function 'sr5650_gpp_sb_init': > src/southbridge/amd/sr5650/pcie.c:377:19: error: 'slave_cpl' may be used > uninitialized in this function [-Werror=uninitialized] > src/southbridge/amd/sr5650/pcie.c:343:6: note: 'slave_cpl' was declared here > CC cpu/amd/model_10xxx/update_microcode.ramstage.o Has anybody an idea where this error comes from? I couldn't find any reference to my patched file there. Thanks, Christoph Grenz

3 2

Patch set updated for coreboot: e9a16dd Fix the build
by Rudolf Marek 30 Oct '11

30 Oct '11

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/359 -gerrit commit e9a16dde3a8334b45ed8860a640f6af997249077 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Oct 30 19:28:08 2011 +0100 Fix the build Just fix the build and print error if buggy gppsb3 is encountered. Change-Id: I8d5ef3777d8a7dfe311657707fbd9e7db81202dc Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/southbridge/amd/sr5650/pcie.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 37743ca..3be7fd1 100755 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -224,7 +224,7 @@ static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev) reg |= 0xFF0BAA0; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); + printk(BIOS_ERR, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); break; } nbmisc_write_index(nb_dev, 0x26, reg); @@ -340,7 +340,7 @@ const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E}; static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) { u8 dev_index; - u8 *slave_cpl; + u8 *slave_cpl = (u8 *) &pGpp111111; u8 value; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; @@ -370,7 +370,7 @@ static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) slave_cpl = (u8 *)&pGpp111111; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "buggy gpp3a_configuration\n"); + printk(BIOS_ERR, "buggy gpp3a_configuration\n"); break; } @@ -411,7 +411,7 @@ static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev) set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); } else { - printk(BIOS_DEBUG, "buggy gpp configuration\n"); + printk(BIOS_ERR, "buggy gpp configuration\n"); } }

1 0

Patch set updated for coreboot: a39f6bb Fix the build
by Rudolf Marek 30 Oct '11

30 Oct '11

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/359 -gerrit commit a39f6bbf6b6994e7bb581bec75ca6f5514d780ee Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Oct 30 19:28:08 2011 +0100 Fix the build Just fix the build and print error if buggy gppsb3 is encountered. Change-Id: I8d5ef3777d8a7dfe311657707fbd9e7db81202dc Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/southbridge/amd/sr5650/pcie.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 37743ca..fbb2e31 100755 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -224,7 +224,7 @@ static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev) reg |= 0xFF0BAA0; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); + printk(BIOS_ERR, "Warning:gpp3a_configuration is not correct. Check you devicetree.cb\n"); break; } nbmisc_write_index(nb_dev, 0x26, reg); @@ -340,7 +340,7 @@ const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E}; static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) { u8 dev_index; - u8 *slave_cpl; + u8 *slave_cpl = &pGpp111111; u8 value; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; @@ -370,7 +370,7 @@ static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev) slave_cpl = (u8 *)&pGpp111111; break; default: /* shouldn't be here. */ - printk(BIOS_DEBUG, "buggy gpp3a_configuration\n"); + printk(BIOS_ERR, "buggy gpp3a_configuration\n"); break; } @@ -411,7 +411,7 @@ static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev) set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8); set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11); } else { - printk(BIOS_DEBUG, "buggy gpp configuration\n"); + printk(BIOS_ERR, "buggy gpp configuration\n"); } }

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coreboot October 2011