Hello,
I'm working on a coreboot port to the Sun Ultra 40 M2. This is an MCP55 based dual socket Opteron system with two memory banks per node (four slots each.)
It's currently in a dual dualcore configuration with 8GB of DDR2 memory, two 2GB sticks per bank.
I'm using the Tyan s2912 mainboard definition as a base (not fam10.) I've observed a couple different behaviours.
1) Upon cold boot, the system will sometimes (not always) reboot itself approx every 2 seconds before getting to raminit - it always passes the first stage of HT negotiation but (after the soft-reset) fails on the line "dev1 output ln_width1=0x" (then resets without completing the value) 2) The system usually gets to raminit at least initially. Memory detection goes very quickly until "TrainDQSPos: MutualCSPassW[48]" where it then slows to a crawl. After this, issue 1 reoccurs over and over - http://pastebin.com/aNUZf1Hr (issues 2, followed by issue 1) 3) When the system is booted to linux and the vendor code is (hot) swapped for coreboot and warm rebooted initiated, the system will slowly move past "TrainDQSPos: MutualCSPassW[48]" without rebooting (issues #2 is always followed by a reboot) and has completed cache to ram, then rebooted. This is the furthest it has gotten - http://pastebin.com/5vQPgWQn
Any advice would be greatly appreciated!
Regards, Nick
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Nick