Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/358
-gerrit
commit 99b9fca4e8726b218538d3fe8ba869ef4ef90ccf
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Sun Oct 30 18:06:58 2011 +0100
Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.
This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.
Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
---
src/cpu/amd/car/cache_as_ram.inc | 2 +-
src/cpu/intel/car/cache_as_ram.inc | 2 +-
src/cpu/intel/model_106cx/cache_as_ram.inc | 2 +-
src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +-
src/cpu/intel/model_6fx/cache_as_ram.inc | 2 +-
src/cpu/via/car/cache_as_ram.inc | 6 +++---
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 9d2b400..b9e02f3 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -290,7 +290,7 @@ clear_fixed_var_mtrr_out:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 4ad2fce..26fec6e 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -241,7 +241,7 @@ clear_fixed_var_mtrr_out:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index b45599a..9f7ceaf 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -106,7 +106,7 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index fa35fc9..3a12cf6 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -106,7 +106,7 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index a869011..2ba1872 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -113,7 +113,7 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index d0c43c9..ad2805e 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -120,7 +120,7 @@ clear_fixed_var_mtrr_out:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
@@ -166,7 +166,7 @@ clear_fixed_var_mtrr_out:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %esi
+ movl $copy_and_run, %esi
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
movl %esi, %edi
movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
@@ -247,7 +247,7 @@ testok:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl copy_and_run, %eax
+ movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
the following patch was just integrated into master:
commit b7ff170a978d5a7d03c5a8c1ef344921b54dad7a
Author: Sven Schnelle <svens(a)stackframe.org>
Date: Sun Oct 30 13:30:36 2011 +0100
inteltool: Add Intel i63xx I/O Controller Hub
Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle <svens(a)stackframe.org>
Build-Tested: build bot (Jenkins) at Sun Oct 30 13:36:45 2011, giving +1
Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Sun Oct 30 13:37:15 2011, giving +2
See http://review.coreboot.org/356 for details.
-gerrit
the following patch was just integrated into master:
commit f6e9e81303cac8567ed2fa9e391020dc501fc4d3
Author: Sven Schnelle <svens(a)stackframe.org>
Date: Sun Oct 30 08:49:43 2011 +0100
remove usbdebug.h include from mainboard/romstage code
No romstage is supposed to use usbdebug functions/defines
directly, so remove all those includes. The usb code is now
called and setup from console code.
Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
Signed-off-by: Sven Schnelle <svens(a)stackframe.org>
Build-Tested: build bot (Jenkins) at Sun Oct 30 12:36:02 2011, giving +1
Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Sun Oct 30 12:37:05 2011, giving +2
See http://review.coreboot.org/354 for details.
-gerrit
the following patch was just integrated into master:
commit 784921939448aae10ee10f02e81af1c1ab866f34
Author: Stefan Reinauer <reinauer(a)google.com>
Date: Tue Oct 11 22:37:59 2011 -0700
Update coreboot cross toolchain to gcc 4.6.1
- Tested on Mac OS X 10.7.1
- Tested on Ubuntu 10.04 LTS (Lucid Lynx)
- Tested on Ubuntu 11.10 (Oneiric Ocelot)
Please test on Windows and other Linux distributions
Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Build-Tested: build bot (Jenkins) at Sat Oct 29 00:25:45 2011, giving +1
Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Sun Oct 30 12:01:01 2011, giving +2
See http://review.coreboot.org/250 for details.
-gerrit