coreboot August 2010

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[commit] r5749 - trunk/src/northbridge/amd/amdmct/mct
by repository service 30 Aug '10

30 Aug '10

Author: kerry Date: Mon Aug 30 11:40:41 2010 New Revision: 5749 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5749 Log: Multi-DIMMS on AMD ddr2 MCT channel B fixed. Signed-off-by: Kerry She <Kerry.she(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Mon Aug 30 09:31:31 2010 (r5748) +++ trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Mon Aug 30 11:40:41 2010 (r5749) @@ -1086,12 +1086,12 @@ *valid = 0; - if (!pDCTstat->GangedMode) { // FIXME: not used. + if (!pDCTstat->GangedMode) { reg_off = 0x100 * Channel; } /* get the local base addr of the chipselect */ - reg = 0x40 + (receiver << 2); + reg = 0x40 + (receiver << 2) + reg_off; val = Get_NB32(dev, reg); val &= ~0x0F;

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AMD ddr MCT channelB patch
by She, Kerry 30 Aug '10

30 Aug '10

Hi, Multi-DIMMS on AMD ddr MCT channel B fixed. Signed-off-by: Kerry She <Kerry.she(a)amd.com>

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[commit] r5748 - in trunk/src/northbridge/amd/amdmct: mct_ddr3 wrappers
by repository service 30 Aug '10

30 Aug '10

Author: zbao Date: Mon Aug 30 09:31:31 2010 New Revision: 5748 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5748 Log: Multi-DIMMS on AMD ddr3 MCT channel B works. Signed-off-by: Kerry She <Kerry.she(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c trunk/src/northbridge/amd/amdmct/wrappers/mcti.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Mon Aug 30 09:24:13 2010 (r5747) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c Mon Aug 30 09:31:31 2010 (r5748) @@ -332,7 +332,6 @@ if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */ continue; - pDCTstat->DqsRdWrPos_Saved = 0; for ( DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) { pDCTstat->DQSDelay = DQSWrDelay; @@ -1174,12 +1173,12 @@ *valid = 0; - if (!pDCTstat->GangedMode) { /* FIXME: not used. */ + if (!pDCTstat->GangedMode) { reg_off = 0x100 * Channel; } /* get the local base addr of the chipselect */ - reg = 0x40 + (receiver << 2); + reg = 0x40 + (receiver << 2) + reg_off; val = Get_NB32(dev, reg); val &= ~0x0F; Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c Mon Aug 30 09:24:13 2010 (r5747) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c Mon Aug 30 09:31:31 2010 (r5748) @@ -22,6 +22,8 @@ { u8 Dimms, DimmNum, MaxDimm, Speed; u32 val; + u32 dct = 0; + u32 reg_off = 0; DimmNum = MrsChipSel >> 20; @@ -32,8 +34,14 @@ MaxDimm = mctGet_NVbits(NV_MAX_DIMMS); Speed = pDCTstat->DIMMAutoSpeed; - /* if (dct == 0) */ - Dimms = pDCTstat->MAdimms[0]; + + if (pDCTstat->CSPresent_DCT[0] > 0) { + dct = 0; + } else if (pDCTstat->CSPresent_DCT[1] > 0 ){ + dct = 1; + } + reg_off = 0x100 * dct; + Dimms = pDCTstat->MAdimms[dct]; val = 0; if (CtrlWordNum == 0) @@ -87,14 +95,21 @@ static void mct_SendCtrlWrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 val) { + u32 reg_off = 0; u32 dev = pDCTstat->dev_dct; - val |= Get_NB32(dev, 0x7C) & ~0xFFFFFF; + if (pDCTstat->CSPresent_DCT[0] > 0) { + reg_off = 0; + } else if (pDCTstat->CSPresent_DCT[1] > 0 ){ + reg_off = 0x100; + } + + val |= Get_NB32(dev, reg_off + 0x7C) & ~0xFFFFFF; val |= 1 << SendControlWord; - Set_NB32(dev, 0x7C, val); + Set_NB32(dev, reg_off + 0x7C, val); do { - val = Get_NB32(dev, 0x7C); + val = Get_NB32(dev, reg_off + 0x7C); } while (val & (1 << SendControlWord)); } @@ -104,6 +119,7 @@ u8 MrsChipSel; u32 dev = pDCTstat->dev_dct; u32 val, cw; + u32 reg_off = 0x100 * dct; mct_Wait(1600); @@ -111,7 +127,7 @@ for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) { if (pDCTstat->CSPresent & (1 << MrsChipSel)) { - val = Get_NB32(dev, 0xA8); + val = Get_NB32(dev, reg_off + 0xA8); val &= ~(0xF << 8); switch (MrsChipSel) { @@ -128,7 +144,7 @@ case 7: val |= (3 << 6) << 8; } - Set_NB32(dev, 0xA8, val); + Set_NB32(dev, reg_off + 0xA8 , val); for (cw=0; cw <=15; cw ++) { mct_Wait(1600); Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c Mon Aug 30 09:24:13 2010 (r5747) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c Mon Aug 30 09:31:31 2010 (r5748) @@ -86,7 +86,7 @@ for (dimm = 0; dimm < MAX_TOTAL_DIMMS; dimm++) { u8 DimmRanks; - if (DimmValid & (1 << dimm)) { + if (DimmValid & (1 << (dimm << 1))) { DimmRanks = 1; if (pDCTstat->DimmDRPresent & (1 << (dimm+dct))) DimmRanks = 2; Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti.h Mon Aug 30 09:24:13 2010 (r5747) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti.h Mon Aug 30 09:31:31 2010 (r5748) @@ -51,9 +51,18 @@ /*---------------------------------------------------------------------------- UPDATE AS NEEDED ----------------------------------------------------------------------------*/ +#ifndef MAX_NODES_SUPPORTED #define MAX_NODES_SUPPORTED 8 +#endif + +#ifndef MAX_DIMMS_SUPPORTED #define MAX_DIMMS_SUPPORTED 8 +#endif + +#ifndef MAX_CS_SUPPORTED #define MAX_CS_SUPPORTED 8 +#endif + #define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_END 0x00000CFF Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Mon Aug 30 09:24:13 2010 (r5747) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Mon Aug 30 09:31:31 2010 (r5748) @@ -40,8 +40,8 @@ val = MAX_NODES_SUPPORTED; break; case NV_MAX_DIMMS: - //val = MAX_DIMMS_SUPPORTED; - val = 8; + val = MAX_DIMMS_SUPPORTED; + //val = 8; break; case NV_MAX_MEMCLK: /* Maximum platform supported memclk */

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amd-mct_ddr3-ChannelB Patch
by She, Kerry 30 Aug '10

30 Aug '10

Hi, Multi-DIMMS on AMD ddr3 MCT channel B works. Signed-off-by: Kerry She <Kerry.she(a)amd.com>

2 1

[commit] r5747 - trunk/src/northbridge/amd/amdmct/mct_ddr3
by repository service 30 Aug '10

30 Aug '10

Author: zbao Date: Mon Aug 30 09:24:13 2010 New Revision: 5747 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5747 Log: Trivial syntax correction of AMD mct_ddr3 dir. Signed-off-by: Kerry She <Kerry.she(a)amd.com> Acked-by: Kerry She <Kerry.she(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Sun Aug 29 01:23:47 2010 (r5746) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Mon Aug 30 09:24:13 2010 (r5747) @@ -2030,7 +2030,7 @@ RegDIMMPresent = 0; pDCTstat->DimmQRPresent = 0; - for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { if (i >= MaxDimms) break; @@ -2214,7 +2214,7 @@ } else { /* Configure DCT1 if unganged and enabled*/ if (!pDCTstat->GangedMode) { - if ( pDCTstat->DIMMValidDCT[1] > 0) { + if (pDCTstat->DIMMValidDCT[1] > 0) { err_code = pDCTstat->ErrCode; /* save DCT0 errors */ pDCTstat->ErrCode = 0; DCTInit_D(pMCTstat, pDCTstat, 1); @@ -2512,7 +2512,7 @@ { u8 ret; - if ( dct == 0) + if (dct == 0) ret = DIMMPresence_D(pMCTstat, pDCTstat); else ret = pDCTstat->ErrCode; Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Sun Aug 29 01:23:47 2010 (r5746) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c Mon Aug 30 09:24:13 2010 (r5747) @@ -446,9 +446,9 @@ printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); for(Channel = 0; Channel < 2; Channel++) { - printk(BIOS_DEBUG, "Channel:%x\n"); + printk(BIOS_DEBUG, "Channel:%x\n", Channel); for(Receiver = 0; Receiver<8; Receiver+=2) { - printk(BIOS_DEBUG, "\t\tReceiver:%x:"); + printk(BIOS_DEBUG, "\t\tReceiver:%x:", Receiver); p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i=0;i<8; i++) { val = p[i];

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amd mct_ddr3 trivial patch
by She, Kerry 30 Aug '10

30 Aug '10

Hi, Trivial syntax correction of AMD mct_ddr3 dir. Signed-off-by: Kerry She <Kerry.she(a)amd.com> Acked-by: Kerry She <Kerry.she(a)amd.com>

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[commit] r5746 - trunk/payloads/libpayload/sample
by repository service 29 Aug '10

29 Aug '10

Author: stepan Date: Sun Aug 29 01:23:47 2010 New Revision: 5746 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5746 Log: fix compilation of hello.elf example payload. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/sample/Makefile Modified: trunk/payloads/libpayload/sample/Makefile ============================================================================== --- trunk/payloads/libpayload/sample/Makefile Fri Aug 27 11:36:41 2010 (r5745) +++ trunk/payloads/libpayload/sample/Makefile Sun Aug 29 01:23:47 2010 (r5746) @@ -28,10 +28,9 @@ ## # Sample libpayload Makefile. - -LIBPAYLOAD_DIR := .. -CC := $(LIBPAYLOAD_DIR)/bin/lpgcc -AS := $(LIBPAYLOAD_DIR)/bin/lpas +LIBPAYLOAD_DIR := ../install/libpayload +XCC := CC=$(CC) $(LIBPAYLOAD_DIR)/bin/lpgcc +XAS := AS=$(AS) $(LIBPAYLOAD_DIR)/bin/lpas CFLAGS := -Wall -Werror -Os TARGET := hello OBJS := $(TARGET).o @@ -39,13 +38,13 @@ all: $(TARGET).elf $(TARGET).elf: $(OBJS) - $(CC) -o $@ $(OBJS) + $(XCC) -o $@ $(OBJS) %.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< + $(XCC) $(CFLAGS) -c -o $@ $< %.S.o: %.S - $(AS) --32 -o $@ $< + $(XAS) --32 -o $@ $< clean: rm -f $(TARGET).elf *.o

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Re: [coreboot] Chipset VIA Apollo Pro+?
by anders＠jenbo.dk 28 Aug '10

28 Aug '10

I did some initial code for this chip set (debug is working) but haven't played with it for a while. Mvh Anders ----- Reply message ----- Fra: "Darmawan Salihun" <darmawan.salihun(a)gmail.com> Dato: lør., aug. 28, 2010 10:09 Emne: [coreboot] Chipset VIA Apollo Pro+? Til: "Mats Erik Andersson" <mats.andersson(a)gisladisker.se> Cc: <coreboot(a)coreboot.org> I have the datasheet of this chipset. I'll send it to you later. I was one working with legacy BIOS on moatherboard with this chipset. -Darmawan On 8/27/10, Mats Erik Andersson <mats.andersson(a)gisladisker.se> wrote: > Hello, > > is there now, or has there been, someone interested > in the legacy chipset VIA Apollo Pro+? In the sense > of investigating its use with Coreboot. > > The northbridge is VIA VT82C693, and the southbridge > is VIA VT82C596A on a mainboard from ECS: > > PCI-bridge VT82C691, > AGP-bridge VT82C598, > ISA-bridge VT82C596A, > IDE-interface VT82C571, > USB-controller VT82C572, and > Power-ctrl VT82C596. > > A search for datasheets has given nothing but trivial > information. > > > Regards, > > Mats Erik Andersson, fil. dr > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =- -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

1 0

Chipset VIA Apollo Pro+?
by Mats Erik Andersson 28 Aug '10

28 Aug '10

Hello, is there now, or has there been, someone interested in the legacy chipset VIA Apollo Pro+? In the sense of investigating its use with Coreboot. The northbridge is VIA VT82C693, and the southbridge is VIA VT82C596A on a mainboard from ECS: PCI-bridge VT82C691, AGP-bridge VT82C598, ISA-bridge VT82C596A, IDE-interface VT82C571, USB-controller VT82C572, and Power-ctrl VT82C596. A search for datasheets has given nothing but trivial information. Regards, Mats Erik Andersson, fil. dr

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undefined reference to `IS_PC_SLICE_TYPE_BSD'
by BeBa 27 Aug '10

27 Aug '10

HI, this is my first try at compiling filo. the latest versions downloaded with svn co. google shows one issue already reported. Is this something new? How to circumvent this barrier? thanks BenBa />make CC="gcc -m32" LD="ld -b elf32-i386" HOSTCC="gcc" AS="as --32" Found Libpayload /home/kb2qzv/subversion/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/ipchecksum.o CC build/main/grub/grub.o CC build/main/grub/builtins.o CC build/main/grub/cmdline.o CC build/main/grub/char_io.o CC build/main/grub/completions.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o CC build/fs/fsys_fat.o CC build/fs/fsys_reiserfs.o CC build/fs/fsys_iso9660.o CC build/fs/fsys_cbfs.o CC build/fs/cbfs.o CC build/fs/lzma.o CC build/drivers/ide.o CC build/drivers/usb.o CC build/drivers/intel.o LD build/filo /home/kb2qzv/subversion/coreboot/payloads/filo/build/main/grub/completions.o: In function `print_completions': completions.c:(.text+0x2f2): undefined reference to `IS_PC_SLICE_TYPE_BSD' make: *** [/home/kb2qzv/subversion/coreboot/payloads/filo/build/filo] Error 1

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coreboot August 2010