coreboot September 2009

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[PATCH] amd/pistachio and technexion/tim8960 devicetree.cb comments
by Carl-Daniel Hailfinger 22 Sep '09

22 Sep '09

r4534 introduced devicetree.cb in every mainboard directory, but didn't copy any comment lines before the start of the device tree. Fix up amd/pistachio and technexion/tim8960. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb (Revision 4614) +++ LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb (Arbeitskopie) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_AM2 Index: LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb (Revision 4614) +++ LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb (Arbeitskopie) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff80000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1 -- http://www.hailfinger.org/

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[v2] r4648 - in trunk/coreboot-v2/src/mainboard: amd/pistachio technexion/tim8690
by svn＠coreboot.org 22 Sep '09

22 Sep '09

Author: hailfinger Date: 2009-09-22 12:03:15 +0200 (Tue, 22 Sep 2009) New Revision: 4648 Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb Log: r4534 introduced devicetree.cb in every mainboard directory, but didn't copy any comment lines before the start of the device tree. Fix up amd/pistachio and technexion/tim8960. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-09-22 09:43:25 UTC (rev 4647) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-09-22 10:03:15 UTC (rev 4648) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_AM2 Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb 2009-09-22 09:43:25 UTC (rev 4647) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb 2009-09-22 10:03:15 UTC (rev 4648) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff80000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1

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[PATCH] Clean up PCI ops in AMD 690 boards
by Carl-Daniel Hailfinger 22 Sep '09

22 Sep '09

r4646 enabled early usage of pci_{read,write}_config{8,16,32} This allows us to change dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); to the much more readable dword = pci_read_config32(sm_dev, 0x64); Clean up all PCI operations in mainboards based on AMD 690. Boot tested on Asus M2A-VM which is a slightly modified AMD DBM690T. Build tested on all targets. (cbfstool hangs in an endless loop for the technexion board.) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c (Revision 4646) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/pistachio/mainboard.c (Arbeitskopie) @@ -83,7 +83,6 @@ u16 word; u32 dword; device_t sm_dev; - struct bus pbus; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -167,28 +166,19 @@ /* GPM5 as GPIO not USB OC */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - dword = - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x64); + dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 19; - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x64, dword); + pci_write_config32(sm_dev, 0x64, dword); /* Enable Client Management Index/Data registers */ - dword = - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x78); + dword = pci_read_config32(sm_dev, 0x78); dword |= 1 << 11; /* Cms_enable */ - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x78, dword); + pci_write_config32(sm_dev, 0x78, dword); /* MiscfuncEnable */ - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x41); + byte = pci_read_config8(sm_dev, 0x41); byte |= (1 << 5); - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x41, byte); + pci_write_config8(sm_dev, 0x41, byte); /* set GPM5 as input */ /* set index register 0C50h to 13h (miscellaneous control) */ @@ -228,12 +218,9 @@ pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Revision 4646) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c (Arbeitskopie) @@ -97,32 +97,24 @@ static void get_ide_dma66() { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - struct bus pbus; + struct device *sm_dev; + struct device *ide_dev; + printk_info("%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9); + byte = pci_read_config8(sm_dev, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9, byte); + pci_write_config8(sm_dev, 0xA9, byte); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, - 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56, byte); + pci_write_config8(ide_dev, 0x56, byte); } /* @@ -133,7 +125,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -156,12 +147,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/technexion/tim8690/mainboard.c (Revision 4646) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/technexion/tim8690/mainboard.c (Arbeitskopie) @@ -59,16 +59,15 @@ u8 byte; device_t sm_dev; - struct bus pbus; printk_info("enable_onboard_nic.\n"); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - byte= pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a); + byte = pci_read_config8(sm_dev, 0x9a); byte |= ( 1 << 7); - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a,byte); + pci_write_config8(sm_dev, 0x9a, byte); byte=pm_ioread(0x59); @@ -76,10 +75,10 @@ pm_iowrite(0x59,byte); - byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8); + byte = pci_read_config8(sm_dev, 0xA8); byte |= (1 << 1); //set bit 1 to high - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8, byte); + pci_write_config8(sm_dev, 0xA8, byte); } /* set thermal config @@ -89,7 +88,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -112,12 +110,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); -- http://www.hailfinger.org/

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[v2] r4647 - in trunk/coreboot-v2/src/mainboard: amd/dbm690t amd/pistachio technexion/tim8690
by svn＠coreboot.org 22 Sep '09

22 Sep '09

Author: hailfinger Date: 2009-09-22 11:43:25 +0200 (Tue, 22 Sep 2009) New Revision: 4647 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c Log: r4646 enabled early usage of pci_{read,write}_config{8,16,32} This allows us to change dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); to the much more readable dword = pci_read_config32(sm_dev, 0x64); Clean up all PCI operations in mainboards based on AMD 690: amd/pistachio amd/dbm690t technexion/tim8690 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-09-22 00:09:41 UTC (rev 4646) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2009-09-22 09:43:25 UTC (rev 4647) @@ -97,32 +97,24 @@ static void get_ide_dma66() { u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - struct bus pbus; + struct device *sm_dev; + struct device *ide_dev; + printk_info("%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9); + byte = pci_read_config8(sm_dev, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0xA9, byte); + pci_write_config8(sm_dev, 0xA9, byte); ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_cf8_conf1. - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, - 0xAA)) + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary, - ide_dev->path.pci.devfn, 0x56, byte); + pci_write_config8(ide_dev, 0x56, byte); } /* @@ -133,7 +125,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -156,12 +147,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-09-22 00:09:41 UTC (rev 4646) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/mainboard.c 2009-09-22 09:43:25 UTC (rev 4647) @@ -83,7 +83,6 @@ u16 word; u32 dword; device_t sm_dev; - struct bus pbus; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -167,28 +166,19 @@ /* GPM5 as GPIO not USB OC */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - dword = - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x64); + dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 19; - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x64, dword); + pci_write_config32(sm_dev, 0x64, dword); /* Enable Client Management Index/Data registers */ - dword = - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x78); + dword = pci_read_config32(sm_dev, 0x78); dword |= 1 << 11; /* Cms_enable */ - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x78, dword); + pci_write_config32(sm_dev, 0x78, dword); /* MiscfuncEnable */ - byte = - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x41); + byte = pci_read_config8(sm_dev, 0x41); byte |= (1 << 5); - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x41, byte); + pci_write_config8(sm_dev, 0x41, byte); /* set GPM5 as input */ /* set index register 0C50h to 13h (miscellaneous control) */ @@ -228,12 +218,9 @@ pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c 2009-09-22 00:09:41 UTC (rev 4646) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/mainboard.c 2009-09-22 09:43:25 UTC (rev 4647) @@ -59,16 +59,15 @@ u8 byte; device_t sm_dev; - struct bus pbus; printk_info("enable_onboard_nic.\n"); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - byte= pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a); + byte = pci_read_config8(sm_dev, 0x9a); byte |= ( 1 << 7); - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a,byte); + pci_write_config8(sm_dev, 0x9a, byte); byte=pm_ioread(0x59); @@ -76,10 +75,10 @@ pm_iowrite(0x59,byte); - byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8); + byte = pci_read_config8(sm_dev, 0xA8); byte |= (1 << 1); //set bit 1 to high - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8, byte); + pci_write_config8(sm_dev, 0xA8, byte); } /* set thermal config @@ -89,7 +88,6 @@ u8 byte; u16 word; device_t sm_dev; - struct bus pbus; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -112,12 +110,9 @@ /* set GPIO 64 to input */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56); + word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.pci.devfn, 0x56, word); + pci_write_config16(sm_dev, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0);

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Patchwork update script
by Carl-Daniel Hailfinger 22 Sep '09

22 Sep '09

Hi, here's the script I'm using to set the status of flashrom patches in patchwork to "Accepted". The web interface only allows you to set the status, but it does not allow you to set a commit ID. With pwclient (part of patchwork) you can do that. My script simply retrieves a patch (-p0) for a given numeric commit ID (without leading r), hashes it with the special patchwork hash (which is somewhat tolerant of context and order changes), then uses pwclient to set the patch status for that hash to "Accepted" and the commit ID to "r$1". If the patch (-p0) can't be found, it retrieves a patch (-p1) for the commit ID. Usage: update-patchwork 1234 You might want to adjust a few paths for coreboot usage and for your local installation. Requirements for this script: - A local patchwork source (or installation) - ~/.pwclientrc (downloaded from the patchwork web interface) Where can you get .pwclientrc? Go to http://patchwork.coreboot.org/project/ and log in. Then click on your preferred project, then click on "project info". There you find: "Sample patchwork client configuration for this project: .pwclientrc." Download .pwclientrc and fill in your patchwork password, then store it in your $HOME. I hope this helps others reduce patchwork maintenance efforts. Regards, Carl-Daniel #!/bin/bash # Install this script as update-patchwork in your $PATH # and call it with the revision number as parameter. test -z "$1" && { echo "No revision provided."; exit 1; } revision="$1" hashcand=$(svn diff -c $revision svn://coreboot.org/flashrom/trunk/|python /sources/tmptrees/patchwork/apps/patchwork/parser.py --hash) /sources/tmptrees/patchwork/apps/patchwork/bin/pwclient update -s Accepted -c r$revision -h $hashcand && { echo "done"; exit 0; } echo hashcand=$(svn diff -c $revision svn://coreboot.org/flashrom/|python /sources/tmptrees/patchwork/apps/patchwork/parser.py --hash) /sources/tmptrees/patchwork/apps/patchwork/bin/pwclient update -s Accepted -c r$revision -h $hashcand && { echo "done"; exit 0; } echo "No matching patch in patchwork found." exit 1 -- http://www.hailfinger.org/

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build service results for r4646
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4646 to the coreboot repository. This caused the following changes: Change Log: If no pci access method has been set for the device tree so far (e.g. during early coreboot_ram), pci_{read,write}_config{8,16,32} will die(). This patch changes pci_{read,write}_config{8,16,32} to use the existing PCI access method autodetection infrastructure instead of die()ing. Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of embeddedplanet:ep405pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4646&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4646&device=sandpointx3_al… Compilation of totalimpact:briq has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4646&device=briq&vendor=to… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] Auto-pick working PCI ops if none are set
by Carl-Daniel Hailfinger 22 Sep '09

22 Sep '09

Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); The advantage is obvious. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c (Arbeitskopie) @@ -25,6 +25,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +/* The only consumer of the return value of get_pbus() is ops_pci_bus(). + * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + */ static struct bus *get_pbus(device_t dev) { struct bus *pbus = NULL; @@ -44,8 +47,9 @@ pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { - printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev)); - die(""); + /* This can happen before the device tree is set up completely. */ + //printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev)); + pbus = NULL; } return pbus; } Index: LinuxBIOSv2-asus_m2a-vm/src/include/device/pci_ops.h =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/include/device/pci_ops.h (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/include/device/pci_ops.h (Arbeitskopie) @@ -21,4 +21,7 @@ void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val); #endif +/* This function lives in pci_ops_auto.c */ +const struct pci_bus_operations *pci_remember_direct(void); + #endif /* PCI_OPS_H */ Index: LinuxBIOSv2-asus_m2a-vm/src/include/device/pci.h =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/include/device/pci.h (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/include/device/pci.h (Arbeitskopie) @@ -97,6 +97,8 @@ if (bus && bus->dev && bus->dev->ops) { bops = bus->dev->ops->ops_pci_bus; } + if (!bops) + bops = pci_remember_direct(); return bops; } Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/pci_ops_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/pci_ops_auto.c (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/pci_ops_auto.c (Arbeitskopie) @@ -41,6 +41,8 @@ return 0; } +struct pci_bus_operations *pci_bus_fallback_ops = NULL; + const struct pci_bus_operations *pci_check_direct(void) { unsigned int tmp; @@ -81,11 +83,18 @@ return NULL; } +const struct pci_bus_operations *pci_remember_direct(void) +{ + if (!pci_bus_fallback_ops) + pci_bus_fallback_ops = pci_check_direct(); + return pci_bus_fallback_ops; +} + /** Set the method to be used for PCI, type I or type II */ void pci_set_method(device_t dev) { printk_info("Finding PCI configuration type.\n"); - dev->ops->ops_pci_bus = pci_check_direct(); + dev->ops->ops_pci_bus = pci_remember_direct(); post_code(0x5f); } -- http://www.hailfinger.org/

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[v2] r4646 - in trunk/coreboot-v2/src: arch/i386/lib devices include/device
by svn＠coreboot.org 22 Sep '09

22 Sep '09

Author: hailfinger Date: 2009-09-22 02:09:41 +0200 (Tue, 22 Sep 2009) New Revision: 4646 Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c trunk/coreboot-v2/src/devices/pci_ops.c trunk/coreboot-v2/src/include/device/pci.h trunk/coreboot-v2/src/include/device/pci_ops.h Log: If no pci access method has been set for the device tree so far (e.g. during early coreboot_ram), pci_{read,write}_config{8,16,32} will die(). This patch changes pci_{read,write}_config{8,16,32} to use the existing PCI access method autodetection infrastructure instead of die()ing. Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c 2009-09-17 18:30:23 UTC (rev 4645) +++ trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c 2009-09-22 00:09:41 UTC (rev 4646) @@ -41,6 +41,8 @@ return 0; } +struct pci_bus_operations *pci_bus_fallback_ops = NULL; + const struct pci_bus_operations *pci_check_direct(void) { unsigned int tmp; @@ -81,11 +83,18 @@ return NULL; } +const struct pci_bus_operations *pci_remember_direct(void) +{ + if (!pci_bus_fallback_ops) + pci_bus_fallback_ops = pci_check_direct(); + return pci_bus_fallback_ops; +} + /** Set the method to be used for PCI, type I or type II */ void pci_set_method(device_t dev) { printk_info("Finding PCI configuration type.\n"); - dev->ops->ops_pci_bus = pci_check_direct(); + dev->ops->ops_pci_bus = pci_remember_direct(); post_code(0x5f); } Modified: trunk/coreboot-v2/src/devices/pci_ops.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_ops.c 2009-09-17 18:30:23 UTC (rev 4645) +++ trunk/coreboot-v2/src/devices/pci_ops.c 2009-09-22 00:09:41 UTC (rev 4646) @@ -25,6 +25,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +/* The only consumer of the return value of get_pbus() is ops_pci_bus(). + * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + */ static struct bus *get_pbus(device_t dev) { struct bus *pbus = NULL; @@ -44,8 +47,9 @@ pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { - printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev)); - die(""); + /* This can happen before the device tree is set up completely. */ + //printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev)); + pbus = NULL; } return pbus; } Modified: trunk/coreboot-v2/src/include/device/pci.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci.h 2009-09-17 18:30:23 UTC (rev 4645) +++ trunk/coreboot-v2/src/include/device/pci.h 2009-09-22 00:09:41 UTC (rev 4646) @@ -97,6 +97,8 @@ if (bus && bus->dev && bus->dev->ops) { bops = bus->dev->ops->ops_pci_bus; } + if (!bops) + bops = pci_remember_direct(); return bops; } Modified: trunk/coreboot-v2/src/include/device/pci_ops.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci_ops.h 2009-09-17 18:30:23 UTC (rev 4645) +++ trunk/coreboot-v2/src/include/device/pci_ops.h 2009-09-22 00:09:41 UTC (rev 4646) @@ -21,4 +21,7 @@ void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val); #endif +/* This function lives in pci_ops_auto.c */ +const struct pci_bus_operations *pci_remember_direct(void); + #endif /* PCI_OPS_H */

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USB POST card
by Myles Watson 21 Sep '09

21 Sep '09

http://www.nowthatsit.nl/?c=447&i=8877 Has anyone used one of these? I'm wondering how well they work, if they could replace the serial port on a board that didn't have one, etc. You can find them for about $10 on ebay. Thanks, Myles

6 13

dell s1850 progress
by ron minnich 21 Sep '09

21 Sep '09

Well, we're getting serial out now. coreboot-2.0.0-r.0Fallback Fri Sep 18 16:51:15 PDT 2009 starting... PCI: 00:00.00 PCI: 00:10.00 PCI: 0f:00.00 PCI: 0f:10.00 SMBus controller enabled so we own it. There's a missing smbus controller, a few more bits to work out, but given that we support this chipset, I've only bricked 6 nodes, there are 4500 left to go, this ought to be doable. I can't wait to get rid of this factory bios. There is just so much it does wrong ... ron

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coreboot September 2009