coreboot September 2009

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build service results for r4656
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4656 to the coreboot repository. This caused the following changes: Change Log: failoverR.diff: Revert my failover change since Kconfig only supports fallback. kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4656&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4656&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4656&device=briq&vendor=to… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4655
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4655 to the coreboot repository. This caused the following changes: Change Log: tables.diff: Add Kconfig dialogues for ACPI, MP_TABLE, ... Kconfig_bools.diff: Change some more ints to bools, change some default values. xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB. smp.diff: set CONFIG_SMP based on MAX_CPUS. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4655&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4655&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4655&device=briq&vendor=to… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Kconfig patches
by Myles Watson 22 Sep '09

22 Sep '09

I'm still trying to update my Tyan boards so they don't get pruned. They're pretty close, there is still an issue with ACPI that I'm working on, but I'd like to start shrinking my patch stack. tables.diff: Add Kconfig dialogues for ACPI, MP_TABLE, ... Kconfig_bools.diff: Change some more ints to bools, change some default values. xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB so that the end of the ROM gets cached (speeds up booting immensely.) failoverR.diff: Revert my failover change from before since Kconfig only supports fallback. kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig. smp.diff: set CONFIG_SMP based on MAX_CPUS. I think maybe CONFIG_SMP should just die and test for CONFIG_MAX_CPUS. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4656 - in trunk/coreboot-v2: src/mainboard/tyan src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/southbridge/nvidia/ck804 targets/tyan/s2895
by svn＠coreboot.org 22 Sep '09

22 Sep '09

Author: myles Date: 2009-09-22 20:53:50 +0200 (Tue, 22 Sep 2009) New Revision: 4656 Added: trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/tyan/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2895/Config.lb Log: failoverR.diff: Revert my failover change since Kconfig only supports fallback. kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/tyan/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/mainboard/tyan/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -23,6 +23,9 @@ depends on VENDOR_TYAN source "src/mainboard/tyan/s1846/Kconfig" +source "src/mainboard/tyan/s2891/Kconfig" +source "src/mainboard/tyan/s2892/Kconfig" +source "src/mainboard/tyan/s2895/Kconfig" endchoice Copied: trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +## +## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +#driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc +crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +MAINBOARD_OPTIONS= -DCONFIG_AP_IN_SIPI_WAIT=0 + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/Makefile.s289x.inc ___________________________________________________________________ Added: svn:mergeinfo + Copied: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,142 @@ +config BOARD_TYAN_S2891 + bool "Tyan Thunder K8SRE S2891" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2891 + depends on BOARD_TYAN_S2891 + +config APIC_ID_OFFSET + hex + default 8 + depends on BOARD_TYAN_S2891 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2891 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2891 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2891 + +config MAINBOARD_PART_NUMBER + string + default "s2891" + depends on BOARD_TYAN_S2891 + +config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2891 + depends on BOARD_TYAN_S2891 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2891 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2891 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2891 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2891 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2891 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2891 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2891 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2891 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2891 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2891 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_TYAN_S2891 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2891 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2891 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_TYAN_S2891 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_TYAN_S2891 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2891 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2891 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_TYAN_S2891 + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default y + depends on BOARD_TYAN_S2891 + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Makefile.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Copied: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,142 @@ +config BOARD_TYAN_S2892 + bool "Tyan Thunder K8SE S2892" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2892 + depends on BOARD_TYAN_S2892 + +config APIC_ID_OFFSET + hex + default 8 + depends on BOARD_TYAN_S2892 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2892 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2892 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2892 + +config MAINBOARD_PART_NUMBER + string + default "s2892" + depends on BOARD_TYAN_S2892 + +config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2892 + depends on BOARD_TYAN_S2892 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2892 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2892 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2892 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2892 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2892 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2892 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2892 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2892 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2892 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2892 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_TYAN_S2892 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2892 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2892 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_TYAN_S2892 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_TYAN_S2892 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2892 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2892 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_TYAN_S2892 + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default y + depends on BOARD_TYAN_S2892 + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Added: trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Makefile.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,3 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc + +driver-y += ../../../drivers/i2c/adm1027/adm1027.o Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb 2009-09-22 18:53:50 UTC (rev 4656) @@ -29,25 +29,10 @@ end if CONFIG_USE_INIT -if CONFIG_USE_FAILOVER_IMAGE makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/failover.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/failover.c -o $@" - end -else - makerule ./auto.o depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end -end -else #CONFIG_USE_INIT -if CONFIG_USE_FAILOVER_IMAGE - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/failover.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/failover.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end else makerule ./auto.inc depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" @@ -56,32 +41,51 @@ action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -end #CONFIG_USE_INIT ## ## Build our 16 bit and 32 bit coreboot entry code ## -if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + end end mainboardinit cpu/x86/32bit/entry32.inc if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end ## ## Build our reset vector (This is where coreboot is entered) ## -if CONFIG_USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds + else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds + end else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds + else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds + end end ## @@ -93,9 +97,16 @@ ## ## ROMSTRAP table for CK804 ## -if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + mainboardinit southbridge/nvidia/ck804/romstrap.inc + ldscript /southbridge/nvidia/ck804/romstrap.lds + end end ## @@ -108,8 +119,14 @@ ### Things are delicate and we test to see if we should ### failover to another image. ### -if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE + ldscript /arch/i386/lib/failover_failover.lds + end +else + if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + end end ## Copied: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig (from rev 4611, trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig) =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1,142 @@ +config BOARD_TYAN_S2895 + bool "Tyan Thunder K8WE S2895" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_SMSC_LPC47B397 + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default tyan/s2895 + depends on BOARD_TYAN_S2895 + +config APIC_ID_OFFSET + hex + default 8 + depends on BOARD_TYAN_S2895 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2895 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2895 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2895 + +config MAINBOARD_PART_NUMBER + string + default "s2895" + depends on BOARD_TYAN_S2895 + +config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2895 + depends on BOARD_TYAN_S2895 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2895 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2895 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2895 + +config HAVE_FAILOVER_BOOT + bool + default n + depends on BOARD_TYAN_S2895 + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_TYAN_S2895 + +config MAX_CPUS + int + default 4 + depends on BOARD_TYAN_S2895 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_TYAN_S2895 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_TYAN_S2895 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2895 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2895 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_TYAN_S2895 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2895 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2895 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_TYAN_S2895 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_TYAN_S2895 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2895 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2895 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_TYAN_S2895 + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default y + depends on BOARD_TYAN_S2895 + Property changes on: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig ___________________________________________________________________ Added: svn:mergeinfo + Added: trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Makefile.inc 2009-09-22 18:53:50 UTC (rev 4656) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-09-22 18:53:50 UTC (rev 4656) @@ -1,3 +1,4 @@ +#define ASSEMBLY 1 #define __ROMCC__ #define K8_ALLOCATE_IO_RANGE 1 @@ -20,12 +21,11 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#define post_code(x) outb(x, 0x80) +#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -34,6 +34,8 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#endif + #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" @@ -42,6 +44,8 @@ #define SUPERIO_GPIO_IO_BASE 0x400 +#if CONFIG_USE_FAILOVER_IMAGE==0 + #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -114,8 +118,117 @@ #include "cpu/amd/model_fxx/init_cpus.c" +#endif + +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) + +#include "southbridge/nvidia/ck804/ck804_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +static void sio_setup(void) +{ + + unsigned value; + uint32_t dword; + uint8_t byte; + + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); + + byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); + + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); + + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); + +} + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + /* Setup the ck804 */ + ck804_enable_rom(); + + /* Is this a deliberate reset by the bios */ +// post_code(0x22); + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: +// post_code(0x23); + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ + ); + + fallback_image: +// post_code(0x25); +#if CONFIG_HAVE_FAILOVER_BOOT==1 + __asm__ volatile ("jmp __fallback_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ) +#endif + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 + failover_process(bist, cpu_init_detectedx); + #else + real_main(bist, cpu_init_detectedx); + #endif +#else + #if CONFIG_USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif + real_main(bist, cpu_init_detectedx); +#endif +} + +#if CONFIG_USE_FAILOVER_IMAGE==0 + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, @@ -135,7 +248,7 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } - post_code(0x32); +// post_code(0x32); lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -197,3 +310,4 @@ post_cache_as_ram(); } +#endif Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig 2009-09-22 18:53:50 UTC (rev 4656) @@ -1,3 +1,14 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool default n + +config HAVE_HARD_RESET + bool + default y + depends on SOUTHBRIDGE_NVIDIA_CK804 + +config IOAPIC + bool + default y + depends on SOUTHBRIDGE_NVIDIA_CK804 + Modified: trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-09-22 18:53:50 UTC (rev 4656) @@ -24,11 +24,4 @@ payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Modified: trunk/coreboot-v2/targets/tyan/s2895/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config.lb 2009-09-22 18:49:08 UTC (rev 4655) +++ trunk/coreboot-v2/targets/tyan/s2895/Config.lb 2009-09-22 18:53:50 UTC (rev 4656) @@ -7,80 +7,21 @@ # Tyan s2895 romimage "normal" -# 48K for SCSI FW -# option CONFIG_ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option CONFIG_ROM_SIZE = 425984 -# 64K for Etherboot -# option CONFIG_ROM_SIZE = 458752 -# 64K for NIC option 48K for Raid option rom -# option CONFIG_ROM_SIZE = 409600 option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 -# option CONFIG_ROM_IMAGE_SIZE=0x11800 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x15000 option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x17800 option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" -# payload ../../../payloads/tg3--ide_disk.zelf -# payload ../../../payloads/filo.elf -# payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo.zelf -# payload ../../../payloads/tg3.zelf -# payload ../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf -# payload ../../../payloads/forcedeth_vga.zelf -# payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf -# payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf -# payload ../../../../../../elf/ram0_2.5_2.6.12.tiny.elf -# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf -# payload ../../../payloads/tg3_vga.zelf -# payload ../../../payloads/tg3--filo_hda2_vgax.zelf -# payload ../../../payloads/tg3--filo_hda2_com2.zelf -# payload ../../../payloads/e1000--filo.zelf -# payload ../../../payloads/tg3--e1000--filo.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf payload ../payload.elf end romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 -# option CONFIG_ROM_IMAGE_SIZE=0x11800 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x15000 option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x17800 option CONFIG_XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" -# payload ../../../payloads/tg3--ide_disk.zelf -# payload ../../../payloads/filo.elf -# payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo.zelf -# payload ../../../payloads/tg3.zelf -# payload ../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf -# payload ../../../payloads/forcedeth_vga.zelf -# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf -# payload ../../../payloads/tg3_vga.zelf -# payload ../../../payloads/tg3--filo_hda2_vgax.zelf -# payload ../../../payloads/tg3--filo_hda2_com2.zelf -# payload ../../../payloads/e1000--filo.zelf -# payload ../../../payloads/tg3--e1000--filo.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf payload ../payload.elf end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" -end - - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

1 0

[v2] r4655 - in trunk/coreboot-v2/src: . console cpu cpu/x86 mainboard mainboard/amd/rumba mainboard/amd/serengeti_cheetah northbridge/intel/i82810
by svn＠coreboot.org 22 Sep '09

22 Sep '09

Author: myles Date: 2009-09-22 20:49:08 +0200 (Tue, 22 Sep 2009) New Revision: 4655 Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/cpu/Kconfig trunk/coreboot-v2/src/cpu/x86/Kconfig trunk/coreboot-v2/src/mainboard/Kconfig trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig Log: tables.diff: Add Kconfig dialogues for ACPI, MP_TABLE, ... Kconfig_bools.diff: Change some more ints to bools, change some default values. xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB. smp.diff: set CONFIG_SMP based on MAX_CPUS. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -40,14 +40,10 @@ bool default y -config HAVE_HIGH_TABLES +config PCI_BUS_SEGN_BITS bool - default y + default n -config PCI_BUS_SEGN_BITS - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0 @@ -81,20 +77,20 @@ default 126 config LOGICAL_CPUS - int - default 1 + bool + default y config PCI_ROM_RUN bool default n config HT_CHAIN_UNITID_BASE - int + hex default 1 config HT_CHAIN_END_UNITID_BASE - int - default 32 + hex + default 0x20 config HEAP_SIZE hex @@ -136,10 +132,6 @@ int default 2048 -config MULTIBOOT - bool - default n - config COMPRESSED_PAYLOAD_LZMA bool default y @@ -158,10 +150,6 @@ int default 0 -config HAVE_ACPI_TABLES - bool - default n - config HAVE_FALLBACK_BOOT bool default y @@ -186,18 +174,10 @@ bool default y -config HAVE_MP_TABLE - bool - default n - config HAVE_OPTION_TABLE bool default y -config HAVE_PIRQ_TABLE - bool - default n - config PIRQ_ROUTE bool default n @@ -214,11 +194,55 @@ bool default n +config USE_WATCHDOG_ON_BOOT + bool + default n + +config VGA + bool + default n + help + Build board-specific VGA code. + +config GFXUMA + bool + default n + help + Enable Unified Memory Architecture for graphics. + # TODO # menu "Drivers" # # endmenu +menu "Generated System Tables" + +config HAVE_LOW_TABLES + bool + default y + +config HAVE_HIGH_TABLES + bool "Write 'high' tables to avoid being overwritten in F segment" + default y + +config MULTIBOOT + bool "Add Multiboot tables (for grub2)" + default n + +config HAVE_ACPI_TABLES + bool "Generate ACPI tables" + default n + +config HAVE_MP_TABLE + bool "Generate an MP table" + default n + +config HAVE_PIRQ_TABLE + bool "Generate a PIRQ table" + default n + +endmenu + menu "Payload" config COMPRESSED_PAYLOAD_LZMA Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/console/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -32,6 +32,12 @@ bool "Use VGA console, once initialized." default n +config CONSOLE_VGA_ONBOARD_AT_FIRST + bool "Use onboard VGA as primary" + default n + help + If not selected, the last adapter found will be used. + config MAXIMUM_CONSOLE_LOGLEVEL int "Maximum console loglevel" default 9 Modified: trunk/coreboot-v2/src/cpu/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/cpu/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -19,7 +19,7 @@ config SMP bool - default n + default y if MAX_CPUS != 1 config CPU_SOCKET_TYPE hex Modified: trunk/coreboot-v2/src/cpu/x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -16,4 +16,4 @@ config XIP_ROM_SIZE hex - default 0x2000 + default 0x20000 Modified: trunk/coreboot-v2/src/mainboard/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/mainboard/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -331,6 +331,11 @@ default "Tyan" depends on VENDOR_TYAN +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x10f1 + depends on VENDOR_TYAN + config MAINBOARD_VENDOR string default "VIA" Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -52,6 +52,6 @@ depends on BOARD_AMD_RUMBA config USE_INIT - int - default 0 + bool + default n depends on BOARD_AMD_RUMBA Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -69,30 +69,24 @@ default "Serengeti-Cheetah" depends on BOARD_AMD_SERENGETI_CHEETAH - -config USE_FAILOVER_IMAGE - int - default 0 - depends on BOARD_AMD_SERENGETI_CHEETAH - config HW_MEM_HOLE_SIZEK hex default 0x100000 depends on BOARD_AMD_SERENGETI_CHEETAH config MEM_TRAIN_SEQ - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config HAVE_FAILOVER_BOOT - int - default 0 + bool + default n depends on BOARD_AMD_SERENGETI_CHEETAH config USE_FAILOVER_IMAGE - int - default 0 + bool + default n depends on BOARD_AMD_SERENGETI_CHEETAH config MAX_CPUS @@ -106,28 +100,28 @@ depends on BOARD_AMD_SERENGETI_CHEETAH config MEM_TRAIN_SEQ - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config AP_CODE_IN_CAR - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config HW_MEM_HOLE_SIZE_AUTO_INC - int - default 0 + bool + default n depends on BOARD_AMD_SERENGETI_CHEETAH config HT_CHAIN_END_UNITID_BASE - int + hex default 0x6 depends on BOARD_AMD_SERENGETI_CHEETAH config USE_INIT - int - default 0 + bool + default n depends on BOARD_AMD_SERENGETI_CHEETAH config SERIAL_CPU_INIT @@ -136,13 +130,13 @@ depends on BOARD_AMD_SERENGETI_CHEETAH config AP_CODE_IN_CAR - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config WAIT_BEFORE_CPUS_INIT - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config SB_HT_CHAIN_ON_BUS0 Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-09-22 15:58:19 UTC (rev 4654) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-09-22 18:49:08 UTC (rev 4655) @@ -18,11 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config HAVE_HIGH_TABLES - bool "Do we have high tables" - default y - config NORTHBRIDGE_INTEL_I82810 bool default n -

1 0

build service results for r4654
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4654 to the coreboot repository. This caused the following changes: Change Log: This separates the code for each command in cbfstool. For the good and for the bad: It brings a certain amount of code duplication (some of which can be cleaned up again, or get rid of by proper refactoring). On the other hand now there's a very simple code flow for each command, rather than for each operation. ie. adding a file to a cbfs means: - open the cbfs - add the file - close the cbfs rather than open the cbfs: - do this for add, remove, but not for create create a new lar - if we don't have an open one yet add a file: - if we didn't bail out before close the file: - if we didn't bail out before The short term benefit is that this fixes a problem where cbfstool was trying to add a file if you gave a non-existing command because it bailed out on known, not on unknown commands. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4654&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4654&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4654&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r4653
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4653 to the coreboot repository. This caused the following changes: Change Log: * guard all mallocs in cbfstool * fix an issue that could lead to cbfstool writing outside of its allocated memory Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4653&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4653&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4653&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r4652
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4652 to the coreboot repository. This caused the following changes: Change Log: .. make abuild Kconfig proof for the time being. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4652&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4652&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4652&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r4651
by coreboot information 22 Sep '09

22 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4651 to the coreboot repository. This caused the following changes: Change Log: back out some overzealous renames Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4651&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4651&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4651&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4654 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 22 Sep '09

22 Sep '09

Author: stepan Date: 2009-09-22 17:58:19 +0200 (Tue, 22 Sep 2009) New Revision: 4654 Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.c Log: This separates the code for each command in cbfstool. For the good and for the bad: It brings a certain amount of code duplication (some of which can be cleaned up again, or get rid of by proper refactoring). On the other hand now there's a very simple code flow for each command, rather than for each operation. ie. adding a file to a cbfs means: - open the cbfs - add the file - close the cbfs rather than open the cbfs: - do this for add, remove, but not for create create a new lar - if we don't have an open one yet add a file: - if we didn't bail out before close the file: - if we didn't bail out before The short term benefit is that this fixes a problem where cbfstool was trying to add a file if you gave a non-existing command because it bailed out on known, not on unknown commands. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/cbfstool.c 2009-09-22 15:55:01 UTC (rev 4653) +++ trunk/coreboot-v2/util/cbfstool/cbfstool.c 2009-09-22 15:58:19 UTC (rev 4654) @@ -23,50 +23,79 @@ #include "common.h" #include "cbfs.h" -int main(int argc, char **argv) +typedef enum { + CMD_ADD, + CMD_ADD_PAYLOAD, + CMD_ADD_STAGE, + CMD_CREATE, + CMD_PRINT +} cmd_t; + +struct command { + cmd_t id; + const char *name; + int (*function) (int argc, char **argv); +}; + +static int cbfs_add(int argc, char **argv) { - if (argc < 3) { - printf - ("cbfstool: Management utility for CBFS formatted ROM images\n" - "USAGE:\n" "cbfstool [-h]\n" - "cbfstool FILE COMMAND [PARAMETERS]...\n\n" "OPTIONs:\n" - " -h Display this help message\n\n" - "COMMANDs:\n" - "add FILE NAME TYPE [base address] Add a component\n" - "add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" - "add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" - "create SIZE BSIZE BOOTBLOCK [ALIGN] Create a ROM file\n" - "print Show the contents of the ROM\n"); - return 1; - } char *romname = argv[1]; char *cmd = argv[2]; + void *rom = loadrom(romname); - if (strcmp(cmd, "create") == 0) { - if (argc < 6) { - printf("not enough arguments to 'create'.\n"); - return 1; - } - uint32_t size = strtoul(argv[3], NULL, 0); - /* ignore bootblock size. we use whatever we get and won't allocate any larger */ - char *bootblock = argv[5]; - uint32_t align = 0; - if (argc > 6) - align = strtoul(argv[6], NULL, 0); - return create_cbfs_image(romname, size, bootblock, align); + if (rom == NULL) { + printf("Could not load ROM image '%s'.\n", romname); + return 1; } + if (argc < 5) { + printf("not enough arguments to '%s'.\n", cmd); + return 1; + } + + char *filename = argv[3]; + char *cbfsname = argv[4]; + + uint32_t filesize = 0; + void *filedata = loadfile(filename, &filesize, 0, SEEK_SET); + if (filedata == NULL) { + printf("Could not load file '%s'.\n", filename); + return 1; + } + + uint32_t base = 0; + void *cbfsfile = NULL; + + if (argc < 6) { + printf("not enough arguments to 'add'.\n"); + return 1; + } + uint32_t type; + if (intfiletype(argv[5]) != ((uint64_t) - 1)) + type = intfiletype(argv[5]); + else + type = strtoul(argv[5], NULL, 0); + if (argc > 6) { + base = strtoul(argv[6], NULL, 0); + } + cbfsfile = + create_cbfs_file(cbfsname, filedata, &filesize, type, &base); + add_file_to_cbfs(cbfsfile, filesize, base); + writerom(romname, rom, romsize); + return 0; +} + +static int cbfs_add_payload(int argc, char **argv) +{ + char *romname = argv[1]; + char *cmd = argv[2]; void *rom = loadrom(romname); + if (rom == NULL) { printf("Could not load ROM image '%s'.\n", romname); return 1; } - if (strcmp(cmd, "print") == 0) { - print_cbfs_directory(romname); - return 0; - } - if (argc < 5) { printf("not enough arguments to '%s'.\n", cmd); return 1; @@ -83,59 +112,150 @@ } uint32_t base = 0; - void *cbfsfile; + void *cbfsfile = NULL; - if (strcmp(cmd, "add") == 0) { - if (argc < 6) { - printf("not enough arguments to 'add'.\n"); - return 1; - } - uint32_t type; - if (intfiletype(argv[5]) != ((uint64_t) - 1)) - type = intfiletype(argv[5]); - else - type = strtoul(argv[5], NULL, 0); - if (argc > 6) { - base = strtoul(argv[6], NULL, 0); - } - cbfsfile = - create_cbfs_file(cbfsname, filedata, &filesize, type, - &base); + comp_algo algo = CBFS_COMPRESS_NONE; + if (argc > 5) { + if (argv[5][0] == 'l') + algo = CBFS_COMPRESS_LZMA; } + if (argc > 6) { + base = strtoul(argv[6], NULL, 0); + } + unsigned char *payload; + filesize = parse_elf_to_payload(filedata, &payload, algo); + cbfsfile = + create_cbfs_file(cbfsname, payload, &filesize, + CBFS_COMPONENT_PAYLOAD, &base); + add_file_to_cbfs(cbfsfile, filesize, base); + writerom(romname, rom, romsize); + return 0; +} - if (strcmp(cmd, "add-payload") == 0) { - comp_algo algo = CBFS_COMPRESS_NONE; - if (argc > 5) { - if (argv[5][0] == 'l') - algo = CBFS_COMPRESS_LZMA; - } - if (argc > 6) { - base = strtoul(argv[6], NULL, 0); - } - unsigned char *payload; - filesize = parse_elf_to_payload(filedata, &payload, algo); - cbfsfile = - create_cbfs_file(cbfsname, payload, &filesize, - CBFS_COMPONENT_PAYLOAD, &base); +static int cbfs_add_stage(int argc, char **argv) +{ + char *romname = argv[1]; + char *cmd = argv[2]; + void *rom = loadrom(romname); + + if (rom == NULL) { + printf("Could not load ROM image '%s'.\n", romname); + return 1; } - if (strcmp(cmd, "add-stage") == 0) { - comp_algo algo = CBFS_COMPRESS_NONE; - if (argc > 5) { - if (argv[5][0] == 'l') - algo = CBFS_COMPRESS_LZMA; - } - if (argc > 6) { - base = strtoul(argv[6], NULL, 0); - } - unsigned char *stage; - filesize = parse_elf_to_stage(filedata, &stage, algo, &base); - cbfsfile = - create_cbfs_file(cbfsname, stage, &filesize, - CBFS_COMPONENT_STAGE, &base); + if (argc < 5) { + printf("not enough arguments to '%s'.\n", cmd); + return 1; } + char *filename = argv[3]; + char *cbfsname = argv[4]; + + uint32_t filesize = 0; + void *filedata = loadfile(filename, &filesize, 0, SEEK_SET); + if (filedata == NULL) { + printf("Could not load file '%s'.\n", filename); + return 1; + } + + uint32_t base = 0; + void *cbfsfile = NULL; + + comp_algo algo = CBFS_COMPRESS_NONE; + if (argc > 5) { + if (argv[5][0] == 'l') + algo = CBFS_COMPRESS_LZMA; + } + if (argc > 6) { + base = strtoul(argv[6], NULL, 0); + } + unsigned char *stage; + filesize = parse_elf_to_stage(filedata, &stage, algo, &base); + cbfsfile = + create_cbfs_file(cbfsname, stage, &filesize, + CBFS_COMPONENT_STAGE, &base); + add_file_to_cbfs(cbfsfile, filesize, base); writerom(romname, rom, romsize); return 0; } + +static int cbfs_create(int argc, char **argv) +{ + char *romname = argv[1]; + char *cmd = argv[2]; + if (argc < 6) { + printf("not enough arguments to 'create'.\n"); + return 1; + } + + uint32_t size = strtoul(argv[3], NULL, 0); + /* ignore bootblock size. we use whatever we get and won't allocate any larger */ + char *bootblock = argv[5]; + uint32_t align = 0; + + if (argc > 6) + align = strtoul(argv[6], NULL, 0); + + return create_cbfs_image(romname, size, bootblock, align); +} + +static int cbfs_print(int argc, char **argv) +{ + char *romname = argv[1]; + char *cmd = argv[2]; + void *rom = loadrom(romname); + + if (rom == NULL) { + printf("Could not load ROM image '%s'.\n", romname); + return 1; + } + + print_cbfs_directory(romname); + return 0; +} + +struct command commands[] = { + {CMD_ADD, "add", cbfs_add}, + {CMD_ADD_PAYLOAD, "add-payload", cbfs_add_payload}, + {CMD_ADD_STAGE, "add-stage", cbfs_add_stage}, + {CMD_CREATE, "create", cbfs_create}, + {CMD_PRINT, "print", cbfs_print} +}; + +void usage(void) +{ + printf + ("cbfstool: Management utility for CBFS formatted ROM images\n" + "USAGE:\n" "cbfstool [-h]\n" + "cbfstool FILE COMMAND [PARAMETERS]...\n\n" "OPTIONs:\n" + " -h Display this help message\n\n" + "COMMANDs:\n" + "add FILE NAME TYPE [base address] Add a component\n" + "add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" + "add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" + "create SIZE BSIZE BOOTBLOCK [ALIGN] Create a ROM file\n" + "print Show the contents of the ROM\n"); +} + +int main(int argc, char **argv) +{ + int i; + + if (argc < 3) { + usage(); + return 1; + } + + char *cmd = argv[2]; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name) != 0) + continue; + return commands[i].function(argc, argv); + } + + printf("Unknown command '%s'.\n", cmd); + usage(); + return 1; +}

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coreboot September 2009