coreboot August 2009

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build service results for r4531
by coreboot information 11 Aug '09

11 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4531 to the coreboot repository. This caused the following changes: Change Log: Enable CBFS everywhere. All boards compiled for me (abuild tested), and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=atc-6220&vendo… Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=be6-ii_v2_0&ve… Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b&vendor=asu… Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b-d&vendor=a… Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b-ds&vendor=… Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p2b-f&vendor=a… Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=pt-6ibd&vendor… Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=deskpro_en_sff… Compilation of embeddedplanet:ep405pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ep405pc&vendor… Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ga-6bxc&vendor… Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=nova4899r&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=sandpointx3_al… Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ms6119&vendor=… Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=ms6147&vendor=… Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=sy-6ba-plus-ii… Compilation of totalimpact:briq has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=briq&vendor=to… Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=s1846&vendor=t… Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531&device=epia-m&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Problem to build the rom image
by bz 11 Aug '09

11 Aug '09

Hello, I just tried to build coreboot.rom for an Axus TC 320 as described in the Build tutorial. ./buildtarget axus/tc320 until here everything works fine. LANG=C make The job stop with the following messages. objdump -dS coreboot > coreboot.disasm objcopy --gap-fill 0xff -O binary coreboot coreboot.strip make[1]: *** No rule to make target `../../../../../../../images/etherboot.elf', needed by `payload'. Stop. make[1]: Leaving directory `/home/bz/neu/coreboot-v2/targets/axus/tc320/tc320/normal' make: *** [normal/coreboot.rom] Error 2 What am i doing wrong? Can anyone help me? I try to do that with different revisions of Coreboot-V2

3 2

[v2] r4531 - in trunk/coreboot-v2: src/config src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61 src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp src/mainboar
by svn＠coreboot.org 11 Aug '09

11 Aug '09

Author: oxygene Date: 2009-08-11 19:35:02 +0200 (Tue, 11 Aug 2009) New Revision: 4531 Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb trunk/coreboot-v2/src/mainboard/via/epia/Options.lb trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb trunk/coreboot-v2/targets/amd/db800/Config.lb trunk/coreboot-v2/targets/amd/norwich/Config.lb trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb Log: Enable CBFS everywhere. All boards compiled for me (abuild tested), and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/config/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -693,7 +693,7 @@ comment "Enable FAT filesystem support" end define CONFIG_CBFS - default 0 + default 1 export always comment "The new CBFS file system" end Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,7 +78,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -102,5 +102,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -106,9 +106,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -305,5 +305,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -106,9 +106,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -305,5 +305,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -164,5 +164,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -105,12 +105,8 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 -#FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 -#FAILOVER: 4K +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl @@ -239,7 +235,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -333,5 +329,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -130,11 +130,9 @@ ## #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 1024K - 8K -default CONFIG_FALLBACK_SIZE=0xFE000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8k default CONFIG_FAILOVER_SIZE=0x02000 @@ -368,5 +366,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -76,7 +76,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -246,5 +246,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -166,5 +166,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -100,8 +100,8 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 252 * 1024 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE = 4 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_HAVE_FAILOVER_BOOT = 1 @@ -171,5 +171,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -95,7 +95,7 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_HAVE_PIRQ_TABLE = 0 @@ -171,5 +171,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -173,9 +173,12 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" + +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 # # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -162,5 +162,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,7 +78,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -102,5 +102,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -81,7 +81,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -103,5 +103,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -81,7 +81,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -108,5 +108,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_PIRQ_ROUTE = 1 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -87,7 +87,7 @@ default CONFIG_PIRQ_ROUTE = 1 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -107,5 +107,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -84,7 +84,7 @@ default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -108,5 +108,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -81,9 +81,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -266,5 +264,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -130,7 +130,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 ## ## Use a small 8K stack @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -119,5 +119,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -1,5 +1,4 @@ default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = 0x10000 ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 32 * 1024 Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -93,7 +93,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -127,5 +127,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -185,5 +185,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -91,7 +91,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -169,5 +169,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -148,5 +148,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -131,11 +131,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -132,11 +132,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -270,7 +268,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -365,6 +363,6 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 ### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -65,7 +65,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -225,5 +225,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -67,7 +67,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -231,5 +231,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -3,8 +3,6 @@ ## (coreboot plus bootloader) will live in the boot rom chip. ## default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_SIZE -default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -150,5 +150,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -98,7 +98,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -177,5 +177,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ default CONFIG_PIRQ_ROUTE = 1 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_DCACHE_RAM = 1 default CONFIG_DCACHE_RAM_BASE = 0xc8000 default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 @@ -111,5 +111,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -161,7 +161,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -246,5 +246,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -18,7 +18,7 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -150,7 +150,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM @@ -229,5 +229,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -18,7 +18,7 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -150,7 +150,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM @@ -231,5 +231,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -1,5 +1,5 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb arch i386 end Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -79,7 +79,7 @@ ## Build code for the fallback boot? ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## Delay timer options @@ -244,5 +244,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -105,11 +105,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-8K -default CONFIG_FALLBACK_SIZE=0x3e000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8K default CONFIG_FAILOVER_SIZE=0x02000 @@ -238,7 +236,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -332,5 +330,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -66,7 +66,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -66,7 +66,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -231,5 +231,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -109,5 +109,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -164,5 +164,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,7 +129,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -215,5 +215,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,7 +129,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -215,5 +215,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -75,10 +75,10 @@ # ROM layout default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 # RAM layout default CONFIG_RAMBASE = 0x00004000 Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -130,5 +130,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -125,5 +125,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -101,5 +101,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -112,7 +112,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=(252*1024) +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=(4*1024) @@ -228,8 +228,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = (64*1024) -#65536 +default CONFIG_ROM_IMAGE_SIZE = (64*1024) - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -325,5 +324,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = (256 * 1024) - (4 * 1024) +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE = 4 * 1024 default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 @@ -169,7 +169,7 @@ default CONFIG_MAINBOARD_VENDOR = "MSI" default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x7260 -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE default CONFIG_STACK_SIZE = 0x2000 default CONFIG_HEAP_SIZE = 0x8000 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) @@ -190,5 +190,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -118,10 +118,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -334,5 +331,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -112,9 +112,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -313,5 +311,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,7 +74,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -100,5 +100,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -73,9 +73,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -249,5 +247,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,11 +129,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -259,7 +257,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -355,5 +353,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -89,7 +89,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -165,5 +165,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -89,7 +89,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -165,5 +165,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -119,7 +119,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## enable CACHE_AS_RAM specifics @@ -203,5 +203,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -68,7 +68,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_FALLBACK_SIZE = 512 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 @@ -100,5 +100,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -77,7 +77,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -96,5 +96,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -82,9 +82,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -282,5 +280,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -133,11 +133,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Set all of the defaults for an x86 architecture Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -233,5 +233,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -4,7 +4,7 @@ default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/nofailovercalculation.lb ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -147,7 +147,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Coreboot C code runs at this location in RAM @@ -232,5 +232,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -106,9 +106,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -108,7 +108,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -140,5 +140,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,7 +88,7 @@ default CONFIG_IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_USE_OPTION_TABLE = 0 @@ -108,5 +108,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -68,7 +68,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_FALLBACK_SIZE = 256 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 @@ -100,5 +100,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -132,5 +132,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,7 +78,7 @@ default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = 128 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 default CONFIG_HAVE_OPTION_TABLE = 0 @@ -102,5 +102,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -76,7 +76,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default CONFIG_FALLBACK_SIZE=131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -260,5 +260,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -250,5 +248,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## @@ -251,5 +249,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -250,5 +248,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -79,9 +79,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -267,5 +265,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,9 +74,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -250,5 +248,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,9 +85,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -277,5 +275,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -88,9 +88,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -306,5 +304,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -82,9 +82,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ### ### Build options @@ -294,5 +292,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -91,11 +91,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -218,7 +216,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -313,5 +311,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -129,11 +129,9 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 256K-4K -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K default CONFIG_FAILOVER_SIZE=0x01000 @@ -261,7 +259,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -357,5 +355,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -20,7 +20,7 @@ ## ## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 +default CONFIG_XIP_ROM_SIZE = 128 * 1024 include /config/failovercalculation.lb arch i386 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -133,10 +133,8 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#default CONFIG_FALLBACK_SIZE=0x40000 -default CONFIG_FALLBACK_SIZE=0x3f000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl @@ -270,7 +268,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE ## ## Use a small 8K stack @@ -366,5 +364,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,9 +78,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -259,5 +257,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -78,9 +78,7 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE=131072 -#256K -default CONFIG_FALLBACK_SIZE=0x40000 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot @@ -258,5 +256,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -111,7 +111,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -146,5 +146,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -85,7 +85,7 @@ default CONFIG_HAVE_ACPI_TABLES = 0 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -109,5 +109,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -101,7 +101,7 @@ ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = 131072 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack @@ -148,5 +148,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -124,7 +124,7 @@ default CONFIG_HAVE_ACPI_TABLES = 1 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 16 * 1024 default CONFIG_HEAP_SIZE = 20 * 1024 @@ -137,7 +137,7 @@ default HOSTCC = "gcc" default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CBFS = 0 +default CONFIG_CBFS=1 ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -98,7 +98,7 @@ #default CONFIG_PAYLOAD_SIZE = 125 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 default CONFIG_PAYLOAD_SIZE = 256 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE + CONFIG_PAYLOAD_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 16 * 1024 @@ -123,5 +123,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -74,7 +74,7 @@ default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 default CONFIG_CONSOLE_SERIAL8250 = 1 @@ -117,5 +117,5 @@ # CBFS # # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/targets/amd/db800/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/db800/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/db800/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -32,7 +32,6 @@ # Leave 36k for VSA. option CONFIG_ROM_SIZE=512*1024-36*1024 # option CONFIG_ROM_SIZE=256*1024-36*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 Modified: trunk/coreboot-v2/targets/amd/norwich/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/norwich/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/norwich/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -32,7 +32,6 @@ option CONFIG_ROM_SIZE=512*1024-36*1024 #option CONFIG_ROM_SIZE=256*1024-36*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 Modified: trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb =================================================================== --- trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/rumba/Config.nofallback.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -5,8 +5,6 @@ mainboard amd/rumba option CONFIG_ROM_SIZE=128*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE -#option CONFIG_FALLBACK_SIZE=65535 #romimage "normal" # option CONFIG_USE_FALLBACK_IMAGE=0 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah/Config-lab.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "fallback" option CONFIG_PRECOMPRESSED_PAYLOAD=1 option CONFIG_COMPRESSED_PAYLOAD_LZMA=1 - option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x1a000 option CONFIG_XIP_ROM_SIZE=0x40000 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-lab.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -31,7 +31,6 @@ # 1024KB ROM option CONFIG_ROM_SIZE=1024*1024 -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE-CONFIG_FAILOVER_SIZE romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 Modified: trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ uses CONFIG_ROM_PAYLOAD_START uses CONFIG_UDELAY_TSC uses CPU_FIXUP -uses CONFIG_FALLBACK_SIZE uses CONFIG_HAVE_FALLBACK_BOOT uses CONFIG_HAVE_MP_TABLE uses CONFIG_HAVE_PIRQ_TABLE @@ -71,12 +70,6 @@ option CONFIG_ROM_PAYLOAD=1 option CONFIG_HAVE_FALLBACK_BOOT=1 -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE - ## Coreboot C code runs at this location in RAM option CONFIG_RAMBASE=0x00004000 Modified: trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb =================================================================== --- trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/artecgroup/dbe61/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -21,8 +21,6 @@ ## not including any payload. option CONFIG_ROM_IMAGE_SIZE=64*1024 -option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE - option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 romimage "fallback" Modified: trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asi/mb_5blmp/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -23,7 +23,6 @@ option CONFIG_ROM_SIZE = (256 * 1024) # option CONFIG_ROM_SIZE = (256 * 1024) - (32 * 1024) -# option CONFIG_FALLBACK_SIZE = (256 * 1024) - (32 * 1024) romimage "normal" option CONFIG_USE_FALLBACK_IMAGE = 0 Modified: trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asus/a8n_e/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -35,15 +35,6 @@ ## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, ## not including any payload. -# Please note that 128KB is cached for (XIP) too - -option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 - -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image -## (including payload) will use. - -option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE - romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 payload __PAYLOAD__ Modified: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -41,11 +41,6 @@ option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image -## (including payload) will use. - -option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE - romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 payload ../payload.elf Modified: trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/digitallogic/msm586seg/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -9,9 +9,7 @@ __LOGLEVEL__ romimage "fallback" - option CONFIG_FALLBACK_SIZE = 256 * 1024 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE= 128 * 1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -34,8 +34,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x28000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end @@ -43,8 +41,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/iei/juki-511p/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -9,22 +9,15 @@ __LOGLEVEL__ option CONFIG_ROM_SIZE=256*1024 -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -option CONFIG_FALLBACK_SIZE=128*1024 romimage "normal" option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/msi/ms7135/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/msi/ms7260/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -31,8 +31,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE = 0 option CONFIG_USE_FALLBACK_IMAGE = 0 - option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 - option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Normal" payload __PAYLOAD__ end @@ -40,8 +38,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE = 0 option CONFIG_USE_FALLBACK_IMAGE = 1 - option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 - option CONFIG_XIP_ROM_SIZE = 256 * 1024 option COREBOOT_EXTRA_VERSION = ".0Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/technologic/ts5300/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -9,9 +9,7 @@ __LOGLEVEL__ romimage "fallback" - option CONFIG_FALLBACK_SIZE = 256 * 1024 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=128 * 1024 # 0x10000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/tyan/s2895/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/tyan/s2912/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -13,7 +13,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -21,7 +20,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb 2009-08-11 17:32:26 UTC (rev 4530) +++ trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb 2009-08-11 17:35:02 UTC (rev 4531) @@ -31,8 +31,6 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x34000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end @@ -40,8 +38,6 @@ romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x34000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end

1 0

[v2] r4530 - trunk/coreboot-v2/src/cpu/amd/model_lx
by svn＠coreboot.org 11 Aug '09

11 Aug '09

Author: oxygene Date: 2009-08-11 19:32:26 +0200 (Tue, 11 Aug 2009) New Revision: 4530 Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc Log: cpu/amd/model_lx used its own routine for copying coreboot_ram. This change makes it use the generic infrastructure. NOTE: If you're bisecting issues on geode-lx circa jumping to coreboot_ram, this change has a high probability to break that place - so look into it. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2009-08-11 15:56:18 UTC (rev 4529) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2009-08-11 17:32:26 UTC (rev 4530) @@ -217,107 +217,25 @@ * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ -#if !CONFIG_COMPRESS + movl %ebp, %esi + /* FIXME: look for a proper place for the stack */ + movl $0x4000000, %esp + movl %esp, %ebp + pushl %esi +#if CONFIG_CBFS == 1 + pushl $str_coreboot_ram_name + call cbfs_and_run_core +#else movl $_liseg, %esi movl $_iseg, %edi movl $_eiseg, %ecx subl %edi, %ecx - movb %cl, %al - shrl $2, %ecx - andb $3, %al - rep movsl - movb %al, %cl - rep movsb -#else - leal 4+_liseg, %esi - leal _iseg, %edi - movl %ebp, %esp /* preserve %ebp */ - movl $-1, %ebp /* last_m_off = -1 */ - jmp dcl1_n2b - -/* ------------- DECOMPRESSION ------------- - - Input: - %esi - source - %edi - dest - %ebp - -1 - cld - - Output: - %eax - 0 - %ecx - 0 -*/ - -.macro getbit bits -.if \bits == 1 - addl %ebx, %ebx - jnz 1f -.endif - movl (%esi), %ebx - subl $-4, %esi /* sets carry flag */ - adcl %ebx, %ebx -1: -.endm - -decompr_literals_n2b: - movsb - -decompr_loop_n2b: - addl %ebx, %ebx - jnz dcl2_n2b -dcl1_n2b: - getbit 32 -dcl2_n2b: - jc decompr_literals_n2b - xorl %eax, %eax - incl %eax /* m_off = 1 */ -loop1_n2b: - getbit 1 - adcl %eax, %eax /* m_off = m_off*2 + getbit() */ - getbit 1 - jnc loop1_n2b /* while(!getbit()) */ - xorl %ecx, %ecx - subl $3, %eax - jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */ - shll $8, %eax - movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */ - incl %esi - xorl $-1, %eax - jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */ - movl %eax, %ebp /* last_m_off = m_off ?*/ -decompr_ebpeax_n2b: - getbit 1 - adcl %ecx, %ecx /* m_len = getbit() */ - getbit 1 - adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */ - jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */ - incl %ecx /* m_len++ */ -loop2_n2b: - getbit 1 - adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */ - getbit 1 - jnc loop2_n2b /* while(!getbit()) */ - incl %ecx - incl %ecx /* m_len += 2 */ -decompr_got_mlen_n2b: - cmpl $-0xd00, %ebp - adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */ - movl %esi, %edx - leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */ - rep - movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */ - movl %edx, %esi - jmp decompr_loop_n2b -decompr_end_n2b: - intel_chip_post_macro(0x12) /* post 12 */ - - movl %esp, %ebp + pushl %ecx + pushl %edi + pushl %esi + call copy_and_run_core #endif - CONSOLE_DEBUG_TX_STRING($str_pre_main) - leal _iseg, %edi - jmp *%edi - .Lhlt: intel_chip_post_macro(0xee) /* post fail ee */ hlt @@ -377,3 +295,10 @@ .previous #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ +#if CONFIG_CBFS == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 +str_coreboot_ram_name: .string "fallback/coreboot_ram" +# else +str_coreboot_ram_name: .string "normal/coreboot_ram" +# endif +#endif

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Re: [coreboot] ASUS KFN4D16 - K8 FAM10
by Myles Watson 11 Aug '09

11 Aug '09

> 1. > I can report that flashrom v0.9.0-r670 works with KFN4-D16 > I flashed an ASUS ROM (3.02) and halted the computer and rebooted, > computer booted up as normal. > > Should I formally inform someone so that the documentation can be updated > to reflect the fact that flashwom works with this board? If no one picks it up from this mail, you can send an email to the flashrom list and they'll update it. > 2. > I am struggling to configure coreboot for this board based on Myles > Watson's recommendation of using the tyans2892 as a template. > 2.1 > in acpi_tables.c resourcemap.c mptable.c dsdt.dsl there are references to > AMD8131, this board does not have an AMD8131, should I remove these > references? Yes. > > 2.2 in Options.lb > default CONFIG_MAINBOARD_PART_NUMBER="s2892" > default CONFIG_MAINBOARD_VENDOR="Tyan" > default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 > default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892 > Do I need to edit? Yes. It won't matter much at first, but you'll want those correct. > 2.3 > in dsdt.dsl there are references to onboard ATI RAGE, this board has an > ES1000 > and to an INTELL NIC, this board has broadcom You'll need to change those as well. > > 2.4 > > in Config.lb > 2.4.1 there are references to 8 DIMMS, this board has 16 > should I add 8 more from 58 to 65? > chip drivers/generic/generic #dimm 1-1-1 > device i2c 57 on end > end I don't know enough about this. > 2.4.2 > the SMBUS has ADT7463A and WINBOND monitors, do I need to edit this to > reflect the KFN4-DE16?, How do I find out what the KFN4-D16 has > 2.4.3 > Do I just remove the references to AMD8131? Do I replace with anything? Only if the board has something there. Many boards only have one HT link used, which simplifies things. > 2.4.4 > Do I need to add info about the PCI-E to PCI bridge and the ATI ES1000 > VGA? > 02:00.0 PCI bridge: Intel Corporation 6702PXH PCI Express-to-PCI Bridge A > (rev 09) > 04:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 > Gigabit Ethernet PCI Express (rev 21) > 05:00.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5721 > Gigabit Ethernet PCI Express (rev 21) > 06:05.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) You only need to add devices that: 1. Won't be found otherwise 2. Need some specific initialization 3. Are soldered to the mainboard Everything else will be found and initialized automatically. Good luck, Myles

2 2

mkelfimage with CBFS?
by Cristi Magherusan 11 Aug '09

11 Aug '09

Hello, First of all, I'd like to know if mkelfimage is still needed when using CBFS and LAB payloads, and what would be its purpose once the kernel can already be compiled as an ELF vmlinux binary with initramfs included, using for example buildroot and the kernel buildsystem's features. Does it have anything to do with the multiboot specification, or why does coreboot need the ELF to be modified using the mkelfImage tool? Thanks, Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

3 6

Tyan S2912[Fam10] HTX problem
by Maximilian Thuermer 11 Aug '09

11 Aug '09

Hi all, I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. I am not familiar with the PCI subsystem and the procedures of coreboot regarding this matter, but when scanning through the code, I do not even see why the last line is printed out twice whereas the procedure including the printout only gets called once with the specified parameters. Does anyone have an idea where I could start searching for a possible solution to my problem. Thanks for the help in advance, Maximilian Thuermer coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 reexx other core - nodeid: 01 cores: cco0coorr3e -: x::s t: a r- ----t--e-d - { { a { p A A aPPApIIPCiCIIcICiDDI d D =:= = F000o12 u 3 NnNONdODO DDE3EIEI IDDD w = =or =x : 0rroo2o1---mm--Pm-i -ii-cc cs- trr{{r o{aoo c c rc toAoAoPdAedPdIeIePde::C:C:II C I DrDrIr01e e eD v=vv=A P = ii i ddsdc8 t 410 oo 3}}ccc} pp odB-dd----ee-ee -- g-ip na Vccrrtt cccFhhhImmmi!Dii!! r n!8!nd dDooccccpp ccpououuModSSdSdSeeeeRee:t:t:t 0A A A rMrxMrMeDeDecDM0vMvMv SS0 S iRiiRR1d 0 dd 0 7nnnooo1tt tF F0I dI fXxXffoooM0Monn coctcoawd 0.C0.C.i P P0nSiU0SUSk kt 3kiV iVi_fe0pepppprpirxis4isidnvni0nigogigo0 n3 n dm_m 6m iuiaiu04ncncpcr(r0krkonoso no is owodnddgnF ee Iee o1 oDVrppr)pa I aa ttntaDnc ococphihotht! !c!n d Bu teettPetpcccpPpp ppuuo,uo01rSSr SAte SMiM edFAAIdAM!!IMMCDD_D DM S ! ISdR:RRDFF I IXXo0MM0nEE eV ! FFAIPdC IoPCXX:MUPM ne0E UE!!1V CC nw awnongnsnUiUsiBtS o i_PVnVoe enfufr irsiudsnndvikii onokn=onndw o_ u1waunn0pn n(7kok n0rnos 0orto tgrn1t ote F1t ooos rru) s n unudapnop ppo3piottcor trsswiutuodeper:dpkd !ppc! ooi e MVeFFcdIdFIo!X!I rM XDEe sEI o!! D FFIIC o XPCnoXPU nMM Un EEA o!!VdV ePCeCr:ePrs Pisc0UU1i ene VVn t Wra rusniusiiktnokon nfnno woo uunrwnnn kA konPonro rowwns nnnot ao to gtorrse s u n1unpop:potto p raosrstpu_tuepdaeppp!pdo!o irc r teed En FddI !dX=! oM e! FFIIC ng ko PrXXiMMUenEi aE!!tVd b _eCraCfPscPiUdikU vo V=Vine edr_u1rssan0i1ipkon0o(nso7n tw0uuan1n eauppken1r noo) cwow nnomna ptm ooi ornrcs u_ indpfno:piott od ( 0rstps3u drttVdcpkpF!o eoIrD n0E )e eIF=IdDd! X! o1M ! PX: 70 FA dCIP0o ie UMnE e0W!aV C r tri sPnifiUtoo V_rne f iArusndPi kvinosntdo_w aagnun pe( konrs1o: tanw nago tpe1_o rs)a p uapinocppioticdr sti d=uepd: p2! 8 o t1 EFFIdIX! MDV !ID FI CXoPnUM E!VAP eCr: Ps8Ui o1Vn rerusniknoonw unn korn ownno t osru npopotr tsuepdp! o te ddo! ne uIiXnMitE_!f CiPdUvi dVe_rasp(isont augen1k)no wapni cori dn: o0t 2s FpIpDorVtIDe do! n AP d: o0ne2 n irt_efaidbdavicdk_ =a p2(s0t10a7g0e11) ( acpiocmimodn:_ 4f1id 1pFIaDcVkeIdD) o n= 1A0P:7 040 Wait for AP stage 1: ap_apicid = 3 readback = 3010701 common_fid(packed) = 10700 common_fid = 10700 FID Change Node:00, F3xD4: c3310f27 FID Change Node:01, F3xD4: c3310f27 End FIDVIDMSR 0xc0010071 0x00800003 0x30036040 mcp55_num:01 ...WARM RESET... coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 Start other core - nodeid: 01 cores: ccc0o3oorrr x:-xxxs::: ta r-t-----e-d -- { a{ { p AaAPApPIPIiCICcICiIDIDd D= : = = F0o300 uNn12dO DNNE3OOIDD DwEEo IIr=DD k - - ::- 2c3o1}d}r-c--P-r-m-m si o i {ctc{c{ o rar rod oAcAtceAP:PoPeoddI IdICeCe:CrIeI:I: 0 DvD D r1r =i=eAe= v d vP iniscc -cc }r o e o t - --p-ooB--e-a-ddee c tFmmmiciia! t oocc cIchDhcccrV!rrp! ScD fo oooeccdpddptMeASueeu:S:MRS: e e D rM0rtrteAeSxeAvMvMvRc0 D D iM0iMidSddS1 R R0 nd nn 0oo7oot1ttn ef0 fFodxoI !0d.i. t un0inE8ndned. gcnoodpd 0 C0S_SikfkSnP0iU3iikiit dppp_0Vvppifxeiipnini3rdgs_ngd0 v0 isg tmi3moinmaid60_c igcre4srucrno20toc aokc oao !:t e2dweieen c E an pipadppdoatrt:ai Fcc c tc0Iihnh!o!h3Dd I s upuSoRcucppM1pcupS 1SRSR Ser eStet0txeAtAdcMAMD!0DMDM 0MMS 0 0R F I7X1M E0F!x d0dI oC0oXM8Pnne0UeE! 0V kssoe0iinr3PnUiis 0ttiVox__fen3fiir 0d0dsuv0vinik3iondn0d_ _o0acuawpn np(( :epp ottrmaca wngpgn oe5e1ot15)_r ) n s aaunupppmotipi: 0cocis1irdtud te do!8cr 11 MVIFFFI!II XDDV oneEIDD!F I oCoXMnPnE U A!A P PV:eC: rP 8csU 11iV te r suinoknno uwnn knoor wnn otor sunpotpo rsutpedpo!r n d d! o Fe IXinMEi!t_ fCPidUv Vied_rssitaogn e2u nkapniowcnid o:r 0 2no t supported! done init_fidvid_ap(stage1) apicid: 41 FIDVID on AP: 41 fill_mem_ctrl() enable_smbus() raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 00000000 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000050 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000051 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000052 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000053 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00008003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00008000 AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000001 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000054 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000055 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000056 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000057 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 0001a003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 0001a000 AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000002 mctAutoInitMCT_D: mct_init Node 00000003 mctAutoInitMCT_D: mct_init Node 00000004 mctAutoInitMCT_D: mct_init Node 00000005 mctAutoInitMCT_D: mct_init Node 00000006 mctAutoInitMCT_D: mct_init Node 00000007 mctAutoInitMCT_D: SyncDCTsReady_D mct_SyncDCTsReady: Node 00000000 mct_SyncDCTsReady: DramEnabled mct_SyncDCTsReady: Node 00000001 mct_SyncDCTsReady: DramEnabled mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: ffffff BottomIO: e00000 Node: 01 base: 1200000 limit: 21fffff BottomIO: e00000 Copy dram map from Node 0 to Node 01 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:00e00000 CPUMemTyping: Bottom32bIO:00e00000 CPUMemTyping: Bottom40bIO:02200000 mctAutoInitMCT_D: DQSTiming_D DQSTiming_D: mct_BeforeDQSTrain_D: vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: step 2a vErrara350: step 2b vErrara350: step 3 vErrara350: step 4 vErrara350: step 4b vErrara350: step 5 DQSTiming_D: TrainReceiverEn_D FirstPass: TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001107 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001007 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done DQSTiming_D: mct_TrainDQSPos_D TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done DQSTiming_D: mctSetEccDQSRcvrEn_D DQSTiming_D: TrainMaxReadLatency_D DQSTiming_D: mct_EndDQSTraining_D DQSTiming_D: MCTMemClr_D mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 00001107 InterleaveNodes_D: ErrStatus 00000010 InterleaveNodes_D: ErrCode 00000000 InterleaveNodes_D: Done InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002003 InterleaveChannels_D: Node 00000000 InterleaveChannels_D: Status 00001107 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00012584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002002 InterleaveChannels_D: Node 00000001 InterleaveChannels_D: Status 00001007 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000002 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000003 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000004 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000005 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000006 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000007 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECCInit 0 ECC enabled on node: 00000000 ECC enabled on node: 00000001 ECCInit 1 ECCInit 2 ECCInit 3 mctAutoInitMCT_D: MCTMemClr_D mct_FinalMCT_D: Clr Cl, Wb All Done raminit_amdmct end: *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf18 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing image to RAM. Jumping to image. coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 11:11:04 CEST 2009 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.0 links increase to 8 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:19.0 links increase to 8 PCI: 00:19.3 siblings=3 CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0369] enabled next_unitid: 0011 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [10de/0369] enabled PCI: 00:02.0 [10de/0364] enabled PCI: 00:02.1 [10de/0368] enabled PCI: 00:02.2 [10de/036a] enabled PCI: 00:02.3 [10de/036b] enabled PCI: 00:03.0 [10de/036c] enabled PCI: 00:03.1 [10de/036d] enabled PCI: 00:05.0 [10de/036e] enabled PCI: 00:06.0 [10de/037f] enabled PCI: 00:06.1 [10de/037f] enabled PCI: 00:06.2 [10de/037f] enabled PCI: 00:07.0 [10de/0370] enabled PCI: 00:07.1 [10de/0371] disabled PCI: 00:09.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0373] enabled PCI: 00:0b.0 [10de/0376] enabled PCI: 00:0e.0 [10de/0378] enabled PCI: 00:10.0 [10de/0377] enabled PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled smbus: PCI: 00:02.1[0]->I2C: 01:50 enabled smbus: PCI: 00:02.1[0]->I2C: 01:51 enabled smbus: PCI: 00:02.1[0]->I2C: 01:52 enabled smbus: PCI: 00:02.1[0]->I2C: 01:53 enabled smbus: PCI: 00:02.1[0]->I2C: 01:54 enabled smbus: PCI: 00:02.1[0]->I2C: 01:55 enabled smbus: PCI: 00:02.1[0]->I2C: 01:56 enabled smbus: PCI: 00:02.1[0]->I2C: 01:57 enabled smbus: PCI: 00:02.1[1]->I2C: 02:51 enabled PCI: pci_scan_bus for bus 01 PCI: 01:04.0 [1002/515e] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004

5 4

[patch] Fix CONFIG_GFXUMA in mtrr.c
by Bao, Zheng 11 Aug '09

11 Aug '09

The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1. We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 4505) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -418,7 +418,7 @@ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#ifdef CONFIG_GFXUMA +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ // For now we assume the UMA space is at the end of memory if (var_state.hole_startk || var_state.hole_sizek) { printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");

2 2

[v2] r4525 - trunk/coreboot-v2/src/cpu/x86/mtrr
by svn＠coreboot.org 11 Aug '09

11 Aug '09

Author: zbao Date: 2009-08-11 05:18:11 +0200 (Tue, 11 Aug 2009) New Revision: 4525 Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c Log: The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1. We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-08-10 15:57:05 UTC (rev 4524) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-08-11 03:18:11 UTC (rev 4525) @@ -418,7 +418,7 @@ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#ifdef CONFIG_GFXUMA +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ // For now we assume the UMA space is at the end of memory if (var_state.hole_startk || var_state.hole_sizek) { printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");

1 0

AMD RS690 TMDS
by Daniel Toussaint 11 Aug '09

11 Aug '09

Dear All, I am working on supporting yet another AMD 690E based board. We have everything working fine, except for the HDMI output. I can't seem to switch to an HDMI or DVI monitor with Xrandr. The RS690 Register programming requirements , page 65 (PCIE inititialization for TMDS) starts explaining the steps to get TMDS working - as far as I can see they are not implemented yet in southbridge/amd/rs690 ? Implemening those steps would bring up HDMI or are there other things that need to be taken care of ? The VBIOS binary is given to me by AMD and has HDMI support, so they say. The ASIC revisision of the chip is A12. Any comments / idea's are more than welcome. Greetings, Daniel Toussaint

1 0

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coreboot August 2009