coreboot August 2009

coreboot@coreboot.org

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356 discussions

[v2] r4507 - trunk/coreboot-v2/src/pc80
by svn＠coreboot.org 06 Aug '09

06 Aug '09

Author: stepan Date: 2009-08-06 13:36:33 +0200 (Thu, 06 Aug 2009) New Revision: 4507 Modified: trunk/coreboot-v2/src/pc80/serial.c Log: fix for the case that CONFIG_TTYS0_DIV is defined in mainboard's Config.lb Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/pc80/serial.c =================================================================== --- trunk/coreboot-v2/src/pc80/serial.c 2009-08-06 04:22:12 UTC (rev 4506) +++ trunk/coreboot-v2/src/pc80/serial.c 2009-08-06 11:36:33 UTC (rev 4507) @@ -13,7 +13,9 @@ #error Bad ttys0 baud rate #endif +#ifndef CONFIG_TTYS0_DIV #define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif /* Line Control Settings */ #ifndef CONFIG_TTYS0_LCS

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Re: [coreboot] Recent wpdchanges to acpi_write_rsdp
by Harrison, Jon (SELEX GALILEO, UK) 06 Aug '09

06 Aug '09

OK, I think I've seen it now. The API to acpi_add_table has changed too. It's now passed the rsdp as the root of the table structs rather than rsdt. Shouldn't we really have an announces list to advertise fairly fundamental API changes like this ? > -----Original Message----- > From: Harrison, Jon (SELEX GALILEO, UK) > Sent: 06 August 2009 11:57 > To: 'coreboot(a)coreboot.org' > Subject: Recent wpdchanges to acpi_write_rsdp > > > Hi guys, > > I've finally got my EPIA-N/CN400 port booting all of the way > into linux (fc9 2.6.25) > > I've been merging my latest back into a copy of the current > trunk (R4506)to get patches together, but I've found that > ACPI is now broken in my build. > > It appear that the API to acpi_write_rsdp has changed to > allow an xsdt table to be written. > > I have tried including and xsdt and also setting the pointer > NULL the results are both the same. > > Is there some other table revision issue or perhaps alignment > issue that needs to be taken care of ?? > > Thanks for any help. I'm on hols from tomorrow and would like > to get the patch out before I go. > > Before acpi_write_rsdp API change::: > > High Tables Base is 3bff0000. > Copying Interrupt Routing Table to 0x000f0000... done. > Copying Interrupt Routing Table to 0x3bff0000... done. > ACPI: Writing ACPI tables at 3bff0400... > ACPI: * FACS > ACPI: * DSDT > ACPI: * DSDT @ 3bff04c0 Length 11fc > ACPI: * FADT > ACPI: added table 1/8 Length now 40 > ACPI: * MADT > ACPI: Creating lapic entry for CPU #0 in MADT > ACPI: added table 2/8 Length now 44 > ACPI: done. > Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp > table end at: 3bff1c10 - 3bff1d30 Moving GDT to > 0x3bff2000...ok Multiboot Information structure has been written. > Writing high table forward entry at 0x00000500 Wrote coreboot > table at: 00000500 - 00000518 checksum 9fdf New > low_table_end: 0x00000518 Now going to write high coreboot > table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust > low_table_end from 0x00000518 to 0x00001000 Adjust > rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table > area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum ad2e > > After acpi_write_rsdp API change::: > > High Tables Base is 3bff0000. > Copying Interrupt Routing Table to 0x000f0000... done. > Copying Interrupt Routing Table to 0x3bff0000... done. > ACPI: Writing ACPI tables at 3bff0400... > ACPI: * FACS > ACPI: * DSDT > ACPI: * DSDT @ 3bff04c0 Length 11fc > ACPI: * FADT > ACPI: Error: Could not add ACPI table, too many tables. > ACPI: * MADT > ACPI: Error: Could not add ACPI table, too many tables. > ACPI: done. > Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp > table end at: 3bff1c10 - 3bff1d30 Moving GDT to > 0x3bff2000...ok Multiboot Information structure has been written. > Writing high table forward entry at 0x00000500 Wrote coreboot > table at: 00000500 - 00000518 checksum 9fdf New > low_table_end: 0x00000518 Now going to write high coreboot > table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust > low_table_end from 0x00000518 to 0x00001000 Adjust > rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table > area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum 9a77 SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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Recent wpdchanges to acpi_write_rsdp
by Harrison, Jon (SELEX GALILEO, UK) 06 Aug '09

06 Aug '09

Hi guys, I've finally got my EPIA-N/CN400 port booting all of the way into linux (fc9 2.6.25) I've been merging my latest back into a copy of the current trunk (R4506)to get patches together, but I've found that ACPI is now broken in my build. It appear that the API to acpi_write_rsdp has changed to allow an xsdt table to be written. I have tried including and xsdt and also setting the pointer NULL the results are both the same. Is there some other table revision issue or perhaps alignment issue that needs to be taken care of ?? Thanks for any help. I'm on hols from tomorrow and would like to get the patch out before I go. Before acpi_write_rsdp API change::: High Tables Base is 3bff0000. Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x3bff0000... done. ACPI: Writing ACPI tables at 3bff0400... ACPI: * FACS ACPI: * DSDT ACPI: * DSDT @ 3bff04c0 Length 11fc ACPI: * FADT ACPI: added table 1/8 Length now 40 ACPI: * MADT ACPI: Creating lapic entry for CPU #0 in MADT ACPI: added table 2/8 Length now 44 ACPI: done. Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp table end at: 3bff1c10 - 3bff1d30 Moving GDT to 0x3bff2000...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 9fdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum ad2e After acpi_write_rsdp API change::: High Tables Base is 3bff0000. Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x3bff0000... done. ACPI: Writing ACPI tables at 3bff0400... ACPI: * FACS ACPI: * DSDT ACPI: * DSDT @ 3bff04c0 Length 11fc ACPI: * FADT ACPI: Error: Could not add ACPI table, too many tables. ACPI: * MADT ACPI: Error: Could not add ACPI table, too many tables. ACPI: done. Wrote the mp table end at: 000f0440 - 000f0560 Wrote the mp table end at: 3bff1c10 - 3bff1d30 Moving GDT to 0x3bff2000...ok Multiboot Information structure has been written. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 9fdf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3bff2400 rom_table_end = 0x3bff2400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3bff2400 to 0x3c000000 Adding high table area Wrote coreboot table at: 3bff2400 - 3bff2ad4 checksum 9a77 SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England & Wales. Company no. 02426132 ******************************************************************** This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. ********************************************************************

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[FILO] r104 - trunk/filo/drivers
by svn＠coreboot.org 06 Aug '09

06 Aug '09

Author: stepan Date: 2009-08-06 12:21:41 +0200 (Thu, 06 Aug 2009) New Revision: 104 Modified: trunk/filo/drivers/intel.c Log: fix physical memory access in intel driver.. Modified: trunk/filo/drivers/intel.c =================================================================== --- trunk/filo/drivers/intel.c 2009-07-30 17:10:26 UTC (rev 103) +++ trunk/filo/drivers/intel.c 2009-08-06 10:21:41 UTC (rev 104) @@ -24,7 +24,7 @@ #define DEBUG_THIS CONFIG_DEBUG_INTEL #include <debug.h> -#define DEFAULT_RCBA 0xfed1c000 +#define DEFAULT_RCBA phys_to_virt(0xfed1c000) #define PM1_STS 0x00 #define PWRBTN_STS (1 << 8)

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SerialICE 1.0 - QEMU stops responding
by Daniel Liu 06 Aug '09

06 Aug '09

Hey, I've been trying to use SerialICE to trace through some BIOS code, but periodically QEMU stops responding. The SerialICE rom loaded onto the target motherboard's bios chip still responds to serial commands. It's not a specific instruction that causes it to stop, it seems to stop at random points when running normally and when debugging with GDB. Does anyone know why this might be happening? I setup SerialICE following the README instructions for QEMU 0.10.4. My host system with QEMU is running Debian Linux 2.6.30-1-amd64. My target board is an ASUS P5Q-EM DO based on the Q45 Chipset with an ICH10. I'm using the intel_d945gclf.c mainboard configuration (which works fine with the newer chipset). Thanks, Daniel Liu

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usb rom progress
by Jason Wang 06 Aug '09

06 Aug '09

Hi all Since the usb rom can detect the USB devices, but i am bloced after the UHCI initialization, in set_address function it failed at can not communicate with the USB device. Is there any one who can help me about that? Or give me some advices about how to deal with this.... hello, initialize_usb 00:13.0 4387:1002.0 OHCI controller Not supported. 00:13.1 4388:1002.1 OHCI controller Not supported. 00:13.2 4389:1002.2 OHCI controller Not supported. 00:13.3 438a:1002.3 OHCI controller Not supported. 00:13.4 438b:1002.4 OHCI controller Not supported. 00:13.5 4386:1002.5 EHCI controller Not supported. 00:05.0 3038:1106.0 UHCI controller hstart:55b0,size:ffffc 00:05.1 3038:1106.1 UHCI controller fullspeed device control packet, req 500 SETUP packet (at 6ad00) to 0.0 failed td (counter at 3) returns: bitstuff err: 0, CRC err: 0, NAK rcvd: 0, Babble: 0, Data Buffer err : 0, Stalled: 0, Active: 1 still active - timeout? set_address failed fullspeed device control packet, req 500 SETUP packet (at 6ad00) to 0.0 failed td (counter at 3) returns: bitstuff err: 0, CRC err: 0, NAK rcvd: 0, Babble: 0, Data Buffer err : 0, Stalled: 0, Active: 1 still active - timeout? set_address failed fullspeed device control packet, req 500 SETUP packet (at 6ad00) to 0.0 failed td (counter at 3) returns: bitstuff err: 0, CRC err: 0, NAK rcvd: 0, Babble: 0, Data Buffer err : 0, Stalled: 0, Active: 1 still active - timeout? set_address failed fullspeed device -- Jason Wang Peking University

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790GX lspci output
by Andrew Suessmuth 05 Aug '09

05 Aug '09

The output from lspci -nnvvvxxxx run on an MSI DKA790GX-Platinum, as requested by Carl-Daniel Hailfinger.

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filo compile errors
by Jason Wang 05 Aug '09

05 Aug '09

hi all it seems there is a variable are not included in /include/grub/shard.h which would caused error with main/grub/completions.c UNIQUE_BUF undefined details are patched. Index: include/grub/shared.h =================================================================== --- include/grub/shared.h (revision 103) +++ include/grub/shared.h (working copy) @@ -55,6 +55,7 @@ #define COMPLETION_BUFLEN MAX_CMDLINE /* The buffer for the unique string. */ +extern char UNIQUE_BUF[]; #define UNIQUE_BUFLEN MAX_CMDLINE /* The buffer for the menu entries. */ -- Jason Wang Peking University

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[v2] r4499 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 05 Aug '09

05 Aug '09

Author: stepan Date: 2009-08-05 15:10:38 +0200 (Wed, 05 Aug 2009) New Revision: 4499 Modified: trunk/payloads/libpayload/libc/string.c Log: fix buggy comment in libpayload's strncat function Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/libc/string.c =================================================================== --- trunk/payloads/libpayload/libc/string.c 2009-08-05 13:06:37 UTC (rev 4498) +++ trunk/payloads/libpayload/libc/string.c 2009-08-05 13:10:38 UTC (rev 4499) @@ -165,7 +165,7 @@ * * @param d The destination string. * @param s The source string. - * @param n The target string will have a length of n characters at most. + * @param n Not more than n characters from s will be appended to d. * @return A pointer to the destination string. */ char *strncat(char *d, const char *s, size_t n)

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[PATCH]es: Various changes from the kconfig branch
by Patrick Georgi 05 Aug '09

05 Aug '09

Hi, as preparation for the kconfig merge, here are some changes from the kconfig tree that are unrelated to kconfig itself. 20090805-1-ttys0-rename Takes care of the different CONFIG_* names of the variable containing the serial I/O port 20090805-2-config-prefixes Some more CONFIG_* prefixes that were missing 20090805-3-empty-files These changes exist mostly to make diff happy, which ignores empty files (or rather: Make Patrick happy when he's using diff). Maybe the right way would be to delete those files. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Index: coreboot-v2/src/arch/i386/lib/printk_init.c =================================================================== --- coreboot-v2.orig/src/arch/i386/lib/printk_init.c +++ coreboot-v2/src/arch/i386/lib/printk_init.c @@ -8,6 +8,10 @@ #include <stdarg.h> #include <console/loglevel.h> +#if !defined(CONFIG_TTYS0_BASE) +#define CONFIG_TTYS0_BASE CONFIG_SERIAL_IOBASE +#endif + /* printk's without a loglevel use this.. */ #define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */ Index: coreboot-v2/src/include/uart8250.h =================================================================== --- coreboot-v2.orig/src/include/uart8250.h +++ coreboot-v2/src/include/uart8250.h @@ -1,6 +1,10 @@ #ifndef UART8250_H #define UART8250_H +#if !defined(CONFIG_TTYS0_BASE) +#define CONFIG_TTYS0_BASE CONFIG_SERIAL_IOBASE +#endif + struct uart8250 { unsigned int baud; /* Do I need an lcs parameter here? */ Index: coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- coreboot-v2.orig/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -273,7 +273,7 @@ static void i82801gx_power_options(devic /* Set up power management block and determine sleep mode */ pmbase = pci_read_config16(dev, 0x40) & 0xfffe; reg32 = inl(pmbase + 0x04); // PM1_CNT -#if HAVE_ACPI_RESUME +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0; printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n", reg32, acpi_slp_type); Index: coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h =================================================================== --- coreboot-v2.orig/src/southbridge/intel/i82801gx/i82801gx_power.h +++ coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_power.h @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif Index: coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c =================================================================== --- coreboot-v2.orig/src/southbridge/intel/i82801gx/i82801gx_smihandler.c +++ coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_smihandler.c @@ -300,7 +300,7 @@ static void southbridge_smi_sleep(unsign * CMOS or even better from GNVS. Right now it's hard * coded at compile time. */ - u8 s5pwr = MAINBOARD_POWER_ON_AFTER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); Index: coreboot-v2/src/cpu/x86/32bit/entry32.lds =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/32bit/entry32.lds @@ -0,0 +1 @@ +# Index: coreboot-v2/src/cpu/x86/fpu/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/fpu/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/cpu/x86/mmx/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/mmx/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/cpu/x86/sse/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/cpu/x86/sse/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/drivers/generic/generic/Config.lb =================================================================== --- /dev/null +++ coreboot-v2/src/drivers/generic/generic/Config.lb @@ -0,0 +1 @@ +# Index: coreboot-v2/src/northbridge/intel/i855pm/i855pm.h =================================================================== --- /dev/null +++ coreboot-v2/src/northbridge/intel/i855pm/i855pm.h @@ -0,0 +1 @@ +#

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coreboot August 2009