coreboot August 2009

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build service results for r4541
by coreboot information 13 Aug '09

13 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4541 to the coreboot repository. This caused the following changes: Change Log: Fix some conflicting types of variables Remove the normal/* files from the image. they're just copies of fallback/* anyway. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=atc-6220&vendo… Compilation of a-trend:atc-6240 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=be6-ii_v2_0&ve… Compilation of asus:p2b is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=p2b&vendor=asu… Compilation of asus:p2b-d is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=p2b-d&vendor=a… Compilation of asus:p2b-ds is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=p2b-ds&vendor=… Compilation of asus:p2b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=p2b-f&vendor=a… Compilation of asus:p3b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=pt-6ibd&vendor… Compilation of biostar:m6tba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=deskpro_en_sff… Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=ep405pc&vendor… Compilation of gigabyte:ga-6bxc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=ga-6bxc&vendor… Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=nova4899r&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=sandpointx3_al… Compilation of msi:ms6119 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=ms6119&vendor=… Compilation of msi:ms6147 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=ms6147&vendor=… Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=sy-6ba-plus-ii… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=briq&vendor=to… Compilation of tyan:s1846 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=s1846&vendor=t… Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4541&device=epia-m&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4541 - in trunk/coreboot-v2/src: arch/i386 cpu/amd/model_fxx mainboard/amd/serengeti_cheetah northbridge/amd/amdk8
by svn＠coreboot.org 13 Aug '09

13 Aug '09

Author: oxygene Date: 2009-08-13 09:33:55 +0200 (Thu, 13 Aug 2009) New Revision: 4541 Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig Log: Fix some conflicting types of variables Remove the normal/* files from the image. they're just copies of fallback/* anyway. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-12 20:25:24 UTC (rev 4540) +++ trunk/coreboot-v2/src/arch/i386/Makefile.inc 2009-08-13 07:33:55 UTC (rev 4541) @@ -14,7 +14,6 @@ $(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL) $(Q)rm -f $@ $(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock - $(Q)$(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG) $(Q)if [ -f fallback/coreboot_apc ]; \ then \ $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \ @@ -25,8 +24,6 @@ else printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n" $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_COMPRESS_FLAG) - printf " PAYLOAD $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n" - $(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE) normal/payload $(CBFS_COMPRESS_FLAG) $(CBFSTOOL) ./build/coreboot.rom print endif Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-08-12 20:25:24 UTC (rev 4540) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-08-13 07:33:55 UTC (rev 4541) @@ -1,10 +1,10 @@ config HAVE_INIT_TIMER - int - default 1 + bool + default y config HAVE_MOVNTI - int - default 1 + bool + default y config CPU_ADDR_BITS int Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-08-12 20:25:24 UTC (rev 4540) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-08-13 07:33:55 UTC (rev 4541) @@ -49,13 +49,13 @@ depends on BOARD_AMD_SERENGETI_CHEETAH config HAVE_HARD_RESET - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config IOAPIC - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config SB_HT_CHAIN_ON_BUS0 @@ -164,8 +164,8 @@ depends on BOARD_AMD_SERENGETI_CHEETAH config SERIAL_CPU_INIT - int - default 0 + bool + default n depends on BOARD_AMD_SERENGETI_CHEETAH config AP_CODE_IN_CAR Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-08-12 20:25:24 UTC (rev 4540) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-08-13 07:33:55 UTC (rev 4541) @@ -26,8 +26,8 @@ default 0x4000000 config HAVE_HIGH_TABLES - int - default 1 + bool + default y -source src/northbridge/amd/amdk8/root_complex/Kconfig \ No newline at end of file +source src/northbridge/amd/amdk8/root_complex/Kconfig

1 0

option rom progress and some issues
by Jason Wang 13 Aug '09

13 Aug '09

Hi all Since USB ROM has already added into the booting menu list(IPL table), and the UHCI stack can be run well in usbrom now, i have some issues to confirm, any advices are welcome. 1) <<Plug and Play BIOS Specification>>Page21, There is an r Return Status from Initialization Call of OPTION ROM. Which used to let the bios know the status. But it seems Seabios does not check the return code. Is that OK? 2) After Seabios make an far call into the BEV, the OPTION ROM should begin to load OS.if it failed, it can return back to BIOS. But it can not return back with my USB OPTION ROM, Is there any configuration I should set? 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the initialization.But after that how does it jump into the booting code which located in the USB disk? BTW: Kevin: I looked the code of Seabios ata.c to learn how seabios booting OS from ata disk. some question i have: 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios know the bootstrap vector based the driver ID? what does ata fill FDPT area for? Should my usbrom do the same? For my usbrom, i should not use add_bcv to add option rom into IPL ? or just take the ata as example? -- Jason Wang Peking University

2 7

why did set smaller ROM size for dbm690t and pistachio board.
by 유택연 13 Aug '09

13 Aug '09

In Config.lb at those two boards, it has this line. option CONFIG_ROM_SIZE = 1024*1024 - 55808 But Config-abuild.lb is not. Final ROM size 992768 bytes by this setting. I need to set like this to boot properly?

2 1

[PATCH]Disable failover in K8 based boards
by Patrick Georgi 12 Aug '09

12 Aug '09

Hi, attached patch disables failover for K8 based boards and makes them use the more usual fallback/normal style. Fam10h requires some reduction in size, or other tricks as the ROM part exceeds 64k (the original ROM mapping) by just a bit. I'll work on that soon. The {HAVE,USE}_FAILOVER stuff still stays in the code itself as it might be useful as a reference (ie. what is strictly necessary to configure ROM mapping) for later work. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Config.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -107,7 +107,7 @@ default CONFIG_ROM_SIZE=524288 ## default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -116,7 +116,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Config.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Config.lb @@ -23,7 +23,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end driver mainboard.o Index: coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Options.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Options.lb @@ -102,9 +102,9 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 * CONFIG_HAVE_FAILOVER_BOOT default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 0 default CONFIG_HAVE_HARD_RESET = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 default CONFIG_IRQ_SLOT_COUNT = 13 Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -70,7 +70,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/sis/sis966/sis966_early_smbus.c" -#include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -23,7 +23,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -135,7 +135,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -144,7 +144,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Config.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb @@ -21,7 +21,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb @@ -136,7 +136,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -150,7 +150,7 @@ default CONFIG_HAVE_FANCTL=1 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Config.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Options.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb @@ -109,7 +109,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-8K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8K -default CONFIG_FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -118,7 +118,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Config.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Config.lb @@ -24,7 +24,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Options.lb @@ -115,7 +115,7 @@ default CONFIG_ROM_SIZE=(512*1024) default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=(4*1024) +default CONFIG_FAILOVER_SIZE=(4*1024) * CONFIG_HAVE_FAILOVER_BOOT ### ### Build options @@ -125,7 +125,7 @@ default CONFIG_FAILOVER_SIZE=(4*1024) ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/msi/ms7260/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Config.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Config.lb @@ -20,7 +20,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Options.lb @@ -102,10 +102,10 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 * CONFIG_HAVE_FAILOVER_BOOT default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 0 default CONFIG_HAVE_HARD_RESET = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct. Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Config.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb @@ -21,7 +21,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Options.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -133,7 +133,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,7 +142,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Config.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb @@ -18,7 +18,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb @@ -137,7 +137,7 @@ default CONFIG_MULTIBOOT=0 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -146,7 +146,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Config.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb @@ -21,7 +21,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb @@ -130,7 +130,7 @@ default CONFIG_ROM_SIZE=0x100000 ## default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -139,7 +139,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot @@ -252,7 +252,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_D ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0xf000 +default CONFIG_ROM_IMAGE_SIZE = 0x10000 - CONFIG_FAILOVER_SIZE ## Index: coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Config.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Options.lb @@ -95,7 +95,7 @@ default CONFIG_ROM_SIZE=1024*1024 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -104,7 +104,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Config.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Config.lb @@ -21,7 +21,7 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb arch i386 end Index: coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Options.lb @@ -133,7 +133,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,7 +142,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0 ## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/amd/serengeti_cheetah/Config-abuild.lb +++ coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/asus/a8n_e/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/asus/a8n_e/Config-abuild.lb +++ coreboot-v2/targets/asus/a8n_e/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/gigabyte/ga_2761gxdk/Config-abuild.lb +++ coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb @@ -45,13 +45,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-Failover" -end - - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/gigabyte/m57sli/Config-abuild.lb +++ coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/iwill/dk8_htx/Config-abuild.lb +++ coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/msi/ms7135/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/msi/ms7135/Config-abuild.lb +++ coreboot-v2/targets/msi/ms7135/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/msi/ms7260/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/msi/ms7260/Config-abuild.lb +++ coreboot-v2/targets/msi/ms7260/Config-abuild.lb @@ -42,13 +42,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE = 1 - option CONFIG_USE_FALLBACK_IMAGE = 0 - option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION = ".0Failover" -end - -# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/nvidia/l1_2pvv/Config-abuild.lb +++ coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dme/Config-abuild.lb +++ coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb @@ -24,12 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dmr/Config-abuild.lb +++ coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb @@ -21,10 +21,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/tyan/s2895/Config-abuild.lb +++ coreboot-v2/targets/tyan/s2895/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/tyan/s2912/Config-abuild.lb +++ coreboot-v2/targets/tyan/s2912/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end -romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

2 6

[BuildROM] r268 - buildrom-devel/packages/memtest
by svn＠coreboot.org 12 Aug '09

12 Aug '09

Author: myles Date: 2009-08-12 23:16:35 +0200 (Wed, 12 Aug 2009) New Revision: 268 Modified: buildrom-devel/packages/memtest/config.h.serial buildrom-devel/packages/memtest/memtest.mk Log: Update the URL and config file for memtest so it builds again. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/packages/memtest/config.h.serial =================================================================== --- buildrom-devel/packages/memtest/config.h.serial 2009-05-21 15:16:09 UTC (rev 267) +++ buildrom-devel/packages/memtest/config.h.serial 2009-08-12 21:16:35 UTC (rev 268) @@ -1,9 +1,9 @@ -/* config.h - MemTest-86 Version 3.0 +/* config.h - MemTest-86 Version 3.3 * * Compile time configuration options * * Released under version 2 of the Gnu Public License. - * By Chris Brady, cbrady(a)sgi.com + * By Chris Brady */ /* PARITY_MEM - Enables support for reporting memory parity errors */ @@ -15,12 +15,12 @@ /* to enable. */ #define SERIAL_CONSOLE_DEFAULT 1 +/* SERIAL_TTY - The default serial port to use. 0=ttyS0, 1=ttyS1 */ +#define SERIAL_TTY 0 + /* SERIAL_BAUD_RATE - Baud rate for the serial console */ #define SERIAL_BAUD_RATE 115200 -/* BEEP_MODE - Beep on error. Default off, Change to 1 to enable */ -#define BEEP_MODE 0 - /* SCRN_DEBUG - extra check for SCREEN_BUFFER */ /* #define SCRN_DEBUG */ Modified: buildrom-devel/packages/memtest/memtest.mk =================================================================== --- buildrom-devel/packages/memtest/memtest.mk 2009-05-21 15:16:09 UTC (rev 267) +++ buildrom-devel/packages/memtest/memtest.mk 2009-08-12 21:16:35 UTC (rev 268) @@ -1,7 +1,7 @@ MEMTEST_URL=http://www.memtest86.com/ -MEMTEST_SOURCE=memtest86-3.3.tar.gz +MEMTEST_SOURCE=memtest86-3.5.tar.gz MEMTEST_DIR=$(BUILD_DIR)/memtest -MEMTEST_SRC_DIR=$(MEMTEST_DIR)/memtest86-3.3 +MEMTEST_SRC_DIR=$(MEMTEST_DIR)/memtest86-3.5 MEMTEST_STAMP_DIR=$(MEMTEST_DIR)/stamps MEMTEST_LOG_DIR=$(MEMTEST_DIR)/logs

1 0

build service results for r4540
by coreboot information 12 Aug '09

12 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4540 to the coreboot repository. This caused the following changes: Change Log: \\ are not escaped in a sane way between fedora and ubuntu! Just create these files to make sure that we don't get idiotic problems. Fix things so they build. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=atc-6220&vendo… Compilation of a-trend:atc-6240 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=be6-ii_v2_0&ve… Compilation of asus:p2b is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=p2b&vendor=asu… Compilation of asus:p2b-d is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=p2b-d&vendor=a… Compilation of asus:p2b-ds is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=p2b-ds&vendor=… Compilation of asus:p2b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=p2b-f&vendor=a… Compilation of asus:p3b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=pt-6ibd&vendor… Compilation of biostar:m6tba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=deskpro_en_sff… Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=ep405pc&vendor… Compilation of gigabyte:ga-6bxc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=ga-6bxc&vendor… Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=nova4899r&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=sandpointx3_al… Compilation of msi:ms6119 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=ms6119&vendor=… Compilation of msi:ms6147 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=ms6147&vendor=… Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=sy-6ba-plus-ii… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=briq&vendor=to… Compilation of tyan:s1846 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=s1846&vendor=t… Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4540&device=epia-m&vendor=… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4540 - trunk/coreboot-v2/documentation
by svn＠coreboot.org 12 Aug '09

12 Aug '09

Author: rminnich Date: 2009-08-12 22:25:24 +0200 (Wed, 12 Aug 2009) New Revision: 4540 Added: trunk/coreboot-v2/documentation/beginverbatim.tex trunk/coreboot-v2/documentation/endverbatim.tex Modified: trunk/coreboot-v2/documentation/Kconfig.tex trunk/coreboot-v2/documentation/Makefile Log: \\ are not escaped in a sane way between fedora and ubuntu! Just create these files to make sure that we don't get idiotic problems. Fix things so they build. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/documentation/Kconfig.tex =================================================================== --- trunk/coreboot-v2/documentation/Kconfig.tex 2009-08-12 17:16:05 UTC (rev 4539) +++ trunk/coreboot-v2/documentation/Kconfig.tex 2009-08-12 20:25:24 UTC (rev 4540) @@ -460,7 +460,7 @@ \subsection{superio} \subsection{drivers/i2c} This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are notneeed. -To compile in one of these files, name the .o directory. E.g. in serengeti_cheetah we have: +To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have: \begin{verbatim} \end{verbatim} Modified: trunk/coreboot-v2/documentation/Makefile =================================================================== --- trunk/coreboot-v2/documentation/Makefile 2009-08-12 17:16:05 UTC (rev 4539) +++ trunk/coreboot-v2/documentation/Makefile 2009-08-12 20:25:24 UTC (rev 4540) @@ -44,29 +44,29 @@ # quick, somebody! make me a macro! mainboardkconfig.tex: ../src/mainboard/Kconfig - echo '\begin{verbatim}' > $@ + cat beginverbatim.tex > $@ grep '^config' $< | awk '{print $2}' >>$@ - echo '\end{verbatim}' >> $@ + cat endverbatim.tex >> $@ skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig - echo '\begin{verbatim}' > $@ + cat beginverbatim.tex > $@ grep '^config' $< | awk '{print $2}' >>$@ - echo '\end{verbatim}' >> $@ + cat endverbatim.tex >> $@ cpukconfig.tex: ../src/cpu/Kconfig - echo '\begin{verbatim}' > $@ + cat beginverbatim.tex > $@ grep '^config' $< | awk '{print $2}' >>$@ - echo '\end{verbatim}' >> $@ + cat endverbatim.tex >> $@ socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig - echo '\begin{verbatim}' > $@ + cat beginverbatim.tex > $@ grep '^config' $< | awk '{print $2}' >>$@ - echo '\end{verbatim}' >> $@ + cat endverbatim.tex >> $@ clean: - rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex + rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketkconfig.tex distclean: clean - rm -f LinuxBIOS-AMD64.pdf mainboardkconfig.tex + rm -f LinuxBIOS-AMD64.pdf Added: trunk/coreboot-v2/documentation/beginverbatim.tex =================================================================== --- trunk/coreboot-v2/documentation/beginverbatim.tex (rev 0) +++ trunk/coreboot-v2/documentation/beginverbatim.tex 2009-08-12 20:25:24 UTC (rev 4540) @@ -0,0 +1 @@ +\begin{verbatim} Added: trunk/coreboot-v2/documentation/endverbatim.tex =================================================================== --- trunk/coreboot-v2/documentation/endverbatim.tex (rev 0) +++ trunk/coreboot-v2/documentation/endverbatim.tex 2009-08-12 20:25:24 UTC (rev 4540) @@ -0,0 +1 @@ +\end{verbatim}

1 0

Non-CBFS build infrastructure will disappear at some point
by Patrick Georgi 12 Aug '09

12 Aug '09

Hi, attached patch removes much of the old style rom image layout. After this patch, only CBFS is available. It's Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Before this patch, people should get some more time to adapt their local trees, and there are a couple of boards that work better with some changes to MTRR/XIP handling that I want to do before this patch. Consider this post a warning that something with the effect of this patch will end up in the repository eventually. Patrick Index: coreboot-v2/src/arch/i386/Config.lb =================================================================== --- coreboot-v2.orig/src/arch/i386/Config.lb +++ coreboot-v2/src/arch/i386/Config.lb @@ -1,46 +1,30 @@ -uses CONFIG_CBFS uses CONFIG_SMP uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_USE_INIT uses CONFIG_HAVE_FAILOVER_BOOT uses CONFIG_USE_FAILOVER_IMAGE uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_CBFS init init/crt0.S.lb -if CONFIG_CBFS - if CONFIG_USE_FAILOVER_IMAGE - else - initobject /src/lib/cbfs.o - initobject /src/console/vsprintf.o - initobject /src/lib/lzma.o - end +if CONFIG_USE_FAILOVER_IMAGE +else + initobject /src/lib/cbfs.o + initobject /src/console/vsprintf.o + initobject /src/lib/lzma.o end if CONFIG_HAVE_FAILOVER_BOOT if CONFIG_USE_FAILOVER_IMAGE ldscript init/ldscript_failover.lb else - if CONFIG_CBFS - ldscript init/ldscript_cbfs.lb - else - ldscript init/ldscript.lb - end + ldscript init/ldscript_cbfs.lb end else - if CONFIG_CBFS - if CONFIG_USE_FALLBACK_IMAGE - ldscript init/ldscript_fallback_cbfs.lb - else - ldscript init/ldscript_cbfs.lb - end + if CONFIG_USE_FALLBACK_IMAGE + ldscript init/ldscript_fallback_cbfs.lb else - if CONFIG_USE_FALLBACK_IMAGE - ldscript init/ldscript_fallback.lb - else - ldscript init/ldscript.lb - end + ldscript init/ldscript_cbfs.lb end end @@ -83,13 +67,6 @@ end # catch the case where there is no compression makedefine PAYLOAD-1:=payload -if CONFIG_CBFS -else -# match the case where a compression type is specified. -makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_NRV2B):=payload.nrv2b -makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_LZMA):=payload.lzma -end - # catch the case where there is precompression. Yes, this bites. if CONFIG_PRECOMPRESSED_PAYLOAD makedefine PAYLOAD-1:=payload @@ -106,8 +83,8 @@ if CONFIG_USE_FAILOVER_IMAGE else makerule coreboot.rom depends "coreboot.strip buildrom $(PAYLOAD-1)" - action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)" - action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi" + action "touch cbfs-support; ./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)" + action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 ]; then echo l > cbfs-support; fi" end end Index: coreboot-v2/src/arch/i386/init/crt0.S.lb =================================================================== --- coreboot-v2.orig/src/arch/i386/init/crt0.S.lb +++ coreboot-v2/src/arch/i386/init/crt0.S.lb @@ -74,19 +74,8 @@ __main: movl $0x4000000, %esp movl %esp, %ebp pushl %esi -#if CONFIG_CBFS == 1 pushl $str_coreboot_ram_name call cbfs_and_run_core -#else - movl $_liseg, %esi - movl $_iseg, %edi - movl $_eiseg, %ecx - subl %edi, %ecx - pushl %ecx - pushl %edi - pushl %esi - call copy_and_run_core -#endif .Lhlt: intel_chip_post_macro(0xee) /* post fe */ @@ -148,12 +137,10 @@ str_pre_main: .string "Jumping to #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ -#if CONFIG_CBFS == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1 str_coreboot_ram_name: .string "fallback/coreboot_ram" # else str_coreboot_ram_name: .string "normal/coreboot_ram" # endif -#endif #endif /* CONFIG_USE_DCACHE_RAM */ Index: coreboot-v2/src/arch/i386/lib/Config.lb =================================================================== --- coreboot-v2.orig/src/arch/i386/lib/Config.lb +++ coreboot-v2/src/arch/i386/lib/Config.lb @@ -1,7 +1,6 @@ uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_CBFS object c_start.S object cpu.c @@ -15,9 +14,5 @@ initobject printk_init.o if CONFIG_USE_FAILOVER_IMAGE else - if CONFIG_CBFS - initobject cbfs_and_run.o - else - initobject copy_and_run.o - end + initobject cbfs_and_run.o end Index: coreboot-v2/src/boot/Config.lb =================================================================== --- coreboot-v2.orig/src/boot/Config.lb +++ coreboot-v2/src/boot/Config.lb @@ -1,9 +1,5 @@ object hardwaremain.o -if CONFIG_CBFS - object selfboot.o -else - object elfboot.o -end +object selfboot.o if CONFIG_FS_PAYLOAD object filo.o end Index: coreboot-v2/src/boot/hardwaremain.c =================================================================== --- coreboot-v2.orig/src/boot/hardwaremain.c +++ coreboot-v2/src/boot/hardwaremain.c @@ -96,22 +96,11 @@ void hardwaremain(int boot_complete) * write our configuration tables. */ lb_mem = write_tables(); -#if CONFIG_CBFS == 1 # if CONFIG_USE_FALLBACK_IMAGE == 1 cbfs_load_payload(lb_mem, "fallback/payload"); # else cbfs_load_payload(lb_mem, "normal/payload"); # endif -#else - -#if CONFIG_FS_PAYLOAD == 1 -#warning "CONFIG_FS_PAYLOAD is deprecated." - filo(lb_mem); -#else -#warning "elfboot will soon be deprecated." - elfboot(lb_mem); -#endif -#endif printk(BIOS_ERR, "Boot failed.\n"); } Index: coreboot-v2/src/config/failovercalculation.lb =================================================================== --- coreboot-v2.orig/src/config/failovercalculation.lb +++ coreboot-v2/src/config/failovercalculation.lb @@ -10,13 +10,8 @@ else default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) else - if CONFIG_CBFS - default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE - default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) - else - default CONFIG_ROM_SECTION_SIZE = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) - default CONFIG_ROM_SECTION_OFFSET = 0 - end + default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FAILOVER_SIZE ) end end Index: coreboot-v2/src/config/nofailovercalculation.lb =================================================================== --- coreboot-v2.orig/src/config/nofailovercalculation.lb +++ coreboot-v2/src/config/nofailovercalculation.lb @@ -6,13 +6,8 @@ if CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE ) else - if CONFIG_CBFS - default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE - default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE ) - else - default CONFIG_ROM_SECTION_SIZE = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE ) - default CONFIG_ROM_SECTION_OFFSET = 0 - end + default CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE + default CONFIG_ROM_SECTION_OFFSET = ( CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE - CONFIG_FALLBACK_SIZE ) end ## Index: coreboot-v2/src/config/Options.lb =================================================================== --- coreboot-v2.orig/src/config/Options.lb +++ coreboot-v2/src/config/Options.lb @@ -692,11 +692,6 @@ define CONFIG_FS_FAT export always comment "Enable FAT filesystem support" end -define CONFIG_CBFS - default 1 - export always - comment "The new CBFS file system" -end define CONFIG_AUTOBOOT_DELAY default 2 export always Index: coreboot-v2/src/cpu/amd/car/copy_and_run.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/car/copy_and_run.c +++ coreboot-v2/src/cpu/amd/car/copy_and_run.c @@ -3,7 +3,6 @@ 2006/05/02 - stepan: move nrv2b to an extra file. */ -#if CONFIG_CBFS == 1 void cbfs_and_run_core(char*, unsigned ebp); static void copy_and_run(void) @@ -26,38 +25,3 @@ static void copy_and_run_ap_code_in_car( # endif } #endif - -#else -void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp); - -extern u8 _liseg, _iseg, _eiseg; - -static void copy_and_run(void) -{ - uint8_t *src, *dst; - unsigned long ilen; - - src = &_liseg; - dst = &_iseg; - ilen = &_eiseg - dst; - - copy_and_run_core(src, dst, ilen, 0); -} - -#if CONFIG_AP_CODE_IN_CAR == 1 - -extern u8 _liseg_apc, _iseg_apc, _eiseg_apc; - -static void copy_and_run_ap_code_in_car(unsigned ret_addr) -{ - uint8_t *src, *dst; - unsigned long ilen; - - src = &_liseg_apc; - dst = &_iseg_apc; - ilen = &_eiseg_apc - dst; - - copy_and_run_core(src, dst, ilen, ret_addr); -} -#endif -#endif Index: coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_lx/cache_as_ram.inc +++ coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc @@ -222,19 +222,8 @@ __main: movl $0x4000000, %esp movl %esp, %ebp pushl %esi -#if CONFIG_CBFS == 1 pushl $str_coreboot_ram_name call cbfs_and_run_core -#else - movl $_liseg, %esi - movl $_iseg, %edi - movl $_eiseg, %ecx - subl %edi, %ecx - pushl %ecx - pushl %edi - pushl %esi - call copy_and_run_core -#endif .Lhlt: intel_chip_post_macro(0xee) /* post fail ee */ @@ -295,10 +284,8 @@ str_pre_main: .string "Jumping to .previous #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ -#if CONFIG_CBFS == 1 -# if CONFIG_USE_FALLBACK_IMAGE == 1 +#if CONFIG_USE_FALLBACK_IMAGE == 1 str_coreboot_ram_name: .string "fallback/coreboot_ram" -# else +#else str_coreboot_ram_name: .string "normal/coreboot_ram" -# endif #endif Index: coreboot-v2/src/cpu/x86/car/copy_and_run.c =================================================================== --- coreboot-v2.orig/src/cpu/x86/car/copy_and_run.c +++ coreboot-v2/src/cpu/x86/car/copy_and_run.c @@ -2,7 +2,6 @@ (Written by Patrick Georgi <patrick.georgi(a)coresystems.de> for coresystems GmbH */ -#if CONFIG_CBFS == 1 void cbfs_and_run_core(char*, unsigned ebp); static void copy_and_run(unsigned cpu_reset) @@ -17,25 +16,3 @@ static void copy_and_run(unsigned cpu_re # endif } -#else -void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp); - -extern u8 _liseg, _iseg, _eiseg; - -static void copy_and_run(unsigned cpu_reset) -{ - uint8_t *src, *dst; - unsigned long ilen; - - - src = &_liseg; - dst = &_iseg; - ilen = &_eiseg - dst; - - if (cpu_reset == 1) cpu_reset = -1; - else cpu_reset = 0; - - copy_and_run_core(src, dst, ilen, cpu_reset); -} -#endif - Index: coreboot-v2/src/devices/pci_rom.c =================================================================== --- coreboot-v2.orig/src/devices/pci_rom.c +++ coreboot-v2/src/devices/pci_rom.c @@ -35,17 +35,15 @@ struct rom_header * pci_rom_probe(struct struct rom_header *rom_header; struct pci_data *rom_data; - if (CONFIG_CBFS) { - void *v; - /* if it's in FLASH, then it's as if dev->on_mainboard was true */ - v = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - printk_debug("In cbfs, rom address for %s = %p\n", - dev_path(dev), v); - if (v) { - dev->rom_address = (u32)v; - dev->on_mainboard = 1; - } - } + void *v; + /* if it's in FLASH, then it's as if dev->on_mainboard was true */ + v = cbfs_load_optionrom(dev->vendor, dev->device, NULL); + printk_debug("In cbfs, rom address for %s = %p\n", + dev_path(dev), v); + if (v) { + dev->rom_address = (u32)v; + dev->on_mainboard = 1; + } if (dev->on_mainboard) { /* this is here as a legacy path. We hope it goes away soon. Users should not have to Index: coreboot-v2/src/lib/Config.lb =================================================================== --- coreboot-v2.orig/src/lib/Config.lb +++ coreboot-v2/src/lib/Config.lb @@ -25,11 +25,5 @@ initobject memset.o initobject memcpy.o initobject memcmp.o -if CONFIG_CBFS - object cbfs.o - object lzma.o -end - -if CONFIG_COMPRESSED_PAYLOAD_LZMA - object lzma.o -end +object cbfs.o +object lzma.o Index: coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/a-trend/atc-6220/Options.lb +++ coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/a-trend/atc-6240/Options.lb +++ coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/abit/be6-ii_v2_0/Options.lb +++ coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -98,9 +97,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/advantech/pcm-5820/Options.lb +++ coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -103,9 +102,4 @@ default CONFIG_TTYS0_LCS = 0x3 # 8n1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/db800/Options.lb +++ coreboot-v2/src/mainboard/amd/db800/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -180,10 +179,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/dbm690t/Options.lb +++ coreboot-v2/src/mainboard/amd/dbm690t/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -301,9 +300,4 @@ default CONFIG_GFXUMA=1 default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/norwich/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/norwich/Options.lb +++ coreboot-v2/src/mainboard/amd/norwich/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -180,10 +179,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/pistachio/Options.lb +++ coreboot-v2/src/mainboard/amd/pistachio/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -301,9 +300,4 @@ default CONFIG_GFXUMA=1 default CONFIG_HAVE_MAINBOARD_RESOURCES=1 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/rumba/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/rumba/Options.lb +++ coreboot-v2/src/mainboard/amd/rumba/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -159,10 +158,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -18,7 +18,6 @@ # uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -362,9 +361,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -325,9 +324,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/arima/hdama/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/arima/hdama/Options.lb +++ coreboot-v2/src/mainboard/arima/hdama/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -242,9 +241,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/artecgroup/dbe61/Options.lb +++ coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -180,10 +179,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asi/mb_5blgp/Options.lb +++ coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -103,9 +102,4 @@ default CONFIG_TTYS0_LCS = 0x3 # 8n1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asi/mb_5blmp/Options.lb +++ coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_PIRQ_TABLE -uses CONFIG_CBFS uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT uses CONFIG_HAVE_HARD_RESET @@ -162,9 +161,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL= default CONFIG_VIDEO_MB = 0 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Options.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_USE_FAILOVER_IMAGE @@ -167,9 +166,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8v-e_se/Options.lb +++ coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb @@ -18,7 +18,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -167,9 +166,4 @@ default CONFIG_TTYS0_LCS = 0x3 # 8n1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/m2v-mx_se/Options.lb +++ coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb @@ -18,7 +18,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -176,9 +175,4 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/mew-am/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/mew-am/Options.lb +++ coreboot-v2/src/mainboard/asus/mew-am/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/mew-vm/Options.lb +++ coreboot-v2/src/mainboard/asus/mew-vm/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -158,9 +157,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_UDELAY_TSC=1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/p2b-d/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/p2b-d/Options.lb +++ coreboot-v2/src/mainboard/asus/p2b-d/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -103,5 +102,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/p2b-ds/Options.lb +++ coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -104,9 +103,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/p2b-f/Options.lb +++ coreboot-v2/src/mainboard/asus/p2b-f/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/p2b/Options.lb +++ coreboot-v2/src/mainboard/asus/p2b/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -98,9 +97,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/p3b-f/Options.lb +++ coreboot-v2/src/mainboard/asus/p3b-f/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/axus/tc320/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/axus/tc320/Options.lb +++ coreboot-v2/src/mainboard/axus/tc320/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -103,9 +102,4 @@ default CONFIG_TTYS0_LCS = 0x3 # 8n1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/azza/pt-6ibd/Options.lb +++ coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/bcom/winnet100/Options.lb +++ coreboot-v2/src/mainboard/bcom/winnet100/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -103,9 +102,4 @@ default CONFIG_TTYS0_LCS = 0x3 # 8n1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/bcom/winnetp680/Options.lb +++ coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -103,10 +102,4 @@ default HOSTCC = "gcc" ## default CONFIG_MAX_PCI_BUSES = 3 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/biostar/m6tba/Options.lb +++ coreboot-v2/src/mainboard/biostar/m6tba/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/broadcom/blast/Options.lb +++ coreboot-v2/src/mainboard/broadcom/blast/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -260,9 +259,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb +++ coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/dell/s1850/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/dell/s1850/Options.lb +++ coreboot-v2/src/mainboard/dell/s1850/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,9 +227,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/digitallogic/adl855pc/Options.lb +++ coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -113,11 +112,4 @@ default CONFIG_ROM_PAYLOAD = 1 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC="gcc" - - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c =================================================================== --- coreboot-v2.orig/src/mainboard/digitallogic/msm586seg/mainboard.c +++ coreboot-v2/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -35,9 +35,6 @@ static void irqdump() - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 */ static void enable_dev(struct device *dev) { -#if !CONFIG_CBFS - extern unsigned char *rom_start, *rom_end; -#endif volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT; @@ -136,14 +133,6 @@ static void enable_dev(struct device *de /* follow fuctory here */ mmcr->dmacontrol.extchanmapa = 0x3210; -#if !CONFIG_CBFS - /* hack for IDIOTIC need to fix rom_start */ - printk_err("Patching rom_start due to sc520 limits\n"); - rom_start = 0x2000000 + 0x40000; - rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; -#endif - - } struct chip_operations mainboard_ops = { CHIP_NAME("DIGITAL-LOGIC MSM586SEG Mainboard") Index: coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/digitallogic/msm586seg/Options.lb +++ coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -121,11 +120,4 @@ default CONFIG_ROM_PAYLOAD = 1 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC="gcc" - - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/digitallogic/msm800sev/Options.lb +++ coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -180,10 +179,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/eaglelion/5bcm/Options.lb +++ coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -164,10 +163,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_VIDEO_MB = 0 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/embeddedplanet/ep405pc/Options.lb +++ coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -3,7 +3,6 @@ ## uses CONFIG_PCIC0_CFGADDR -uses CONFIG_CBFS uses CONFIG_ARCH_X86 uses CONFIG_PCIC0_CFGDATA uses CONFIG_ISA_IO_BASE @@ -144,9 +143,4 @@ default CONFIG_ROMSTART=0xfff03000 default CONFIG_RAMBASE=0x00100000 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/emulation/qemu-x86/Options.lb +++ coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb @@ -48,13 +48,11 @@ uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CBFS default CONFIG_CONSOLE_SERIAL8250=1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 -default CONFIG_CBFS=1 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE = 256*1024 Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -22,7 +22,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -351,9 +350,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga-6bxc/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -359,10 +358,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -# -# CBFS -# -# -default CONFIG_CBFS=1 ### End Options.lb end Index: coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/hp/dl145_g3/Options.lb +++ coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb @@ -84,7 +84,6 @@ uses CONFIG_PCI_ROM_RUN uses CONFIG_HW_MEM_HOLE_SIZEK uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_CBFS uses CONFIG_HT_CHAIN_UNITID_BASE uses CONFIG_HT_CHAIN_END_UNITID_BASE @@ -327,9 +326,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -## -## CBFS -default CONFIG_CBFS=1 - ### End Options.lb end Index: coreboot-v2/src/mainboard/ibm/e325/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/ibm/e325/Options.lb +++ coreboot-v2/src/mainboard/ibm/e325/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -221,9 +220,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/ibm/e326/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/ibm/e326/Options.lb +++ coreboot-v2/src/mainboard/ibm/e326/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -227,9 +226,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iei/juki-511p/Options.lb +++ coreboot-v2/src/mainboard/iei/juki-511p/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -145,10 +144,4 @@ default HOSTCC="gcc" default CONFIG_VIDEO_MB = 0 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iei/nova4899r/Options.lb +++ coreboot-v2/src/mainboard/iei/nova4899r/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -172,10 +171,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_VIDEO_MB = 0 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iei/pcisa-lx-800-r10/Options.lb +++ coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -106,10 +105,4 @@ default CONFIG_TTYS0_LCS = 0x3 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/intel/eagleheights/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/intel/eagleheights/Options.lb +++ coreboot-v2/src/mainboard/intel/eagleheights/Options.lb @@ -70,7 +70,6 @@ uses CONFIG_HAVE_SMI_HANDLER uses CONFIG_PCIE_CONFIGSPACE_HOLE uses CONFIG_MMCONF_SUPPORT uses CONFIG_MMCONF_BASE_ADDRESS -uses CONFIG_CBFS # uses CONFIG_MAINBOARD uses CONFIG_MAINBOARD_PART_NUMBER @@ -322,10 +321,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL= ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -# -# CBFS -# -default CONFIG_CBFS=1 - ### End Options.lb end Index: coreboot-v2/src/mainboard/intel/jarrell/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/intel/jarrell/Options.lb +++ coreboot-v2/src/mainboard/intel/jarrell/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -242,9 +241,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/intel/mtarvon/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/intel/mtarvon/Options.lb +++ coreboot-v2/src/mainboard/intel/mtarvon/Options.lb @@ -18,7 +18,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -225,9 +224,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/intel/truxton/Options.lb +++ coreboot-v2/src/mainboard/intel/truxton/Options.lb @@ -18,7 +18,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -226,10 +225,4 @@ default CONFIG_MAINBOARD_POWER_ON_AFTER_ ### End Options.lb - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/intel/xe7501devkit/Options.lb +++ coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME uses CONFIG_HAVE_PIRQ_TABLE @@ -240,9 +239,4 @@ default CONFIG_DEBUG=1 # default CONFIG_CPU_OPT="-g" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Options.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -326,9 +325,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8s2/Options.lb +++ coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,9 +227,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/iwill/dk8x/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8x/Options.lb +++ coreboot-v2/src/mainboard/iwill/dk8x/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -227,9 +226,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/jetway/j7f24/Options.lb +++ coreboot-v2/src/mainboard/jetway/j7f24/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -104,10 +103,4 @@ default HOSTCC = "gcc" ## default CONFIG_MAX_PCI_BUSES = 3 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/kontron/986lcd-m/Options.lb +++ coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb @@ -71,7 +71,6 @@ uses CONFIG_PCIE_CONFIGSPACE_HOLE uses CONFIG_MMCONF_SUPPORT uses CONFIG_MMCONF_BASE_ADDRESS uses CONFIG_GFXUMA -uses CONFIG_CBFS # uses CONFIG_MAINBOARD @@ -327,10 +326,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" -# -# CBFS -# -default CONFIG_CBFS=1 - ### End Options.lb end Index: coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/lippert/frontrunner/Options.lb +++ coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -159,10 +158,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/lippert/roadrunner-lx/Options.lb +++ coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb @@ -21,7 +21,6 @@ ## Based on Options.lb from AMD's DB800 mainboard. uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -211,9 +210,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/lippert/spacerunner-lx/Options.lb +++ coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb @@ -21,7 +21,6 @@ ## Based on Options.lb from AMD's DB800 mainboard. uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -211,9 +210,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/mitac/6513wu/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/mitac/6513wu/Options.lb +++ coreboot-v2/src/mainboard/mitac/6513wu/Options.lb @@ -19,7 +19,6 @@ ## uses CC -uses CONFIG_CBFS uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_VGA @@ -78,7 +77,6 @@ default CONFIG_ROM_IMAGE_SIZE = 128 * 10 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CBFS=1 # RAM layout default CONFIG_RAMBASE = 0x00004000 Index: coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/motorola/sandpoint/Options.lb +++ coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_SANDPOINT_ALTIMUS -uses CONFIG_CBFS uses CONFIG_ARCH_X86 uses CONFIG_SANDPOINT_TALUS uses CONFIG_SANDPOINT_UNITY @@ -126,9 +125,4 @@ default CONFIG_RAMSTART=0x00100000 default CONFIG_SANDPOINT_ALTIMUS=1 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb +++ coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb @@ -1,6 +1,5 @@ uses CONFIG_ARCH_X86 uses CONFIG_ISA_IO_BASE -uses CONFIG_CBFS uses CONFIG_ISA_MEM_BASE uses CONFIG_PCIC0_CFGADDR uses CONFIG_PCIC0_CFGDATA @@ -121,9 +120,4 @@ default CONFIG_RAMBASE=0x00100000 default CONFIG_RAMSTART=0x00100000 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/msi/ms6119/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms6119/Options.lb +++ coreboot-v2/src/mainboard/msi/ms6119/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms6147/Options.lb +++ coreboot-v2/src/mainboard/msi/ms6147/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,9 +96,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/msi/ms6178/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms6178/Options.lb +++ coreboot-v2/src/mainboard/msi/ms6178/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -97,7 +96,6 @@ default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS = 1 default CONFIG_HAVE_HIGH_TABLES = 1 default CONFIG_VIDEO_MB = 1 end Index: coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Options.lb @@ -21,7 +21,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_USE_FAILOVER_IMAGE @@ -320,9 +319,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_USE_FAILOVER_IMAGE @@ -186,9 +185,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms9185/Options.lb +++ coreboot-v2/src/mainboard/msi/ms9185/Options.lb @@ -23,7 +23,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -327,9 +326,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms9282/Options.lb +++ coreboot-v2/src/mainboard/msi/ms9282/Options.lb @@ -23,7 +23,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -307,9 +306,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/nec/powermate2000/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nec/powermate2000/Options.lb +++ coreboot-v2/src/mainboard/nec/powermate2000/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -96,9 +95,4 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WI default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/newisys/khepri/Options.lb +++ coreboot-v2/src/mainboard/newisys/khepri/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -243,9 +242,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Options.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -349,9 +348,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/olpc/btest/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/olpc/btest/Options.lb +++ coreboot-v2/src/mainboard/olpc/btest/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -159,11 +158,3 @@ default CONFIG_TTYS0_LCS=0x3 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - - -# -# CBFS -# -# -default CONFIG_CBFS=1 -end Index: coreboot-v2/src/mainboard/olpc/rev_a/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/olpc/rev_a/Options.lb +++ coreboot-v2/src/mainboard/olpc/rev_a/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -159,11 +158,3 @@ default CONFIG_TTYS0_LCS=0x3 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - - -# -# CBFS -# -# -default CONFIG_CBFS=1 -end Index: coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/pcengines/alix1c/Options.lb +++ coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -198,10 +197,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/rca/rm4100/Options.lb +++ coreboot-v2/src/mainboard/rca/rm4100/Options.lb @@ -19,7 +19,6 @@ ## uses CC -uses CONFIG_CBFS uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA @@ -96,9 +95,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_MAINBOARD_VENDOR = "RCA" default CONFIG_MAINBOARD_PART_NUMBER = "RM4100" -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb +++ coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -96,5 +95,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/sunw/ultra40/Options.lb +++ coreboot-v2/src/mainboard/sunw/ultra40/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -276,9 +275,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -351,9 +350,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -348,11 +347,5 @@ default CONFIG_USE_FAILOVER_IMAGE=0 default CONFIG_USE_FALLBACK_IMAGE=0 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -# -# CBFS -# -# -default CONFIG_CBFS=1 - ### End Options.lb end Index: coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/x6dai_g/Options.lb +++ coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,10 +227,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/x6dhe_g/Options.lb +++ coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,10 +227,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/x6dhe_g2/Options.lb +++ coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,10 +227,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/x6dhr_ig/Options.lb +++ coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,9 +227,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/x6dhr_ig2/Options.lb +++ coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -228,9 +227,4 @@ default CONFIG_CONSOLE_BTEXT=0 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/technexion/tim8690/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/technexion/tim8690/Options.lb +++ coreboot-v2/src/mainboard/technexion/tim8690/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME Index: coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c =================================================================== --- coreboot-v2.orig/src/mainboard/technologic/ts5300/mainboard.c +++ coreboot-v2/src/mainboard/technologic/ts5300/mainboard.c @@ -35,9 +35,6 @@ static void irqdump() - set ADDDECTL (now done in raminit.c in cpu/amd/sc520 */ static void enable_dev(struct device *dev) { -#if !CONFIG_CBFS - extern unsigned char *rom_start, *rom_end; -#endif volatile struct mmcrpic *pic = MMCRPIC; volatile struct mmcr *mmcr = MMCRDEFAULT; @@ -141,13 +138,6 @@ static void enable_dev(struct device *de mmcr->dmacontrol.extchanmapa = 0xf210; mmcr->dmacontrol.extchanmapb = 0xffff; -#if !CONFIG_CBFS - /* hack for IDIOTIC need to fix rom_start */ - printk_err("Patching rom_start due to sc520 limits\n"); - rom_start = 0x09400000 + 0xe0000; - rom_end = rom_start + CONFIG_PAYLOAD_SIZE - 1; -#endif - printk_err("TS5300 EXIT %s\n", __func__); } Index: coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/technologic/ts5300/Options.lb +++ coreboot-v2/src/mainboard/technologic/ts5300/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -136,9 +135,4 @@ default CONFIG_ROM_PAYLOAD = 1 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC="gcc" -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/televideo/tc7020/Options.lb +++ coreboot-v2/src/mainboard/televideo/tc7020/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -104,9 +103,4 @@ default CONFIG_TTYS0_LCS = 0x3 # 8n1 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/thomson/ip1000/Options.lb +++ coreboot-v2/src/mainboard/thomson/ip1000/Options.lb @@ -19,7 +19,6 @@ ## uses CC -uses CONFIG_CBFS uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA @@ -96,9 +95,4 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_MAINBOARD_VENDOR = "THOMSON" default CONFIG_MAINBOARD_PART_NUMBER = "IP1000" -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/totalimpact/briq/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/totalimpact/briq/Options.lb +++ coreboot-v2/src/mainboard/totalimpact/briq/Options.lb @@ -3,7 +3,6 @@ ## uses CONFIG_TTYS0_DIV -uses CONFIG_CBFS uses CONFIG_ARCH_X86 uses CONFIG_TTYS0_BASE uses CONFIG_BRIQ_750FX @@ -128,9 +127,4 @@ default CONFIG_BRIQ_750FX=1 #default CONFIG_BRIQ_7400=1 ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s1846/Options.lb +++ coreboot-v2/src/mainboard/tyan/s1846/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -98,9 +97,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2735/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2735/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -256,9 +255,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2850/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2850/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -244,9 +243,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2875/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2875/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -245,9 +244,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2880/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2880/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -244,9 +243,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2881/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2881/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -261,9 +260,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2882/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2882/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -244,9 +243,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2885/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2885/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -271,9 +270,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2891/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2891/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -300,9 +299,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2892/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2892/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -288,9 +287,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -307,9 +306,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912_fam10/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -360,9 +359,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -351,9 +350,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s4880/Options.lb +++ coreboot-v2/src/mainboard/tyan/s4880/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -253,9 +252,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s4882/Options.lb +++ coreboot-v2/src/mainboard/tyan/s4882/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -252,9 +251,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/epia-cn/Options.lb +++ coreboot-v2/src/mainboard/via/epia-cn/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -104,10 +103,4 @@ default HOSTCC = "gcc" ## default CONFIG_MAX_PCI_BUSES = 3 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/epia-m/Options.lb +++ coreboot-v2/src/mainboard/via/epia-m/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -143,10 +142,4 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 default CONFIG_CONSOLE_SERIAL8250=1 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/epia-m700/Options.lb +++ coreboot-v2/src/mainboard/via/epia-m700/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT @@ -137,7 +136,6 @@ default CC = "$(CONFIG_CROSS_COMPILE)gcc default HOSTCC = "gcc" default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CBFS=1 ## ## Set this to the max PCI bus number you would ever use for PCI config I/O. Index: coreboot-v2/src/mainboard/via/epia-n/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/epia-n/Options.lb +++ coreboot-v2/src/mainboard/via/epia-n/Options.lb @@ -20,7 +20,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_FAILOVER_BOOT uses CONFIG_USE_FAILOVER_IMAGE @@ -118,10 +117,4 @@ default HOSTCC = "gcc" ## default CONFIG_MAX_PCI_BUSES = 3 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/epia/Options.lb +++ coreboot-v2/src/mainboard/via/epia/Options.lb @@ -1,5 +1,4 @@ uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CBFS uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_TTYS0_BAUD @@ -141,10 +140,4 @@ default CC="$(CONFIG_CROSS_COMPILE)gcc - default HOSTCC="gcc" - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/via/pc2500e/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/pc2500e/Options.lb +++ coreboot-v2/src/mainboard/via/pc2500e/Options.lb @@ -19,7 +19,6 @@ ## uses CONFIG_SMP -uses CONFIG_CBFS uses CONFIG_HAVE_MP_TABLE uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE @@ -112,10 +111,4 @@ default CONFIG_TTYS0_LCS = 0x3 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 - -# -# CBFS -# -# -default CONFIG_CBFS=1 end Index: coreboot-v2/src/mainboard/via/vt8454c/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/via/vt8454c/Options.lb +++ coreboot-v2/src/mainboard/via/vt8454c/Options.lb @@ -55,7 +55,6 @@ uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE -uses CONFIG_CBFS # compiler specifics uses CONFIG_CROSS_COMPILE @@ -243,10 +242,5 @@ default CONFIG_DEFAULT_CONSOLE_LOGLEVEL ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5 -# -# CBFS -# -default CONFIG_CBFS=1 - end Index: coreboot-v2/util/abuild/abuild =================================================================== --- coreboot-v2.orig/util/abuild/abuild +++ coreboot-v2/util/abuild/abuild @@ -176,20 +176,12 @@ EOF cat <<EOF romimage "normal" option CONFIG_USE_FALLBACK_IMAGE=0 -if CONFIG_CBFS -else - option CONFIG_ROM_IMAGE_SIZE=0x17000 -end option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 -if CONFIG_CBFS -else - option CONFIG_ROM_IMAGE_SIZE=0x17000 -end option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Index: coreboot-v2/util/newconfig/config.g =================================================================== --- coreboot-v2.orig/util/newconfig/config.g +++ coreboot-v2/util/newconfig/config.g @@ -2247,9 +2247,6 @@ def writemakefile(path): file = safe_open(makefilepath, 'w+') writemakefileheader(file, makefilepath) - # Hack to get the necessary settings (CONFIG_CBFS): - file.write("include %s/Makefile.settings\n\n" % romimages.keys()[0]) - # main rule file.write("\nall: ") for i in buildroms: @@ -2275,9 +2272,8 @@ def writemakefile(path): file.write("base-clean:\n") file.write("\trm -f romcc*\n\n") - file.write("ifeq \"$(CONFIG_CBFS)\" \"1\"\n\n") file.write("CBFS_COMPRESS_FLAG:=\n") - file.write("ifeq \"$(CONFIG_COMPRESSED_PAYLOAD_LZMA)\" \"1\"\nCBFS_COMPRESS_FLAG:=l\nendif\n\n") + file.write("ifeq \"$(CONFIG_COMPRESSED_PAYLOAD_LZMA)\" \"1\"\nCBFS_COMPRESS_FLAG:=l\n\n") for i in buildroms: file.write("%s: cbfstool" %(i.name)) Index: coreboot-v2/NEWS =================================================================== --- coreboot-v2.orig/NEWS +++ coreboot-v2/NEWS @@ -1,68 +1,12 @@ -- 2.0.0 - - this NEWS file is neglected in favor of the svn commit logs. - See http://tracker.coreboot.org/ -- 1.1.8 - - Store everything in arch -- 1.1.7 - - The configuration language has been cleaned up. No more link keyword. - - Everything is now in the device tree. - - The static and dynamic device trees have been unified - - Support for setting the pci subsystem vendor and pci subsystem device has been added. - - 64bit resource support - - Generic smbus support -- 1.1.6 - - pnp/superio devices are now handled cleanly with very little code - - Initial support for finding x86 BIST errors - - static resource assignments can now be specified in Config.lb - - special VGA I/O decode now should work - - added generic PCI error reporting enables - - build_opt_tbl now generates a header that allows cmos settings to - be read from romcc compiled code. - - split IORESOURCE_SET into IORESOURCE_ASSIGNED and IORESOURCE_STORED - - romcc now gracesfully handles function pointers instead of dying mysteriously - - First regression test in amdk8/raminit_test -- 1.1.5 - - O2, enums, and switch statements work in romcc - - Support for compiling romcc on non x86 platforms - - new romc options -msse and -mmmx for specifying extra registers to use - - Bug fixes to device the device disable/enable framework and an amd8111 implementation - - Move the link specification to the chip specification instead of the path - - Allow specifying devices with internal bridges. - - Initial via epia support - - Opteron errata fixes -- 1.1.4 - Major restructuring of hypertransport handling. - Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically - Updates to hard_reset handling when resetting because of the need to change hypertransport link - speeds and widths. - (a) No longer assume the boot is good just because we get to a hard reset point. - (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the - boot counter. - Updates to arima/hdama mptable so it tracks the new bus numbers -- 1.1.3 - Major update of the dyanmic device tree to so it can handle - * subtractive resources - * merging with the static device tree - * more device types than just pci -- 1.1.2 - Add back in the hard_reset method from freebios1 this allows generic - code to reset the box. - Update the hypertransport setup code to automatically optimize - hypertransport link widths and frequencies, and to call hard_reset - if necessary for the changes to go into effect. -- 1.1.1 - Updates to the new configuration system so it works more reliably - Removed a bunch of unused configuration variables - Removed a bunch of unused assembly code -- 1.1.0 - A whole bunch of random ppc and opteron work we never put a good label on -- 1.1.0 -Intial development release of LinuxBIOS. -Everything is thrown overboard and will be reincluded as necessary so we can -get rid of the legacy baggage. Since LinuxBIOS was started we have developed -some better techniques for some things, but we still hang on to the old ways -because some ports that we want not to break depend on them. So we preserve -them by preserve the 1.0.x series and keeping only the best practices for -the 1.1.x series. When there is a stable port this code base will -become LinuxBIOS 2.0.x and the core will become frozen. +coreboot version 2.1 - 2009-mm-dd +--------------------------------- +This version features the removal of the old style ROM image layout in favor of +CBFS. CONFIG_CBFS was removed as there is no way to unselect it. +Issues: +- cpu/amd/model_lx contains some untested changes in the coreboot_ram + loading stage +- The coreboot_ram loader sets up its own stack at 0x4000000. This has two + implications: + 1. This memory should probably stay alive (eg. resume from suspend) + 2. There might be collisions on SMP (eg. when loading coreboot_apc)

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build service results for r4539
by coreboot information 12 Aug '09

12 Aug '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4539 to the coreboot repository. This caused the following changes: Change Log: Remove duplicate file, adjust Makefile to use the original copy. Keeping identical files around will only bite us eventually, when they get out of sync. See coreboot-v2 history for examples. Trivial and build tested. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=atc-6220&vendo… Compilation of a-trend:atc-6240 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=be6-ii_v2_0&ve… Compilation of asus:p2b is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=p2b&vendor=asu… Compilation of asus:p2b-d is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=p2b-d&vendor=a… Compilation of asus:p2b-ds is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=p2b-ds&vendor=… Compilation of asus:p2b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=p2b-f&vendor=a… Compilation of asus:p3b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=pt-6ibd&vendor… Compilation of biostar:m6tba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=deskpro_en_sff… Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=ep405pc&vendor… Compilation of gigabyte:ga-6bxc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=ga-6bxc&vendor… Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=nova4899r&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=sandpointx3_al… Compilation of msi:ms6119 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=ms6119&vendor=… Compilation of msi:ms6147 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=ms6147&vendor=… Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=sy-6ba-plus-ii… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=briq&vendor=to… Compilation of tyan:s1846 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=s1846&vendor=t… Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4539&device=epia-m&vendor=… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot August 2009