Hi all,
I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. I am not familiar with the PCI subsystem and the procedures of coreboot regarding this matter, but when scanning through the code, I do not even see why the last line is printed out twice whereas the procedure including the printout only gets called once with the specified parameters. Does anyone have an idea where I could start searching for a possible solution to my problem.
Thanks for the help in advance,
Maximilian Thuermer
coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting...
BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 reexx other core - nodeid: 01 cores: cco0coorr3e -: x::s t: a r- ----t--e-d - { { a { p A A aPPApIIPCiCIIcICiDDI d D =:= = F000o12 u 3 NnNONdODO DDE3EIEI IDDD w = =or =x :
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Wait for AP stage 1: ap_apicid = 3 readback = 3010701 common_fid(packed) = 10700 common_fid = 10700 FID Change Node:00, F3xD4: c3310f27 FID Change Node:01, F3xD4: c3310f27 End FIDVIDMSR 0xc0010071 0x00800003 0x30036040 mcp55_num:01 ...WARM RESET...
coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting...
BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 Start other core - nodeid: 01 cores: ccc0o3oorrr x:-xxxs::: ta r-t-----e-d -- { a{ { p AaAPApPIPIiCICcICiIDIDd D= : = = F0o300 uNn12dO DNNE3OOIDD DwEEo IIr=DD k - - ::-
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tFmmmiciia! t oocc cIchDhcccrV!rrp! ScD fo oooeccdpddptMeASueeu:S:MRS: e e D rM0rtrteAeSxeAvMvMvRc0 D D iM0iMidSddS1 R R0 nd nn 0oo7oot1ttn ef0 fFodxoI !0d.i. t un0inE8ndned. gcnoodpd 0 C0S_SikfkSnP0iU3iikiit dppp_0Vvppifxeiipnini3rdgs_ngd0 v0 isg tmi3moinmaid60_c igcre4srucrno20toc aokc oao !:t e2dweieen c E an pipadppdoatrt:ai Fcc c tc0Iihnh!o!h3Dd
I s upuSoRcucppM1pcupS 1SRSR Ser eStet0txeAtAdcMAMD!0DMDM 0MMS 0 0R F I7X1M E0F!x d0dI oC0oXM8Pnne0UeE! 0V kssoe0iinr3PnUiis 0ttiVox__fen3fiir 0d0dsuv0vinik3iondn0d_ _o0acuawpn np(( :epp ottrmaca wngpgn oe5e1ot15)_r ) n s aaunupppmotipi: 0cocis1irdtud te do!8cr 11
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te r suinoknno uwnn knoor wnn otor sunpotpo rsutpedpo!r n d d! o Fe IXinMEi!t_ fCPidUv Vied_rssitaogn e2u nkapniowcnid o:r 0 2no t supported! done init_fidvid_ap(stage1) apicid: 41 FIDVID on AP: 41 fill_mem_ctrl() enable_smbus() raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 00000000 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000050 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000051 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000052 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000053 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00008003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00008000 AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000001 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000054 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000055 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000056 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000057 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 0001a003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 0001a000 AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000002 mctAutoInitMCT_D: mct_init Node 00000003 mctAutoInitMCT_D: mct_init Node 00000004 mctAutoInitMCT_D: mct_init Node 00000005 mctAutoInitMCT_D: mct_init Node 00000006 mctAutoInitMCT_D: mct_init Node 00000007 mctAutoInitMCT_D: SyncDCTsReady_D mct_SyncDCTsReady: Node 00000000 mct_SyncDCTsReady: DramEnabled mct_SyncDCTsReady: Node 00000001 mct_SyncDCTsReady: DramEnabled mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: ffffff BottomIO: e00000 Node: 01 base: 1200000 limit: 21fffff BottomIO: e00000 Copy dram map from Node 0 to Node 01 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:00e00000 CPUMemTyping: Bottom32bIO:00e00000 CPUMemTyping: Bottom40bIO:02200000 mctAutoInitMCT_D: DQSTiming_D DQSTiming_D: mct_BeforeDQSTrain_D: vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: step 2a vErrara350: step 2b vErrara350: step 3 vErrara350: step 4 vErrara350: step 4b vErrara350: step 5 DQSTiming_D: TrainReceiverEn_D FirstPass: TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001107 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001007 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done DQSTiming_D: mct_TrainDQSPos_D TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done DQSTiming_D: mctSetEccDQSRcvrEn_D DQSTiming_D: TrainMaxReadLatency_D DQSTiming_D: mct_EndDQSTraining_D DQSTiming_D: MCTMemClr_D mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 00001107 InterleaveNodes_D: ErrStatus 00000010 InterleaveNodes_D: ErrCode 00000000 InterleaveNodes_D: Done InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002003 InterleaveChannels_D: Node 00000000 InterleaveChannels_D: Status 00001107 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00012584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002002 InterleaveChannels_D: Node 00000001 InterleaveChannels_D: Status 00001007 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000002 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000003 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000004 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000005 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000006 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000007 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECCInit 0 ECC enabled on node: 00000000 ECC enabled on node: 00000001 ECCInit 1 ECCInit 2 ECCInit 3 mctAutoInitMCT_D: MCTMemClr_D mct_FinalMCT_D: Clr Cl, Wb All Done raminit_amdmct end:
*** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf18 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing image to RAM. Jumping to image. coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 11:11:04 CEST 2009 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.0 links increase to 8 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:19.0 links increase to 8 PCI: 00:19.3 siblings=3 CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0369] enabled next_unitid: 0011 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [10de/0369] enabled PCI: 00:02.0 [10de/0364] enabled PCI: 00:02.1 [10de/0368] enabled PCI: 00:02.2 [10de/036a] enabled PCI: 00:02.3 [10de/036b] enabled PCI: 00:03.0 [10de/036c] enabled PCI: 00:03.1 [10de/036d] enabled PCI: 00:05.0 [10de/036e] enabled PCI: 00:06.0 [10de/037f] enabled PCI: 00:06.1 [10de/037f] enabled PCI: 00:06.2 [10de/037f] enabled PCI: 00:07.0 [10de/0370] enabled PCI: 00:07.1 [10de/0371] disabled PCI: 00:09.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0373] enabled PCI: 00:0b.0 [10de/0376] enabled PCI: 00:0e.0 [10de/0378] enabled PCI: 00:10.0 [10de/0377] enabled PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled smbus: PCI: 00:02.1[0]->I2C: 01:50 enabled smbus: PCI: 00:02.1[0]->I2C: 01:51 enabled smbus: PCI: 00:02.1[0]->I2C: 01:52 enabled smbus: PCI: 00:02.1[0]->I2C: 01:53 enabled smbus: PCI: 00:02.1[0]->I2C: 01:54 enabled smbus: PCI: 00:02.1[0]->I2C: 01:55 enabled smbus: PCI: 00:02.1[0]->I2C: 01:56 enabled smbus: PCI: 00:02.1[0]->I2C: 01:57 enabled smbus: PCI: 00:02.1[1]->I2C: 02:51 enabled PCI: pci_scan_bus for bus 01 PCI: 01:04.0 [1002/515e] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Maximilian Thuermer Sent: Tuesday, August 11, 2009 8:13 AM To: coreboot@coreboot.org Subject: [coreboot] Tyan S2912[Fam10] HTX problem
Hi all,
I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. I am not familiar with the PCI subsystem and the procedures of coreboot regarding this matter, but when scanning through the code, I do not even see why the last line is printed out twice whereas the procedure including the printout only gets called once with the specified parameters. Does anyone have an idea where I could start searching for a possible solution to my problem.
I would print out the path to each bridge in the scan to see where it's getting stuck. You can get that with dev_path(bus->dev).
It looks pretty normal up to that point. It looks like it found your chipset, 2 cpus, and a graphics card before it died.
If that doesn't help you track it down, an lspci would be helpful with the information of which bridge it gets stuck scanning. The values of the Configuration Map registers 0xE0-EC might also help you track down where the PCI requests are being routed.
PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004
I can't tell why it's printed twice either.
Good luck, Myles
It seems that the chipset is nVidia nVidia Corporation MCP55 .
Date: Tue, 11 Aug 2009 16:12:39 +0200 From: Maximilian.Thuermer@ziti.uni-heidelberg.de To: coreboot@coreboot.org Subject: [coreboot] Tyan S2912[Fam10] HTX problem
Hi all,
I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. I am not familiar with the PCI subsystem and the procedures of coreboot regarding this matter, but when scanning through the code, I do not even see why the last line is printed out twice whereas the procedure including the printout only gets called once with the specified parameters. Does anyone have an idea where I could start searching for a possible solution to my problem.
Thanks for the help in advance,
Maximilian Thuermer
coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting...
BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 reexx other core - nodeid: 01 cores: cco0coorr3e -: x::s t: a r- ----t--e-d - { { a { p A A aPPApIIPCiCIIcICiDDI d D =:= = F000o12 u 3 NnNONdODO DDE3EIEI IDDD w = =or =x :
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Wait for AP stage 1: ap_apicid = 3 readback = 3010701 common_fid(packed) = 10700 common_fid = 10700 FID Change Node:00, F3xD4: c3310f27 FID Change Node:01, F3xD4: c3310f27 End FIDVIDMSR 0xc0010071 0x00800003 0x30036040 mcp55_num:01 ...WARM RESET...
coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009 starting...
BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: rev id not found. Skipping microcode patch! cpuSetAMDMSR done Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff Exit amd_ht_init() cpuSetAMDPCI 00 On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e cpuSetAMDPCI 01 On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f27 F3xD8: 03000916 F3xDC: 00005334 setup_remote_node: 01 done Start node 01 done. Wait all core0s started Core0 started on node: 01 Wait all core0s started done start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 init node: 01 cores: 03 Start other core - nodeid: 01 cores: ccc0o3oorrr x:-xxxs::: ta r-t-----e-d -- { a{ { p AaAPApPIPIiCICcICiIDIDd D= : = = F0o300 uNn12dO DNNE3OOIDD DwEEo IIr=DD k -
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te r suinoknno uwnn knoor wnn otor sunpotpo rsutpedpo!r n d d! o Fe IXinMEi!t_ fCPidUv Vied_rssitaogn e2u nkapniowcnid o:r 0 2no t supported! done init_fidvid_ap(stage1) apicid: 41 FIDVID on AP: 41 fill_mem_ctrl() enable_smbus() raminit_amdmct() raminit_amdmct begin: mctAutoInitMCT_D: mct_init Node 00000000 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000050 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000051 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000052 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000053 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 00008003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 00008000 AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 00000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000001 mctAutoInitMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: Set Cl, Wb mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT mct_initDCT: DCTInit_D 0 DIMMPresence: i=00000000 DIMMPresence: smbaddr=00000054 DIMMPresence: i=00000001 DIMMPresence: smbaddr=00000055 DIMMPresence: i=00000002 DIMMPresence: smbaddr=00000056 DIMMPresence: i=00000003 DIMMPresence: smbaddr=00000057 DIMMPresence: i=00000004 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000005 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000006 DIMMPresence: smbaddr=00000000 DIMMPresence: i=00000007 DIMMPresence: smbaddr=00000000 DIMMPresence: DIMMValid=0000000c DIMMPresence: DIMMPresent=0000000c DIMMPresence: RegDIMMPresent=0000000c DIMMPresence: DimmECCPresent=0000000c DIMMPresence: DimmPARPresent=0000000c DIMMPresence: Dimmx4Present=00000000 DIMMPresence: Dimmx8Present=0000000c DIMMPresence: Dimmx16Present=00000000 DIMMPresence: DimmPlPresent=0000000c DIMMPresence: DimmDRPresent=0000000c DIMMPresence: DimmQRPresent=00000000 DIMMPresence: DATAload[0]=00000002 DIMMPresence: MAload[0]=00000010 DIMMPresence: MAdimms[0]=00000001 DIMMPresence: DATAload[1]=00000002 DIMMPresence: MAload[1]=00000010 DIMMPresence: MAdimms[1]=00000001 DIMMPresence: Status 00001007 DIMMPresence: ErrStatus 00000000 DIMMPresence: ErrCode 00000000 DIMMPresence: Done DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done SPDGetTCL_D: DIMMCASL 00000003 SPDGetTCL_D: DIMMAutoSpeed 00000003 SPDGetTCL_D: Status 00001007 SPDGetTCL_D: ErrStatus 00000010 SPDGetTCL_D: ErrCode 00000000 SPDGetTCL_D: Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000000 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch DCT0 and DCT1: DRAM Controller Select Low Register = 0001a003 AfterStitch DCT0 and DCT1: DRAM Controller Select High Register = 0001a000 AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 007fffff StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000000 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mct_initDCT: DCTInit_D 1 DCTInit_D: mct_DIMMPresence Done SPDCalcWidth: Status 00001007 SPDCalcWidth: ErrStatus 00000010 SPDCalcWidth: ErrCode 00000000 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming: DramTimingLo 0069ca24 AutoCycTiming: DramTimingHi 01020300 AutoCycTiming: Status 00001007 AutoCycTiming: ErrStatus 00000010 AutoCycTiming: ErrCode 00000000 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done AutoConfig_D: DCT: 00000001 SPDSetBanks: Status 00001007 SPDSetBanks: ErrStatus 00000010 SPDSetBanks: ErrCode 00000000 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 01000000 mct_AfterStitchMemory: pDCTstat->NodeSysLimit 00fffffe StitchMemory: Status 00001007 StitchMemory: ErrStatus 00000010 StitchMemory: ErrCode 00000000 StitchMemory: Done InterleaveBanks_D: Banks Interleaved InterleaveBanks_D: Status 00001007 InterleaveBanks_D: ErrStatus 00000010 InterleaveBanks_D: ErrCode 00000000 InterleaveBanks_D: Done DramTimingLo: val=00000008 DramTimingLo: val=00000008 DramTimingLo: val=00000006 DramTimingLo: val=00000004 DramTimingLo: val=00000002 DramTimingLo: val=00000000 DramTimingLo: val=00000008 DramTimingLo: val=00000008 AutoConfig_D: DramControl: 00000005 AutoConfig_D: DramTimingLo: ef69ca24 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000002 AutoConfig_D: DramConfigLo: 00080110 AutoConfig_D: DramConfigHi: 6f48800a AutoConfig: Status 00001007 AutoConfig: ErrStatus 00000010 AutoConfig: ErrCode 00000000 AutoConfig: Done DCTInit_D: AutoConfig_D Done dct: 00000001 Speed: 00000003 CH_ODC_CTL: 20111222 CH_ADDR_TMG: 00000000 DCTInit_D: PlatformSpec_D Done DCTInit_D: StartupDCT_D StartupDCT_D: MemClkFreqVal StartupDCT_D: DqsRcvEnTrain set StartupDCT_D: DramInit mctAutoInitMCT_D: mct_init Node 00000002 mctAutoInitMCT_D: mct_init Node 00000003 mctAutoInitMCT_D: mct_init Node 00000004 mctAutoInitMCT_D: mct_init Node 00000005 mctAutoInitMCT_D: mct_init Node 00000006 mctAutoInitMCT_D: mct_init Node 00000007 mctAutoInitMCT_D: SyncDCTsReady_D mct_SyncDCTsReady: Node 00000000 mct_SyncDCTsReady: DramEnabled mct_SyncDCTsReady: Node 00000001 mct_SyncDCTsReady: DramEnabled mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: ffffff BottomIO: e00000 Node: 01 base: 1200000 limit: 21fffff BottomIO: e00000 Copy dram map from Node 0 to Node 01 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:00e00000 CPUMemTyping: Bottom32bIO:00e00000 CPUMemTyping: Bottom40bIO:02200000 mctAutoInitMCT_D: DQSTiming_D DQSTiming_D: mct_BeforeDQSTrain_D: vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: dummy read vErrara350: step 2a vErrara350: step 2b vErrara350: step 3 vErrara350: step 4 vErrara350: step 4b vErrara350: step 5 DQSTiming_D: TrainReceiverEn_D FirstPass: TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001107 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done TrainRcvrEn: 1 TrainRcvrEn: 2 TrainRcvrEn: 3 TrainRcvrEn: 4 Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D Rank not enabled_D TrainRcvrEn: mct_DisableDQSRcvEn_D TrainRcvrEn: Status 00001007 TrainRcvrEn: ErrStatus 00000010 TrainRcvrEn: ErrCode 00000000 TrainRcvrEn: Done DQSTiming_D: mct_TrainDQSPos_D TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001107 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done TrainDQSRdWrPos: Status 00001007 TrainDQSRdWrPos: TrainErrors 00000000 TrainDQSRdWrPos: ErrStatus 00000010 TrainDQSRdWrPos: ErrCode 00000000 TrainDQSRdWrPos: Done DQSTiming_D: mctSetEccDQSRcvrEn_D DQSTiming_D: TrainMaxReadLatency_D DQSTiming_D: mct_EndDQSTraining_D DQSTiming_D: MCTMemClr_D mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 00001107 InterleaveNodes_D: ErrStatus 00000010 InterleaveNodes_D: ErrCode 00000000 InterleaveNodes_D: Done InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00000584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002003 InterleaveChannels_D: Node 00000000 InterleaveChannels_D: Status 00001107 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels: F2x110 DRAM Controller Select Low Register = 00012584 InterleaveChannels: F1xF0 DRAM Hole Address Register = e0002002 InterleaveChannels_D: Node 00000001 InterleaveChannels_D: Status 00001007 InterleaveChannels_D: ErrStatus 00000010 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000002 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000003 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000004 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000005 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000006 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Node 00000007 InterleaveChannels_D: Status 00001000 InterleaveChannels_D: ErrStatus 00000000 InterleaveChannels_D: ErrCode 00000000 InterleaveChannels_D: Done mctAutoInitMCT_D: ECCInit_D ECCInit 0 ECC enabled on node: 00000000 ECC enabled on node: 00000001 ECCInit 1 ECCInit 2 ECCInit 3 mctAutoInitMCT_D: MCTMemClr_D mct_FinalMCT_D: Clr Cl, Wb All Done raminit_amdmct end:
*** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf18 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing image to RAM. Jumping to image. coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 11:11:04 CEST 2009 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 1, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.5: enabled 1, 4 resources PNP: 002e.6: enabled 0, 1 resources PNP: 002e.7: enabled 0, 3 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PNP: 002e.b: enabled 1, 2 resources PCI: 00:01.1: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 0 resources PCI: 00:02.1: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:05.0: enabled 1, 0 resources PCI: 00:05.1: enabled 1, 0 resources PCI: 00:05.2: enabled 1, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:04.0: enabled 1, 0 resources PCI: 00:06.1: enabled 0, 0 resources PCI: 00:08.0: enabled 1, 0 resources PCI: 00:09.0: enabled 1, 0 resources PCI: 00:0a.0: enabled 1, 0 resources PCI: 00:0b.0: enabled 0, 0 resources PCI: 00:0c.0: enabled 0, 0 resources PCI: 00:0d.0: enabled 1, 0 resources PCI: 00:0e.0: enabled 0, 0 resources PCI: 00:0f.0: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:18.4: enabled 1, 0 resources APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.0 links increase to 8 PCI: 00:18.3 siblings=3 CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:19.0 links increase to 8 PCI: 00:19.3 siblings=3 CPU: APIC: 04 enabled CPU: APIC: 05 enabled CPU: APIC: 06 enabled CPU: APIC: 07 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1200] enabled PCI: 00:18.1 [1022/1201] enabled PCI: 00:18.2 [1022/1202] enabled PCI: 00:18.3 [1022/1203] enabled PCI: 00:18.4 [1022/1204] enabled PCI: 00:19.0 [1022/1200] enabled PCI: 00:19.1 [1022/1201] enabled PCI: 00:19.2 [1022/1202] enabled PCI: 00:19.3 [1022/1203] enabled PCI: 00:19.4 [1022/1204] enabled PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0369] enabled next_unitid: 0011 PCI: pci_scan_bus for bus 00 PCI: 00:01.0 [10de/0369] enabled PCI: 00:02.0 [10de/0364] enabled PCI: 00:02.1 [10de/0368] enabled PCI: 00:02.2 [10de/036a] enabled PCI: 00:02.3 [10de/036b] enabled PCI: 00:03.0 [10de/036c] enabled PCI: 00:03.1 [10de/036d] enabled PCI: 00:05.0 [10de/036e] enabled PCI: 00:06.0 [10de/037f] enabled PCI: 00:06.1 [10de/037f] enabled PCI: 00:06.2 [10de/037f] enabled PCI: 00:07.0 [10de/0370] enabled PCI: 00:07.1 [10de/0371] disabled PCI: 00:09.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0373] enabled PCI: 00:0b.0 [10de/0376] enabled PCI: 00:0e.0 [10de/0378] enabled PCI: 00:10.0 [10de/0377] enabled PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled smbus: PCI: 00:02.1[0]->I2C: 01:50 enabled smbus: PCI: 00:02.1[0]->I2C: 01:51 enabled smbus: PCI: 00:02.1[0]->I2C: 01:52 enabled smbus: PCI: 00:02.1[0]->I2C: 01:53 enabled smbus: PCI: 00:02.1[0]->I2C: 01:54 enabled smbus: PCI: 00:02.1[0]->I2C: 01:55 enabled smbus: PCI: 00:02.1[0]->I2C: 01:56 enabled smbus: PCI: 00:02.1[0]->I2C: 01:57 enabled smbus: PCI: 00:02.1[1]->I2C: 02:51 enabled PCI: pci_scan_bus for bus 01 PCI: 01:04.0 [1002/515e] enabled PCI: pci_scan_bus returning with max=001 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004
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Hi Maximilian,
On Tue, Aug 11, 2009 at 04:12:39PM +0200, Maximilian Thuermer wrote:
I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning.
Do you mean *re*booting?
I've seen some of that.
Are you using gcc 3.x or 4.x to compile, and on 32 or 64 bit?
I've found there are issues with gcc 4.3 (even when built with the nice coresystems build-your-own-toolchain script). The most reliable compiler for coreboot in my experience is still gcc 3.4.
Also, are you sure your CONFIG_HT_* settings are correct? I found that CONFIG_HT_CHAIN_UNITID_BASE really has to be 1 to get a bootable system with mcp55 on fam10.
Thanks, Ward.
On Tue, Aug 11, 2009 at 8:16 AM, Ward Vandewegeward@gnu.org wrote:
The most reliable compiler for coreboot in my experience is still gcc 3.4.
This is really getting to be a problem. Is 4.4 any better? Any idea what could have caused the breakage? I think we can trust that gcc is not going to stop changing just for us :-)
ron
-
Maximilian Thuermer -
Myles Watson -
ron minnich -
Ward Vandewege -
Zheng Bao