coreboot July 2009

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304 discussions

[v2] r4444 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: myles Date: 2009-07-21 20:06:12 +0200 (Tue, 21 Jul 2009) New Revision: 4444 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c Log: Remove a comment that no longer applies. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-07-20 19:42:15 UTC (rev 4443) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-07-21 18:06:12 UTC (rev 4444) @@ -475,11 +475,6 @@ report_resource_stored(dev, resource, buf); } -/** - * - * I tried to reuse the resource allocation code in amdk8_set_resource() - * but it is too diffcult to deal with the resource allocation magic. - */ #if CONFIG_CONSOLE_VGA_MULTI == 1 extern device_t vga_pri; // the primary vga device, defined in device.c #endif

1 0

HIGH_TABLES support for lbtdump
by Carl-Daniel Hailfinger 21 Jul '09

21 Jul '09

util/lbtdump in the v2 tree hasn't been updated in a while and I think it may need adaptations for HIGH_TABLES and forwarding. Do we want to rename it to cbtdump or cbtabledump? Any takers? Regards, Carl-Daniel -- http://www.hailfinger.org/

3 2

[flashrom] [PATCH] external serial flasher protocol support
by Urja Rannikko 21 Jul '09

21 Jul '09

Support for an external serial flasher protocol. Supports RS-232, USB serial converters (untested) and TCP streams. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- Please commit my jedec.c readb to readn patch (or carldani's version that i've only heard of in IRC) before this - they're not dependent but without that patch this protocol is awfully slow. Also attached is a simple specification of the protocol this code implements, it hasnt changed much from my last mail, but i attach it here so it's readily available in the same mail with the implementation. I also have the implementation of this protocol on the device side for an Atmel AVR ATmega168 microcontroller, it is also included just for an idea of how i implemented the device side parser - it has GPL headers added to all files and COPYING included to make it GPLv2+ for real, but has not otherwise been looked at for release - the device it runs on is in a way very special, so i think compiling that directly would be of little use to anyone atm. -- urjaman

5 19

sony vaio pcg sr1k
by misi e 21 Jul '09

21 Jul '09

Hello, as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and wonder if I could flash it with coreboot. The box has Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset. hovewer the results of the following commands are not encouriging, please tell me if there is any chance to get coreboot working. Please find attached the outpoot of the commands. sudo superiotool -dV > siot.out lspci -tvnn > lspci.out sudo flashrom -V

5 10

[v2] r4443 - trunk/coreboot-v2/src/southbridge/via/vt8237r
by svn＠coreboot.org 20 Jul '09

20 Jul '09

Author: myles Date: 2009-07-20 21:42:15 +0200 (Mon, 20 Jul 2009) New Revision: 4443 Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: Add legacy I/O region for vt8237r southbridge. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-07-20 19:34:47 UTC (rev 4442) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-07-20 19:42:15 UTC (rev 4443) @@ -426,11 +426,15 @@ res = new_resource(dev, 0x44); res->base = VT8237R_APIC_BASE; res->size = 256; - res->limit = res->base + res->size - 1; - res->align = 8; - res->gran = 8; + res->limit = 0xffffffffUL; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /**

1 0

[v2] r4442 - in trunk/coreboot-v2/src: include/x86emu southbridge/intel/esb6300 southbridge/intel/i82801gx
by svn＠coreboot.org 20 Jul '09

20 Jul '09

Author: oxygene Date: 2009-07-20 21:34:47 +0200 (Mon, 20 Jul 2009) New Revision: 4442 Modified: trunk/coreboot-v2/src/include/x86emu/fpu_regs.h trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c Log: Rename some preprocessor symbols. I have no idea why those symbols were left alone before, after this, they're somewhat more in line with the rest of the tree. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/include/x86emu/fpu_regs.h =================================================================== --- trunk/coreboot-v2/src/include/x86emu/fpu_regs.h 2009-07-19 00:18:15 UTC (rev 4441) +++ trunk/coreboot-v2/src/include/x86emu/fpu_regs.h 2009-07-20 19:34:47 UTC (rev 4442) @@ -40,7 +40,7 @@ #define __X86EMU_FPU_REGS_H -#if defined(CONFIG_DEBUG) && (DEBUG == 0) +#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0) #undef CONFIG_DEBUG #endif Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-07-19 00:18:15 UTC (rev 4441) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_lpc.c 2009-07-20 19:34:47 UTC (rev 4442) @@ -18,8 +18,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif #define ALL (0xff << 24) @@ -277,7 +277,7 @@ { uint8_t byte; uint32_t value; - int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* sata settings */ pci_write_config32(dev, 0x58, 0x00001181); Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-07-19 00:18:15 UTC (rev 4441) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2009-07-20 19:34:47 UTC (rev 4442) @@ -33,8 +33,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif #define NMI_OFF 0

1 0

option rom size problem
by Jason Wang 20 Jul '09

20 Jul '09

Hi all, Since i am working with adding libpayload usb stack to option rom, i have been blocked with the usb_initialize function. I find that the size of libpayload is 104K, but the max size of option rom is oxff * 512bytes. which means 127.5K. I am afraid our option rom can not works fine with usb stack properly. Is there any other method for us to expand the rom size? -- Jason Wang Peking University

4 5

[PATCH] some more CONFIG_ prefixes
by Patrick Georgi 20 Jul '09

20 Jul '09

Hi, attached patch renames some preprocessor symbols. I have no idea why those symbols were left alone before, after this, they're somewhat more in line with the rest of the tree. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Index: src/southbridge/intel/esb6300/esb6300_lpc.c =================================================================== --- src/southbridge/intel/esb6300/esb6300_lpc.c (revision 4441) +++ src/southbridge/intel/esb6300/esb6300_lpc.c (working copy) @@ -18,8 +18,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif #define ALL (0xff << 24) @@ -277,7 +277,7 @@ { uint8_t byte; uint32_t value; - int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL; + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; /* sata settings */ pci_write_config32(dev, 0x58, 0x00001181); Index: src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- src/southbridge/intel/i82801gx/i82801gx_lpc.c (revision 4441) +++ src/southbridge/intel/i82801gx/i82801gx_lpc.c (working copy) @@ -33,8 +33,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_FAIL -#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif #define NMI_OFF 0 Index: src/include/x86emu/fpu_regs.h =================================================================== --- src/include/x86emu/fpu_regs.h (revision 4441) +++ src/include/x86emu/fpu_regs.h (working copy) @@ -40,7 +40,7 @@ #define __X86EMU_FPU_REGS_H -#if defined(CONFIG_DEBUG) && (DEBUG == 0) +#if defined(CONFIG_DEBUG) && (CONFIG_DEBUG == 0) #undef CONFIG_DEBUG #endif

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Board Specific vgahooks.c for vx800 Eaxmple Board
by bari 20 Jul '09

20 Jul '09

This version of vgahooks.c was used for the vx800 example board. It makes some changes to int15 support. -Bari

2 1

Gigabyte GA-MA74GM-S2H rev2
by Jason Scurtu 19 Jul '09

19 Jul '09

Hi Paul >Is the 740G chipset similar to the 780G? Well the 780G has a HD based graphics core and the 740G is X-Series based I think (X700) they just call it 2100 .. So there is a difference.. you can see it on http://en.wikipedia.org/wiki/AMD_7-Series_Chipsets Jason

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coreboot July 2009