coreboot July 2009

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[v2] r4451 - trunk/coreboot-v2/src/config
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 23:31:36 +0200 (Tue, 21 Jul 2009) New Revision: 4451 Modified: trunk/coreboot-v2/src/config/Config.lb Log: Add more warnings to CFLAGS, and also add some to HOSTCFLAGS include ldoptions from ldscript.ld instead appending it. Not everyone was happy about the -Wmissing-prototypes in CFLAGS. I put it in there now anyways, so everyone can get an overview which parts of their code could use some cleanup. If it gets too ugly, we can still remove that flag again. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-07-21 21:25:45 UTC (rev 4450) +++ trunk/coreboot-v2/src/config/Config.lb 2009-07-21 21:31:36 UTC (rev 4451) @@ -10,17 +10,17 @@ makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: $.*$/\1include/gp") makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) -makedefine CFLAGS := $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +makedefine CFLAGS := $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer if CONFIG_ASSEMBLER_DEBUG makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm end -makedefine HOSTCFLAGS:= -Os -Wall +makedefine HOSTCFLAGS:= -Os -Wall -Wstrict-prototypes -Wmissing-prototypes -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow makerule ldscript.ld depends "ldoptions $(LDSUBSCRIPTS-1)" - action "echo '/*ldoptions*/' > $@; cat ldoptions >> $@ ; for file in $(LDSUBSCRIPTS-1) ; do echo /\* $$file \*/ >> $@; cat $$file >> $@ ; done" + action "echo 'INCLUDE ldoptions' > $@; for file in $(LDSUBSCRIPTS-1) ; do echo /\* $$file \*/ >> $@; cat $$file >> $@ ; done" end #makerule cpuflags

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[v2] r4450 - in trunk/coreboot-v2/src: boot include/console include/x86emu
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 23:25:45 +0200 (Tue, 21 Jul 2009) New Revision: 4450 Modified: trunk/coreboot-v2/src/boot/hardwaremain.c trunk/coreboot-v2/src/include/console/console.h trunk/coreboot-v2/src/include/x86emu/x86emu.h Log: Example how simple it is to use printk instead of printk_something in coreboot ram stage. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-07-21 21:24:22 UTC (rev 4449) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-07-21 21:25:45 UTC (rev 4450) @@ -25,7 +25,6 @@ * C Bootstrap code for the coreboot */ - #include <console/console.h> #include <version.h> #include <device/device.h> @@ -62,7 +61,7 @@ post_code(0x39); - printk_notice("coreboot-%s%s %s %s...\n", + printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); @@ -113,6 +112,6 @@ elfboot(lb_mem); #endif #endif - printk_err("Boot failed.\n"); + printk(BIOS_ERR, "Boot failed.\n"); } Modified: trunk/coreboot-v2/src/include/console/console.h =================================================================== --- trunk/coreboot-v2/src/include/console/console.h 2009-07-21 21:24:22 UTC (rev 4449) +++ trunk/coreboot-v2/src/include/console/console.h 2009-07-21 21:25:45 UTC (rev 4450) @@ -29,6 +29,8 @@ extern int console_loglevel; int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +#define printk(x...) do_printk(x) + #define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) #define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg) #define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg) Modified: trunk/coreboot-v2/src/include/x86emu/x86emu.h =================================================================== --- trunk/coreboot-v2/src/include/x86emu/x86emu.h 2009-07-21 21:24:22 UTC (rev 4449) +++ trunk/coreboot-v2/src/include/x86emu/x86emu.h 2009-07-21 21:25:45 UTC (rev 4450) @@ -49,7 +49,8 @@ /* FIXME: undefine printk for the moment */ #ifdef COREBOOT_VERSION #include "console/console.h" -#define printk printk_debug +#undef printk +#define printk(x...) do_printk(BIOS_DEBUG, x) #else #define printk printf #endif

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[v2] r4449 - trunk/coreboot-v2/src/pc80
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 23:24:22 +0200 (Tue, 21 Jul 2009) New Revision: 4449 Modified: trunk/coreboot-v2/src/pc80/keyboard.c Log: Rewrite keyboard driver to actually wait time in ms as specified in the specs, rather than doing inexact and slow idle loops. Also improve error reporting in case of problems. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/pc80/keyboard.c =================================================================== --- trunk/coreboot-v2/src/pc80/keyboard.c 2009-07-21 21:22:40 UTC (rev 4448) +++ trunk/coreboot-v2/src/pc80/keyboard.c 2009-07-21 21:24:22 UTC (rev 4449) @@ -1,8 +1,9 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) ???? Ollie Lo <ollielo(a)hotmail.com> + * Copyright (C) 2003 Ollie Lo <ollielo(a)hotmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,16 +24,20 @@ #include <pc80/keyboard.h> #include <device/device.h> #include <arch/io.h> +#include <delay.h> +/* Wait 200ms for keyboard controller answers */ +#define KBC_TIMEOUT_IN_MS 200 + static int kbc_input_buffer_empty(void) { u32 timeout; - for(timeout = 1000000; timeout && (inb(0x64) & 0x02); timeout--) { - inb(0x80); + for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(0x64) & 0x02); timeout--) { + mdelay(1); } if (!timeout) { - printk_err("Unexpected Keyboard controller input buffer full\n"); + printk_warning("Unexpected Keyboard controller input buffer full\n"); } return !!timeout; } @@ -41,12 +46,12 @@ static int kbc_output_buffer_full(void) { u32 timeout; - for(timeout = 1000000; timeout && ((inb(0x64) & 0x01) == 0); timeout--) { - inb(0x80); + for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(0x64) & 0x01) == 0); timeout--) { + mdelay(1); } if (!timeout) { - printk_err("Keyboard controller output buffer result timeout\n"); + printk_warning("Keyboard controller output buffer result timeout\n"); } return !!timeout; } @@ -55,7 +60,8 @@ static int kbc_cleanup_buffers(void) { u32 timeout; - for(timeout = 1000000; timeout && (inb(0x64) & 0x03); timeout--) { + for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(0x64) & 0x03); timeout--) { + mdelay(1); inb(0x60); } @@ -75,7 +81,11 @@ do { if (!kbc_input_buffer_empty()) return 0; outb(command, 0x60); - if (!kbc_output_buffer_full()) return 0; + if (!kbc_output_buffer_full()) { + printk_err("Could not send keyboard command %02x\n", + command); + return 0; + } regval = inb(0x60); --resend; } while (regval == 0xFE && resend > 0); @@ -93,18 +103,21 @@ /* clean up any junk that might have been in the kbc */ if (!kbc_cleanup_buffers()) return; - /* reset/self test 8042 - send cmd 0xAA, */ + /* reset/self test 8042 - send cmd 0xAA */ if (!kbc_input_buffer_empty()) return; outb(0xAA, 0x64); - if (!kbc_output_buffer_full()) return; + if (!kbc_output_buffer_full()) { + printk_err("Could not reset keyboard controller.\n"); + return; + } /* read self-test result, 0x55 is returned in the output buffer (0x60) */ if ((regval = inb(0x60) != 0x55)) { - printk_err("Keyboard Controller selftest failed: 0x%x\n", regval); + printk_err("Keyboard Controller self-test failed: 0x%x\n", regval); return; } - /* Enable keyboard interface - No IRQ*/ + /* Enable keyboard interface - No IRQ */ resend = 10; regval = 0; do { @@ -112,8 +125,11 @@ outb(0x60, 0x64); if (!kbc_input_buffer_empty()) return; outb(0x20, 0x60); /* send cmd: enable keyboard */ - if ((inb(0x64) & 0x01)) { + if (kbc_output_buffer_full()) { regval = inb(0x60); + } else { + printk_info("Timeout while enabling keyboard. (No keyboard present?)\n"); + regval = inb(0x60); /* Better than 0 ? */ } --resend; } while (regval == 0xFE && resend > 0); @@ -127,7 +143,11 @@ printk_err("Keyboard selftest failed ACK: 0x%x\n", regval); return; } - if (!kbc_output_buffer_full()) return; + if (!kbc_output_buffer_full()) { + printk_err("Timeout waiting for keyboard after reset.\n"); + return; + } + regval = inb(0x60); if (regval != 0xAA) { printk_err("Keyboard selftest failed: 0x%x\n", regval); @@ -174,7 +194,7 @@ outb(0x60, 0x64); if (!kbc_input_buffer_empty()) return; outb(0x61, 0x60); /* send cmd: enable keyboard and IRQ 1 */ - if ((inb(0x64) & 0x01)) { + if (kbc_output_buffer_full()) { regval = inb(0x60); } --resend;

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[v2] r4448 - trunk/coreboot-v2/util/newconfig
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 23:22:40 +0200 (Tue, 21 Jul 2009) New Revision: 4448 Modified: trunk/coreboot-v2/util/newconfig/config.g Log: - Remove superfluous / from path - use make -C instead of workaround Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-07-21 21:20:45 UTC (rev 4447) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-07-21 21:22:40 UTC (rev 4448) @@ -357,7 +357,7 @@ rel_base = base else: rel_base = re.sub(treetop, "", os.path.join(dirstack.tos(), base)) - source = "$(TOP)/" + rel_base + suffix + source = "$(TOP)" + rel_base + suffix if (rel_base[0] == '/'): rel_base = re.sub("^/", "", rel_base) object = rel_base + '.o' @@ -2263,9 +2263,7 @@ file.write("include Makefile.settings\n\n") for i, o in romimages.items(): file.write("%s/coreboot.rom:\n" % o.getname()) - file.write("\tif (cd %s; \\\n" % o.getname()) - file.write("\t\t$(MAKE) coreboot.rom)\\\n") - file.write("\tthen true; else exit 1; fi;\n\n") + file.write("\t$(MAKE) -C %s coreboot.rom\n" % o.getname()) file.write("clean: ") for i in romimages.keys(): file.write(" %s-clean" % i)

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[v2] r4447 - in trunk/coreboot-v2/src: console include lib pc80
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 23:20:45 +0200 (Tue, 21 Jul 2009) New Revision: 4447 Modified: trunk/coreboot-v2/src/console/usbdebug_direct_console.c trunk/coreboot-v2/src/include/usbdebug_direct.h trunk/coreboot-v2/src/lib/usbdebug_direct.c trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c Log: Some USB debug updates, mostly comments fixing, license header updates and refactoring Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/console/usbdebug_direct_console.c =================================================================== --- trunk/coreboot-v2/src/console/usbdebug_direct_console.c 2009-07-21 21:19:06 UTC (rev 4446) +++ trunk/coreboot-v2/src/console/usbdebug_direct_console.c 2009-07-21 21:20:45 UTC (rev 4447) @@ -1,3 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + #include <string.h> #include <console/console.h> #include <usbdebug_direct.h> @@ -3,15 +20,19 @@ #include <pc80/mc146818rtc.h> -struct ehci_debug_info dbg_info; +static struct ehci_debug_info dbg_info; void set_ehci_base(unsigned ehci_base) { unsigned diff; - if(!dbg_info.ehci_debug) return; + + if (!dbg_info.ehci_debug) + return; + diff = dbg_info.ehci_caps - ehci_base; dbg_info.ehci_regs -= diff; dbg_info.ehci_debug -= diff; dbg_info.ehci_caps = ehci_base; } + void set_ehci_debug(unsigned ehci_debug) { @@ -21,39 +42,46 @@ unsigned get_ehci_debug(void) { - return dbg_info.ehci_debug; + return dbg_info.ehci_debug; } static void dbgp_init(void) { struct ehci_debug_info *dbg_infox; - dbg_infox = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM - memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info) ); + + /* At this point, all we have to do is copy the fixed address + * debug_info data structure to our version defined above. */ + + dbg_infox = (struct ehci_debug_info *) + ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info)); + + memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info)); } -static void dbgp_tx_byte(unsigned char data) +static void dbgp_tx_byte(unsigned char data) { - if(dbg_info.ehci_debug) - dbgp_bulk_write_x(&dbg_info,&data,1); + if (dbg_info.ehci_debug) + dbgp_bulk_write_x(&dbg_info, &data, 1); } -static unsigned char dbgp_rx_byte(void) +static unsigned char dbgp_rx_byte(void) { unsigned char data = 0xff; - if(dbg_info.ehci_debug) - dbgp_bulk_read_x(&dbg_info,&data,1); + + if (dbg_info.ehci_debug) + dbgp_bulk_read_x(&dbg_info, &data, 1); + return data; } -static int dbgp_tst_byte(void) +static int dbgp_tst_byte(void) { return dbg_info.ehci_debug; } static const struct console_driver usbdebug_direct_console __console = { - .init = dbgp_init, - .tx_byte = dbgp_tx_byte, - .rx_byte = dbgp_rx_byte, + .init = dbgp_init, + .tx_byte = dbgp_tx_byte, + .rx_byte = dbgp_rx_byte, .tst_byte = dbgp_tst_byte, }; - Modified: trunk/coreboot-v2/src/include/usbdebug_direct.h =================================================================== --- trunk/coreboot-v2/src/include/usbdebug_direct.h 2009-07-21 21:19:06 UTC (rev 4446) +++ trunk/coreboot-v2/src/include/usbdebug_direct.h 2009-07-21 21:20:45 UTC (rev 4447) @@ -1,3 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + #ifndef USBDEBUG_DIRECT_H #define USBDEBUG_DIRECT_H @@ -9,10 +26,12 @@ unsigned endpoint_out; unsigned endpoint_in; }; + int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size); int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size); void set_ehci_base(unsigned ehci_base); void set_ehci_debug(unsigned ehci_deug); unsigned get_ehci_debug(void); void set_debug_port(unsigned port); + #endif Modified: trunk/coreboot-v2/src/lib/usbdebug_direct.c =================================================================== --- trunk/coreboot-v2/src/lib/usbdebug_direct.c 2009-07-21 21:19:06 UTC (rev 4446) +++ trunk/coreboot-v2/src/lib/usbdebug_direct.c 2009-07-21 21:20:45 UTC (rev 4447) @@ -1,10 +1,22 @@ /* + * This file is part of the coreboot project. + * * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com) * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version - * 2 as published by the Free Software Foundation. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +/* * 2006.12.10 yhlu moved it to corbeoot and use struct instead */ #ifndef __ROMCC__ @@ -15,7 +27,6 @@ #endif #endif - #include <arch/io.h> #include <usb_ch9.h> Modified: trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c =================================================================== --- trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c 2009-07-21 21:19:06 UTC (rev 4446) +++ trunk/coreboot-v2/src/pc80/usbdebug_direct_serial.c 2009-07-21 21:20:45 UTC (rev 4447) @@ -1,24 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + #include <part/fallback_boot.h> -#include "../lib/usbdebug_direct.c" +#include "../lib/usbdebug_direct.c" + static void early_usbdebug_direct_init(void) { - struct ehci_debug_info *dbg_info = - (struct ehci_debug_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); - - usbdebug_direct_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); + struct ehci_debug_info *dbg_info = (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + + usbdebug_direct_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); } + void usbdebug_direct_tx_byte(unsigned char data) { struct ehci_debug_info *dbg_info; - dbg_info = (struct ehci_debug_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); // in Cache - if (dbg_info->ehci_debug) { + + /* "Find" dbg_info structure in Cache */ + dbg_info = (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + + if (dbg_info->ehci_debug) { dbgp_bulk_write_x(dbg_info, &data, 1); } } + void usbdebug_direct_ram_tx_byte(unsigned char data) { struct ehci_debug_info *dbg_info; - dbg_info = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM + + /* "Find" dbg_info structure in RAM */ + dbg_info = (struct ehci_debug_info *) + ((CONFIG_LB_MEM_TOPK << 10) - sizeof(struct ehci_debug_info)); + if (dbg_info->ehci_debug) { dbgp_bulk_write_x(dbg_info, &data, 1); }

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[v2] r4446 - in trunk/coreboot-v2/src: config cpu/x86/lapic cpu/x86/tsc
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 23:19:06 +0200 (Tue, 21 Jul 2009) New Revision: 4446 Added: trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c Log: * rework tsc based timer code to use inb instead of outb for calibration * Add generic Local APIC based timer code. This timer does not need expensive calibration and thus reduces the boot time by up to more than a second. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-07-21 20:27:00 UTC (rev 4445) +++ trunk/coreboot-v2/src/config/Options.lb 2009-07-21 21:19:06 UTC (rev 4446) @@ -928,6 +928,11 @@ export used comment "Implement udelay with x86 io registers" end +define CONFIG_UDELAY_LAPIC + default 0 + export used + comment "Implement udelay with the x86 Local APIC" +end define CONFIG_FAKE_SPDROM default 0 export always Modified: trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb 2009-07-21 20:27:00 UTC (rev 4445) +++ trunk/coreboot-v2/src/cpu/x86/lapic/Config.lb 2009-07-21 21:19:06 UTC (rev 4446) @@ -1,3 +1,11 @@ +uses CONFIG_UDELAY_LAPIC + object lapic.o object lapic_cpu_init.o object secondary.S + +if CONFIG_UDELAY_LAPIC + default HAVE_INIT_TIMER=1 + object apic_timer.o +end + Added: trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c (rev 0) +++ trunk/coreboot-v2/src/cpu/x86/lapic/apic_timer.c 2009-07-21 21:19:06 UTC (rev 4446) @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <delay.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> + +/* NOTE: This code uses global variables, so it can not be used during + * memory init. + */ + +#define FSB_CLOCK_STS 0xcd + +static u32 timer_fsb = 200; // default to 200MHz + +void init_timer(void) +{ + msr_t fsb_clock_sts; + + /* Set the apic timer to no interrupts and periodic mode */ + lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0)); + + /* Set the divider to 1, no divider */ + lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); + + /* Set the initial counter to 0xffffffff */ + lapic_write(LAPIC_TMICT, 0xffffffff); + + /* Set FSB frequency to a reasonable value */ + fsb_clock_sts = rdmsr(FSB_CLOCK_STS); + switch ((fsb_clock_sts.lo >> 4) & 0x07) { + case 0: timer_fsb = 266; break; + case 1: timer_fsb = 133; break; + case 2: timer_fsb = 200; break; + case 3: timer_fsb = 166; break; + case 5: timer_fsb = 100; break; + } +} + +void udelay(u32 usecs) +{ + u32 start, value, ticks; + /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */ + ticks = usecs * timer_fsb; + start = lapic_read(LAPIC_TMCCT); + do { + value = lapic_read(LAPIC_TMCCT); + } while((start - value) < ticks); +} Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-07-21 20:27:00 UTC (rev 4445) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-07-21 21:19:06 UTC (rev 4446) @@ -55,7 +55,7 @@ /* need to save it for RAM resume */ lowmem_backup_size = code_size; lowmem_backup = malloc(code_size); - lowmem_backup_ptr = (unsigned char *)start_eip; + lowmem_backup_ptr = (char *)start_eip; if (lowmem_backup == NULL) die("Out of backup memory\n"); Modified: trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c 2009-07-21 20:27:00 UTC (rev 4445) +++ trunk/coreboot-v2/src/cpu/x86/tsc/delay_tsc.c 2009-07-21 21:19:06 UTC (rev 4446) @@ -106,10 +106,10 @@ printk_spew("Calibrating delay loop...\n"); start = rdtscll(); - // no udivdi3, dammit. + // no udivdi3 because we don't like libgcc. (only in x86emu) // so we count to 1<< 20 and then right shift 20 for(count = 0; count < (1<<20); count ++) - outb(0x80, 0x80); + inb(0x80); end = rdtscll(); #if 0

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some more i945 patches
by Stefan Reinauer 21 Jul '09

21 Jul '09

I'm pushing out a number of i945 patches in order to get more public input and testing on the i945 chipset port and in order to keep some structural changes (XSDT support et al) from bit-rotting. See patches Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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build service results for r4445
by coreboot information 21 Jul '09

21 Jul '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4445 to the coreboot repository. This caused the following changes: Change Log: * cleanup ricoh rl5c476 code: - drop duplicate udelay function - simplify code flow - some cosmetics on comments Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4445&device=epia-m&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4445 - trunk/coreboot-v2/src/southbridge/ricoh/rl5c476
by svn＠coreboot.org 21 Jul '09

21 Jul '09

Author: stepan Date: 2009-07-21 22:27:00 +0200 (Tue, 21 Jul 2009) New Revision: 4445 Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/chip.h trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.h Log: * cleanup ricoh rl5c476 code: - drop duplicate udelay function - simplify code flow - some cosmetics on comments Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/chip.h 2009-07-21 18:06:12 UTC (rev 4444) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/chip.h 2009-07-21 20:27:00 UTC (rev 4445) @@ -5,7 +5,6 @@ struct southbridge_ricoh_rl5c476_config { int enable_cf; - }; -#endif /* _SOUTHBRIDGE_RL5C476 */ +#endif /* _SOUTHBRIDGE_RICOH_RL5C476 */ Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c 2009-07-21 18:06:12 UTC (rev 4444) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.c 2009-07-21 20:27:00 UTC (rev 4445) @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004 Nick Barker <nick.barker9(a)btinternet.com> + * (C) Copyright 2004-2005 Nick Barker <nick.barker(a)btinternet.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -16,8 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, * MA 02110-1301 USA */ -/* (C) Copyright 2005 Nick Barker <nick.barker(a)btinternet.com - brought into line with the current architecture of coreboot */ #include <arch/io.h> #include <device/device.h> @@ -32,21 +30,13 @@ static int enable_cf_boot = 0; static unsigned int cf_base; -static void udelay(int i) -{ - for(; i > 0 ; i--) - inb(0x80); -} - static void rl5c476_init(device_t dev) { - //unsigned char enables; pc16reg_t *pc16; - unsigned char *base; /* cardbus controller function 1 for CF Socket */ - printk_debug("rl5c476 init\n"); + printk_debug("Ricoh RL5c476: Initializing.\n"); printk_debug("CF Base = %0x\n",cf_base); @@ -54,98 +44,120 @@ pci_write_config16(dev,0x82,0x00a0); /* set up second slot as compact flash port if asked to do so */ - if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ - /* make sure isa interrupts are enabled */ - pci_write_config16(dev,0x3e,0x0780); + if (!enable_cf_boot) { + printk_debug("CF boot not enabled.\n"); + return; + } + + if (PCI_FUNC(dev->path.pci.devfn) != 1) { + // Only configure if second CF slot. + return; + } - /* pick up where 16 bit card control structure is (0x800 bytes into config structure) */ - base = (unsigned char *)pci_read_config32(dev,0x10); - pc16 = (pc16reg_t *)(base + 0x800); + /* make sure isa interrupts are enabled */ + pci_write_config16(dev,0x3e,0x0780); - /* disable memory and io windows and turn off socket power */ - pc16->pwctrl = 0; + /* pick up where 16 bit card control structure is + * (0x800 bytes into config structure) + */ + base = (unsigned char *)pci_read_config32(dev,0x10); + pc16 = (pc16reg_t *)(base + 0x800); - /* disable irq lines */ - pc16->igctrl = 0; + /* disable memory and io windows and turn off socket power */ + pc16->pwctrl = 0; - /* disable memory and I/O windows */ - pc16->awinen = 0; + /* disable irq lines */ + pc16->igctrl = 0; - /* reset card, configure for I/O and set IRQ line */ - pc16->igctrl = 0x69; + /* disable memory and I/O windows */ + pc16->awinen = 0; - // set io window 0 for 1e0 - 1ef - /* note this now sets CF up on a contiguous I/O window of 16 bytes, 0x1e0 to 0x1ef - Be warned that this is not a standard IDE address as automatically detected by the likes - of Filo, and would need patching to recognise these addresses as an IDE drive */ - /* an earlier version of this driver set up 2 io windows to emulate the expected addresses - for IDE2, however the pcmcia package within Linux then could not re-initiailse the - device as it tried to take control of it. So I belive it is easier to patch Filo or the like - to pick up this drive rather than playing silly games as the kernel tries to boot. - */ - pc16->iostl0 = 0xe0; - pc16->iosth0 = 1; + /* reset card, configure for I/O and set IRQ line */ + pc16->igctrl = 0x69; - pc16->iospl0 = 0xef; - pc16->iosph0 = 1; + /* set io window 0 for 1e0 - 1ef */ + /* NOTE: This now sets CF up on a contiguous I/O window of + * 16 bytes, 0x1e0 to 0x1ef. + * Be warned that this is not a standard IDE address as + * automatically detected by the likes of FILO, and would need + * patching to recognise these addresses as an IDE drive. + * + * An earlier version of this driver set up 2 I/O windows to + * emulate the expected addresses for IDE2, however the PCMCIA + * package within Linux then could not re-initialize the + * device as it tried to take control of it. So I believe it is + * easier to patch Filo or the like to pick up this drive + * rather than playing silly games as the kernel tries to + * boot. + * + * Nonetheless, FILO needs a special option enabled to boot + * from this configuration, and it needs to clean up + * afterwards. Please refer to FILO documentation and source + * code for more details. + */ + pc16->iostl0 = 0xe0; + pc16->iosth0 = 1; - pc16->ioffl0 = 0; - pc16->ioffh0 = 0; + pc16->iospl0 = 0xef; + pc16->iosph0 = 1; - // clear window 1 - pc16->iostl1 = 0; - pc16->iosth1 = 0; + pc16->ioffl0 = 0; + pc16->ioffh0 = 0; - pc16->iospl1 = 0; - pc16->iosph1 = 0; + /* clear window 1 */ + pc16->iostl1 = 0; + pc16->iosth1 = 0; - pc16->ioffl1 = 0x0; - pc16->ioffh1 = 0; + pc16->iospl1 = 0; + pc16->iosph1 = 0; - // set up CF config window - pc16->smpga0 = cf_base>>24; - pc16->smsth0 = (cf_base>>20)&0x0f; - pc16->smstl0 = (cf_base>>12)&0xff; - pc16->smsph0 = ((cf_base>>20)&0x0f) | 0x80; - pc16->smspl0 = (cf_base>>12)&0xff; - pc16->moffl0 = 0; - pc16->moffh0 = 0x40; + pc16->ioffl1 = 0x0; + pc16->ioffh1 = 0; + /* set up CF config window */ + pc16->smpga0 = cf_base>>24; + pc16->smsth0 = (cf_base>>20)&0x0f; + pc16->smstl0 = (cf_base>>12)&0xff; + pc16->smsph0 = ((cf_base>>20)&0x0f) | 0x80; + pc16->smspl0 = (cf_base>>12)&0xff; + pc16->moffl0 = 0; + pc16->moffh0 = 0x40; - // set I/O width for Auto Data width - pc16->ioctrl = 0x22; + /* set I/O width for Auto Data width */ + pc16->ioctrl = 0x22; - // enable I/O window 0 and 1 - pc16->awinen = 0xc1; + /* enable I/O window 0 and 1 */ + pc16->awinen = 0xc1; - pc16->miscc1 = 1; + pc16->miscc1 = 1; - // apply power and enable outputs - pc16->pwctrl = 0xb0; - + /* apply power and enable outputs */ + pc16->pwctrl = 0xb0; - // delay could be optimised, but this works - udelay(100000); - - pc16->igctrl = 0x69; + // delay could be optimised, but this works + udelay(100000); + pc16->igctrl = 0x69; - // 16 bit CF always have first config byte at 0x200 into Config structure, - // but CF+ May Not according to spec - should locate through reading tuple data, - // but this will do for now !!! - unsigned char *cptr; - cptr = (unsigned char *)(cf_base + 0x200); - printk_debug("CF Config = %x\n",*cptr); - // set CF to decode 16 IO bytes on any 16 byte boundary - rely on the io - // windows of the bridge set up above to map those bytes into the - // addresses for ide controller 3 (0x1e8 - 0x1ef and 0x3ed - 0x3ee) - *cptr = 0x41; - } + /* 16 bit CF always have first config byte at 0x200 into + * Config structure, but CF+ may not according to spec - + * should locate through reading tuple data, but this should + * do for now. + */ + unsigned char *cptr; + cptr = (unsigned char *)(cf_base + 0x200); + printk_debug("CF Config = %x\n",*cptr); + /* Set CF to decode 16 IO bytes on any 16 byte boundary - + * rely on the io windows of the bridge set up above to + * map those bytes into the addresses for IDE controller 3 + * (0x1e8 - 0x1ef and 0x3ed - 0x3ee) + */ + *cptr = 0x41; } void rl5c476_read_resources(device_t dev) @@ -153,9 +165,12 @@ struct resource *resource; - /* for cf socket we need an extra memory window for the control structure of the cf itself */ + /* For CF socket we need an extra memory window for + * the control structure of the CF itself + */ if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ - resource = new_resource(dev,1); /* fake index as it isn't in pci config space */ + /* fake index as it isn't in PCI config space */ + resource = new_resource(dev, 1); resource->flags |= IORESOURCE_MEM ; resource->size = 0x1000; resource->align = resource->gran = 12; Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.h =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.h 2009-07-21 18:06:12 UTC (rev 4444) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/rl5c476.h 2009-07-21 20:27:00 UTC (rev 4445) @@ -1,7 +1,6 @@ /* * (C) Copyright 2004 Nick Barker <nick.barker9(a)btinternet.com> * - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of

1 0

option rom new progress
by Jason Wang 21 Jul '09

21 Jul '09

Hi all Since a few days passed, the option rom have already got some new progress. 1) the size have already expanded to 127.5K 2) the rom can been run not only in segment 0xce00, all of the hardcode things have already been removed. 3) the init and int13 have already been improved within some details. my next progress is going to make the option rom init funciton can detect the usb devices -- Jason Wang Peking University

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coreboot July 2009