coreboot April 2009

coreboot@coreboot.org

69 participants
583 discussions

build service results for r4082
by coreboot information 07 Apr '09

07 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4082 to the coreboot repository. This caused the following changes: Change Log: This tested ok, but qemu can't really handle c0000 as RAM. (trivial) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4082&device=ep405pc&vendor… Configuration of motorola:sandpoint is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4082&device=sandpoint&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4082&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4082&device=briq&vendor=to… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4082 - trunk/coreboot-v2/src/mainboard/emulation/qemu-x86
by svn＠coreboot.org 07 Apr '09

07 Apr '09

Author: rminnich Date: 2009-04-07 17:38:17 +0200 (Tue, 07 Apr 2009) New Revision: 4082 Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb Log: This tested ok, but qemu can't really handle c0000 as RAM. (trivial) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-04-07 14:27:38 UTC (rev 4081) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-04-07 15:38:17 UTC (rev 4082) @@ -39,6 +39,7 @@ uses CONFIG_PCI_OPTION_ROM_RUN_VM86 uses CONFIG_CONSOLE_SERIAL8250 +uses USE_DCACHE_RAM uses DEFAULT_CONSOLE_LOGLEVEL @@ -49,7 +50,7 @@ default CONFIG_CONSOLE_SERIAL8250=1 default DEFAULT_CONSOLE_LOGLEVEL=8 default MAXIMUM_CONSOLE_LOGLEVEL=8 -default CONFIG_ROMFS=1 +default CONFIG_ROMFS=0 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024

1 0

Net and virtio problem with QEMU 0.10.0 and coreboot v2
by rukhsana ansari 07 Apr '09

07 Apr '09

Hi, Software used : qemu-0.10.0, coreboot-v2, filo(latest svn version), fedora9 image Problem encountered: qemu boots Fedora9 image successfully. However, the ethernet interface isn't up and dmesg shows an irq problem. Thhings tried out: I've tried pci=biosirq and problems still remains. I've also patched with the qemu bios patch (0.9.1) available at: http://www.mail-archive.com/coreboot@coreboot.org/msg01771.html However, I haven't applied the other patches that are meant for 0.9 and available at ttp://www.coreboot.org/QEMU_Build_Tutorial#Building_Qemu <http://www.coreboot.org/QEMU_Build_Tutorial#Building_Qemu> because the code difference with 0.10.0 Any suggestions from coreboot experts on howto proceed to resolve this issue? === The following is an edited version of dmesg that shows an irq problem: ne2k-pci.c:v1.03 9/22/2003 D. Becker/P. Gortmaker PCI: No IRQ known for interrupt pin A of device 0000:00:03.0. Please try using pci=biosirq. eth0: RealTek RTL-8029 found at 0x1000, IRQ 0, 52:54:00:12:34:56. PCI: No IRQ known for interrupt pin A of device 0000:00:04.0. Please try using pci=biosirq. IRQ handler type mismatch for IRQ 0 current handler: timer Pid: 490, comm: modprobe Not tainted 2.6.25-14.fc9.i686 #1 [<c045cae6>] setup_irq+0x19a/0x1b2 [<c48ec2fe>] ? vp_interrupt+0x0/0x9a [virtio_pci] [<c045cbc6>] request_irq+0xc8/0xe6 [<c48ec53a>] virtio_pci_probe+0x138/0x193 [virtio_pci] [<c04feac9>] pci_device_probe+0x39/0x59 [<c0562826>] driver_probe_device+0xa0/0x136 [<c0562935>] __driver_attach+0x79/0xaf [<c05621d3>] bus_for_each_dev+0x3b/0x63 [<c05626cb>] driver_attach+0x14/0x16 [<c05628bc>] ? __driver_attach+0x0/0xaf [<c0561ba4>] bus_add_driver+0x9d/0x1ba [<c0562ab8>] driver_register+0x47/0xa7 [<c04fec75>] __pci_register_driver+0x35/0x64 [<c480e028>] virtio_pci_init+0x28/0x3d [virtio_pci] [<c0446f93>] sys_init_module+0x17be/0x18f6 [<c04d3577>] ? selinux_file_permission+0x100/0x106 [<c04cc41c>] ? security_file_permission+0xf/0x11 [<c04835e1>] ? sys_read+0x3b/0x60 [<c0405bf2>] syscall_call+0x7/0xb ======================= virtio-pci: probe of 0000:00:04.0 failed with error -16 --- IRQ handler type mismatch for IRQ 0 current handler: timer Pid: 1524, comm: NetworkManager Not tainted 2.6.25-14.fc9.i686 #1 [<c045cae6>] setup_irq+0x19a/0x1b2 [<c488ff10>] ? ei_interrupt+0x0/0xa [8390] [<c045cbc6>] request_irq+0xc8/0xe6 [<c48e8447>] ne2k_pci_open+0x1c/0x79 [ne2k_pci] [<c05baccf>] dev_open+0x46/0x7e [<c05ba84e>] dev_change_flags+0x9f/0x152 [<c05c12f6>] do_setlink+0x211/0x2c3 [<c05c148a>] rtnl_setlink+0xe2/0xe6 [<c05c13a8>] ? rtnl_setlink+0x0/0xe6 [<c05c231f>] rtnetlink_rcv_msg+0x1a0/0x1ba [<c05c217f>] ? rtnetlink_rcv_msg+0x0/0x1ba [<c05cf18e>] netlink_rcv_skb+0x30/0x86 [<c05c2177>] rtnetlink_rcv+0x1c/0x24 [<c05cecb8>] netlink_unicast+0x1b1/0x20f [<c05cef6b>] netlink_sendmsg+0x255/0x262 [<c05afda0>] sock_sendmsg+0xde/0xf9 [<c04387e7>] ? autoremove_wake_function+0x0/0x33 [<c04387e7>] ? autoremove_wake_function+0x0/0x33 [<c04cf49e>] ? socket_has_perm+0x53/0x5d [<c04f5874>] ? copy_from_user+0x39/0x121 [<c05b6309>] ? verify_iovec+0x40/0x6f [<c05afefa>] sys_sendmsg+0x13f/0x192 [<c05b08e7>] ? sys_recvmsg+0x116/0x17b [<c04f5997>] ? copy_to_user+0x3b/0x10a [<c05b07b9>] ? move_addr_to_user+0x56/0x6e [<c05b0aef>] ? sys_getsockname+0x59/0x76 [<c062bb5a>] ? _spin_unlock_bh+0xe/0x10 [<c05b18b2>] ? release_sock+0x80/0x88 [<c05b2f92>] ? sock_setsockopt+0x506/0x510 [<c04d2097>] ? selinux_socket_setsockopt+0x2d/0x32 [<c05b0deb>] sys_socketcall+0x16b/0x188 [<c0405bf2>] syscall_call+0x7/0xb = ====================== cat /proc/interrupts shows - CPU0 0: 154394 XT-PIC-XT timer 1: 221 XT-PIC-XT i8042 2: 0 XT-PIC-XT cascade 4: 4 XT-PIC-XT 12: 111 XT-PIC-XT i8042 14: 5125 XT-PIC-XT ata_piix 15: 753 XT-PIC-XT ata_piix NMI: 0 Non-maskable interrupts LOC: 102 Local timer interrupts RES: 0 Rescheduling interrupts CAL: 0 function call interrupts TLB: 0 TLB shootdowns TRM: 0 Thermal event interrupts SPU: 0 Spurious interrupts ERR: 0 MIS: 0 Thanks, -Rukhsana

2 7

build service results for r4081
by coreboot information 07 Apr '09

07 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4081 to the coreboot repository. This caused the following changes: Change Log: add Config-abuild for the new board (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4081&device=ep405pc&vendor… Configuration of motorola:sandpoint is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4081&device=sandpoint&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4081&device=sandpointx3_al… Compilation of technexion:tim8690 has been fixed Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4081&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4081 - trunk/coreboot-v2/targets/technexion/tim8690
by svn＠coreboot.org 07 Apr '09

07 Apr '09

Author: stepan Date: 2009-04-07 16:27:38 +0200 (Tue, 07 Apr 2009) New Revision: 4081 Added: trunk/coreboot-v2/targets/technexion/tim8690/Config-abuild.lb Log: add Config-abuild for the new board (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/targets/technexion/tim8690/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/technexion/tim8690/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/technexion/tim8690/Config-abuild.lb 2009-04-07 14:27:38 UTC (rev 4081) @@ -0,0 +1,25 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

1 0

Re: [coreboot] flashrom fails to write/erase on VIA VT8237
by vinuxesgmail 07 Apr '09

07 Apr '09

Hello Peter, > >1. Which vendor and board is this? > The M/B model name is PPAP-2020VL, and the vendor is Portwell. > >2. Please find out where pin 7 WP# and 8 TBL# on the flash chip are > connected. To which pin on which chip? > Pin 7 and 8 of the flash-chip are connected to GPIOA. GPIOA connects to 8237R AE5 PIN. Please find the attached board diagram image "8237.jpg". Let me know if u need any further information. Regards, Vinod

4 13

Re: [coreboot] [Bochs-developers] Has anyone used a real BIOS image?
by Carl-Daniel Hailfinger 07 Apr '09

07 Apr '09

Hi Mark, you have some coreboot questions in the mail below. I'm quoting it in full and adding the coreboot mailing list to CC. On 06.04.2009 00:15, Mark Marshall wrote: > For various reasons (mainly out of curiosity) I've been spending a while > to see if I can get Bochs to boot (and maybe then run) with a real > (unaltered) BIOS. Has anyone done this in the past? What BIOS did they > use? How much did they need to tweak things to get it to work? (I need > PCI for this to be interesting to me). > > I've been playing around trying to get an ASUS P2B to boot. I've got as > far as it getting the graphics up and running (by mapping in the VGA > cards BIOS) but it seems to hang while it's running some sort of test on > the PIT. The POST code has counted up from 0x05 to 0x14 but then hangs. > (The Award docs I've found on the net all say that 0x14 means it's > doing something with the PIT). > Are you trying to get an Asus P2B (hardware) to work or do you want to execute the P2B BIOS in Bochs? Given your first sentence, it seems you want the latter. > To get this far I've had to tweak a few things, mainly to move the PCI > hardware up to 440BX standard. I've also created a skeleton SuperIO. > > This is the sort of generation of hardware that I wanted to go for, but > I had no real requirements. It seemed that the P2B was well understood > (It's the generation of Intel chip-set that seems to be best documented). > > I had to add a little more support to the SMBus stuff, but I still don't > really know what values I should return to mean what - there's a good > chance I've told the BIOS that I have gigs of RAM. > > Has anyone ever used a coreboot BIOS with Bochs? Does this work? Do > the coreboot guys even use Bochs to get things going (if they don't yet, > then I suspect that they would really appreciate Bochs emulation being > improved to the point where this is possible). > The standard coreboot target for development without hardware is Qemu. I believe coreboot runs in Bochs as well, but it's been a long time since I tried and I don't really remember the results. > I first got interested in Bochs because I've been writing the VGA BIOS > for the OGD1 project. For this I wanted a development cycle that didn't > involve re-flashing a board and then power-cycling a PC. Bochs has been > great for this, so thanks. > > MM > > > PS. > I will at some point have a few patches to send up-stream, but I have > slightly large questions about the configuration mechanism used in Bochs > at the moment. I'd like to be able to give it configuration files that > matched different _real_ hardware - I'm not convinced that we can do > that at the moment. (A P2B, a A7N8x, etc.). > Regards, Carl-Daniel -- http://www.hailfinger.org/

3 2

build service results for r4080
by coreboot information 07 Apr '09

07 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4080 to the coreboot repository. This caused the following changes: Change Log: This is a bit of an emergency fix for qemu. Ethernet routing has not been working. Given all the limitations of PIRQ routing we keep it simple and just set the IRQ directly. Most BIOSes are doing setup this way anyways, since there are so many errors in PIRQ tables. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4080&device=ep405pc&vendor… Configuration of motorola:sandpoint is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4080&device=sandpoint&vend… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4080&device=sandpointx3_al… Compilation of technexion:tim8690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4080&device=tim8690&vendor… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4080&device=briq&vendor=to… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

qemu on v2
by ron minnich 07 Apr '09

07 Apr '09

I just did a quick two-liner to the mainboard.c file for qemu that fixes the IRQ issue with ethernet. If someone wishes they can replicate this fix for v3. ron

1 0

[v2] r4080 - trunk/coreboot-v2/src/mainboard/emulation/qemu-x86
by svn＠coreboot.org 07 Apr '09

07 Apr '09

Author: rminnich Date: 2009-04-07 04:18:13 +0200 (Tue, 07 Apr 2009) New Revision: 4080 Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/mainboard.c Log: This is a bit of an emergency fix for qemu. Ethernet routing has not been working. Given all the limitations of PIRQ routing we keep it simple and just set the IRQ directly. Most BIOSes are doing setup this way anyways, since there are so many errors in PIRQ tables. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/mainboard.c 2009-04-06 23:28:22 UTC (rev 4079) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/mainboard.c 2009-04-07 02:18:13 UTC (rev 4080) @@ -7,7 +7,10 @@ #include <arch/io.h> #include "chip.h" -static void vga_init(device_t dev) +/* not sure how these are routed in qemu */ +static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 }; + +static void qemu_init(device_t dev) { /* The VGA OPROM already lives at 0xc0000, * force coreboot to use it. @@ -22,13 +25,19 @@ * emulate a SuperIO chip */ init_pc_keyboard(0x60, 0x64, 0); + + /* The PIRQ table is not working well for interrupt routing purposes. + * so we'll just set the IRQ directly. + */ + printk_info("setting ethernet\n"); + pci_assign_irqs(0, 3, enetIrqs); } static struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = vga_init, + .init = qemu_init, .ops_pci = 0, };

1 0

← Newer
1
...
44
45
46
47
48
49
50
...
59
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2009