coreboot April 2009

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583 discussions

[flashrom][PATCH] MX25L1605 and 1635 accept Chip Erase opcodes 60 and C7
by stephan.guilloux＠free.fr 19 Apr '09

19 Apr '09

Hello, As seen in the specs these 2 chips accept CE (Chip Erase) opcodes 60 and C7. Below a patch to fix flashrom accordingly. Also available in attachment. Make good use of it. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Index: flashrom/flashchips.c =================================================================== --- flashrom/flashchips.c (révision 4138) +++ flashrom/flashchips.c (copie de travail) @@ -806,7 +806,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, }, @@ -820,7 +820,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, },

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[v2] r4139 - trunk/util/flashrom
by svn＠coreboot.org 19 Apr '09

19 Apr '09

Author: stuge Date: 2009-04-20 01:24:26 +0200 (Mon, 20 Apr 2009) New Revision: 4139 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: MX25L1605 and 1635 accept Chip Erase opcodes 60 and C7 Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2009-04-19 23:04:00 UTC (rev 4138) +++ trunk/util/flashrom/flashchips.c 2009-04-19 23:24:26 UTC (rev 4139) @@ -806,7 +806,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, }, @@ -820,7 +820,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, - .erase = spi_chip_erase_c7, + .erase = spi_chip_erase_60_c7, .write = spi_chip_write, .read = spi_chip_read, },

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[flashrom][PATCH] support for MX251635D
by stephan.guilloux＠free.fr 19 Apr '09

19 Apr '09

Hello, Below, a patch to allow MX25L1635D support, as discussed on #coreboot. It is also available in attachment. Make good use of it ;-) Stephan. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Index: flashrom/flashchips.c =================================================================== --- flashrom/flashchips.c (révision 4137) +++ flashrom/flashchips.c (copie de travail) @@ -813,6 +813,19 @@ { .vendor = "Macronix", + .name = "MX25L1635D", + .manufacture_id = MX_ID, + .model_id = MX_25L1635D, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .erase = spi_chip_erase_c7, + .write = spi_chip_write, + .read = spi_chip_read, + }, + { + .vendor = "Macronix", .name = "MX25L3205", .manufacture_id = MX_ID, .model_id = MX_25L3205,

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[v2] r4138 - trunk/util/flashrom
by svn＠coreboot.org 19 Apr '09

19 Apr '09

Author: hailfinger Date: 2009-04-20 01:04:00 +0200 (Mon, 20 Apr 2009) New Revision: 4138 Modified: trunk/util/flashrom/flashchips.c Log: Add MX25L1635D support, as discussed on #coreboot. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2009-04-18 23:04:28 UTC (rev 4137) +++ trunk/util/flashrom/flashchips.c 2009-04-19 23:04:00 UTC (rev 4138) @@ -813,6 +813,19 @@ { .vendor = "Macronix", + .name = "MX25L1635D", + .manufacture_id = MX_ID, + .model_id = MX_25L1635D, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .erase = spi_chip_erase_c7, + .write = spi_chip_write, + .read = spi_chip_read, + }, + { + .vendor = "Macronix", .name = "MX25L3205", .manufacture_id = MX_ID, .model_id = MX_25L3205,

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Timing via serial port
by Kevin O'Connor 19 Apr '09

19 Apr '09

Hi, I wrote a script that can be used on a host machine to read from the serial port and output timing information on each line received. It also tries to adjust for time spent by the target machine actually generating the serial reports. The script is attached if anyone wants to use it (it requires python and the pyserial package). The results are interesting. On my epia-cn machine, it takes coreboot-v2 8.7 seconds to launch SeaBIOS. It looks like about 4 seconds is lost due to a reboot half-way through the startup - I'm guessing a watchdog timer is kicking in. As to why it takes so long to boot - maybe rom caching is off? SeaBIOS takes 1.5 seconds (from startup to OS launch) - after subtracting the 2.5 seconds spent waiting at the boot menu. The biggest SeaBIOS time consumers: 500ms - initializing the ps2 port / keyboard 425ms - scanning for option roms 260ms - initializing ATA drives 200ms - running the via vga rom -Kevin

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build service results for r4137
by coreboot information 18 Apr '09

18 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "mjones" checked in revision 4137 to the coreboot repository. This caused the following changes: Change Log: There is a typo in amdk8/raminit_f.c regarding the preprocessor symbol QRANK_DIMM_SUPPORT in line 2208, which caused the protected code fragment never to be included for compilation. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4137&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4137&device=alix1c&vendor=… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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typo in amdk8/raminit_f.c
by Ronald Hoogenboom 18 Apr '09

18 Apr '09

Hi, There is a typo in amdk8/raminit_f.c regarding the preprocessor symbol QRANK_DIMM_SUPPORT in line 2208, which caused the protected code fragment never to be included for compilation. I guessed what the dimm_mask and sz.rank should have been (I'm not familiar with the functionality of this piece of code). Please review, anyone who is familiar (yhlu/mjones?). Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl>

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[v2] r4137 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 18 Apr '09

18 Apr '09

Author: mjones Date: 2009-04-19 01:04:28 +0200 (Sun, 19 Apr 2009) New Revision: 4137 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c Log: There is a typo in amdk8/raminit_f.c regarding the preprocessor symbol QRANK_DIMM_SUPPORT in line 2208, which caused the protected code fragment never to be included for compilation. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-04-18 18:10:38 UTC (rev 4136) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2009-04-18 23:04:28 UTC (rev 4137) @@ -2205,9 +2205,10 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if QRANK_DIMM_SUPPRT == 1 +#if QRANK_DIMM_SUPPORT == 1 int value; int i; + long dimm_mask = meminfo->dimm_mask; if (!(meminfo->is_registered)) return; @@ -2219,7 +2220,7 @@ continue; } - if (meminfo->sz.rank == 4) { + if (meminfo->sz[i].rank == 4) { value = 1; break; }

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Re: [coreboot] [v2] r4136 - trunk/coreboot-v2/documentation
by Carl-Daniel Hailfinger 18 Apr '09

18 Apr '09

On 18.04.2009 20:10, svn(a)coreboot.org wrote: > Author: stepan > New Revision: 4136 > > Removed: > trunk/coreboot-v2/documentation/ChangeLog.cvsimport > Log: > drop the ChangeLog.cvsimport document from the transition from CVS > to GNU arch. Does anyone remember that? What a fun! > All history is in the SVN repository, including the CVS and TLA parts, > so nothing is lost. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > Great, thanks! That file gave me so many false grep hits. I'm glad it's gone. Regards, Carl-Daniel -- http://www.hailfinger.org/

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build service results for r4136
by coreboot information 18 Apr '09

18 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4136 to the coreboot repository. This caused the following changes: Change Log: drop the ChangeLog.cvsimport document from the transition from CVS to GNU arch. Does anyone remember that? What a fun! All history is in the SVN repository, including the CVS and TLA parts, so nothing is lost. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4136&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4136&device=alix1c&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot April 2009