coreboot April 2009

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Remaining ROMCC targets
by Carl-Daniel Hailfinger 20 Apr '09

20 Apr '09

This is a list of targets using ROMCC together with the CPU type used for ROMCC. bcom/winnetp680 c3 jetway/j7f24 c3 via/epia c3 via/epia-cn c3 via/epia-m c3 via/pc2500e c3 asi/mb_5blmp i386 digitallogic/msm586seg i386 eaglelion/5bcm i386 emulation/qemu-x86 i386 iei/juki-511p i386 iei/nova4899r i386 lippert/frontrunner i386 technologic/ts5300 i386 abit/be6-ii_v2_0 p2 amd/rumba p2 asus/mew-am p2 asus/mew-vm p2 asus/p2b-ds p2 asus/p2b-f p2 asus/p2b p2 asus/p3b-f p2 a-trend/atc-6220 p2 a-trend/atc-6240 p2 azza/pt-6ibd p2 biostar/m6tba p2 compaq/deskpro_en_sff_p600 p2 gigabyte/ga-6bxc p2 msi/ms6119 p2 msi/ms6147 p2 msi/ms6178 p2 nec/powermate2000 p2 olpc/btest p2 olpc/rev_a p2 tyan/s1846 p2 digitallogic/adl855pc p3 rca/rm4100 p3 thomson/ip1000 p3 dell/s1850 p4 intel/jarrell p4 intel/mtarvon p4 intel/truxton p4 intel/xe7501devkit p4 supermicro/x6dai_g p4 supermicro/x6dhe_g2 p4 supermicro/x6dhe_g p4 supermicro/x6dhr_ig2 p4 supermicro/x6dhr_ig p4 Does anybody own any of these boards? If so, which? I hope to use CAR on at least some of them. Regards, Carl-Daniel -- http://www.hailfinger.org/

6 14

[v2] r4143 - trunk/coreboot-v2/documentation
by svn＠coreboot.org 20 Apr '09

20 Apr '09

Author: rminnich Date: 2009-04-20 17:36:57 +0200 (Mon, 20 Apr 2009) New Revision: 4143 Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex Log: Continuing the slow doc-o update Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex =================================================================== --- trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2009-04-20 12:38:17 UTC (rev 4142) +++ trunk/coreboot-v2/documentation/LinuxBIOS-AMD64.tex 2009-04-20 15:36:57 UTC (rev 4143) @@ -1554,7 +1554,7 @@ A coreboot rom file consists of one or more \textit{images}. All images consist of a part that runs in ROM, and a part that runs in RAM. The RAM can be in compressed form and is decompressed when needed by the ROM code. The main function of the ROM code is to get memory working. Both ROM and RAM consist of a very small amount of assembly code and mostly C code. -\subsection{romcc images} +\subsection{romcc images (from emulation/qemu)} ROMCC images are so-called because C code for the ROM part is compiled with romcc. romcc is an optimizing C compiler which compiles one, and only one file; to get more than one file, one must include the C code via include statements. The main ROM code .c file is usually called auto.c. \subsubsection{how it is built} @@ -1596,7 +1596,7 @@ Each image (normal or fallback) is built completely independently and does not get linked to the other. They are assembled into one ROM image by the (soon to be deprecated) buildrom tool, or by the cbfs tool. \subsubsection{boot sequence} -We boot and start at fffffff0. We then jump to the entry point at \_start. Protected\_start does some machine init and an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. The code does a bit more machine setup and then starts executing the romcc code. +We boot and start at fffffff0. We then jump to the entry point at \_start. \_start does some machine init and an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. The code does a bit more machine setup and then starts executing the romcc code. If fallback has been built in, some setup needs to be done. On some machines, it is extensive. Full rom decoding must be enabled. This may in turn require additional PCI setup to enable decoding to be enabled (!). To decided which image to use, hardware registers (cold boot on the Opteron) or CMOS are checked. Finally, once the image to use has been decided, a jmp is performed, viz: \begin{verbatim} @@ -1623,18 +1623,36 @@ ; \end{verbatim} How does the fallback image get the symbol for normal entry? Via magic in the ldscript.ld -- remember, the images are not linked to each other. -\subsection{car images} +Finally, we can see this in the Config.lb for most mainboards: +\begin{verbatim} +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +\end{verbatim} +What does this mean? the non-fallback image has a 32-bit entry point; fallback has a 16-bit entry point. The reason for this is that some code from fallback always runs, so as to pick fallback or normal; but the normal is always called from 32-bit code. +\subsection{car images (from lippert/roadrunner-lx)} +CAR images in their simplest form are modified romcc images. The file is usually cache\_as\_ram\_auto.c. C inclusion is still used. The main difference is in the build sequence. The compiler command line is a very slight changed: instead of using romcc to generate an auto.inc include file, gcc us used. Then, two perl scripts are used to rename the .text and .data sections to .rom.text and .rom.data respectively. \subsubsection{how it is built} +The build is almost identical to the romcc build. Since the auto.inc file exists, it can be included as before. The crt0\_includes.h file has one addition: a file that enables CAR, in this case it is \textit{src/cpu/amd/model\_lx/cache\_as\_ram.inc}. \subsubsection{layout} +No significant change from romcc code. \subsubsection{boot sequence} -We boot and start at fffffff0. We then jump to the entry point at protected\_start (a clear misnomer, since we're not in protected mode at that -point). Protected\_start does an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. +No significant change from romcc code, except that the CAR code has to set up a stack. -\subsection{car + config\_use\_init images} +\subsection{car + CONFIG\_USE\_INIT images} \subsubsection{how it is built} \subsubsection{layout} \subsubsection{boot sequence} +We boot and start at fffffff0. We then jump to the entry point at protected\_start (a clear misnomer, since we're not in protected mode at that +point). Protected\_start does an lgdt and jumps to \_\_protected\_start, at which point we are in protected mode. +\subsection{car + CONFIG\_USE\_PRINTK\_IN\_CAR images} +When CONFIG\_USE\_PRINTK\_IN\_CAR is set, the CAR code can use printk instead of the primitive print functions. + \subsection{failover} %

1 0

[v2] r4142 - trunk/util/flashrom
by svn＠coreboot.org 20 Apr '09

20 Apr '09

Author: stuge Date: 2009-04-20 14:38:17 +0200 (Mon, 20 Apr 2009) New Revision: 4142 Modified: trunk/util/flashrom/board_enable.c Log: flashrom: board_enables: reconstruct table. This patch restores the pciid based board matching table. It makes this table readable and hackable again, and the only disadvantage is that the right margin is way beyond the rather dogmatic 80. All 0x0000 pci ids have been string replaced by 0 to more easily spot missing ids, and extra comments have been added to explain how the various entries are used. Signed-Off-By: Luc Verhaegen <libv(a)skynet.be> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2009-04-20 12:34:30 UTC (rev 4141) +++ trunk/util/flashrom/board_enable.c 2009-04-20 12:38:17 UTC (rev 4142) @@ -618,9 +618,18 @@ * the basis of subsystem/card IDs. As not every vendor handles * subsystem/card IDs in a sane manner. * - * Keep the second set NULLed if it should be ignored. + * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs + * NULLed if they don't identify the board fully. But please take care to + * provide an as complete set of pci ids as possible; autodetection is the + * preferred behaviour and we would like to make sure that matches are unique. * - * Keep the subsystem IDs NULLed if they don't identify the board fully. + * The coreboot ids are used two fold. When running with a coreboot firmware, + * the ids uniquely matches the coreboot board identification string. When a + * legacy bios is installed and when autodetection is not possible, these ids + * can be used to identify the board through the -m command line argument. + * + * When a board is identified through its coreboot ids (in both cases), the + * main pci ids are still required to match, as a safeguard. */ struct board_pciid_enable { /* Any device, but make it sensible, like the ISA bridge. */ @@ -629,7 +638,7 @@ uint16_t first_card_vendor; uint16_t first_card_device; - /* Any device, but make it sensible, like + /* Any device, but make it sensible, like * the host bridge. May be NULL. */ uint16_t second_vendor; @@ -646,425 +655,38 @@ }; struct board_pciid_enable board_pciid_enables[] = { - { - .first_vendor = 0x1106, - .first_device = 0x0571, - .first_card_vendor = 0x1462, - .first_card_device = 0x7120, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "msi", - .lb_part = "kt4v", - .name = "MSI KT4V", - .enable = board_msi_kt4v, - }, - { - .first_vendor = 0x8086, - .first_device = 0x1a30, - .first_card_vendor = 0x1043, - .first_card_device = 0x8070, - .second_vendor = 0x8086, - .second_device = 0x244b, - .second_card_vendor = 0x1043, - .second_card_device = 0x8028, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "ASUS P4B266", - .enable = ich2_gpio22_raise, - }, - { - .first_vendor = 0x10de, - .first_device = 0x0360, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "gigabyte", - .lb_part = "m57sli", - .name = "GIGABYTE GA-M57SLI-S4", - .enable = it87xx_probe_spi_flash, - }, - { - .first_vendor = 0x10de, - .first_device = 0x03e0, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "gigabyte", - .lb_part = "m61p", - .name = "GIGABYTE GA-M61P-S3", - .enable = it87xx_probe_spi_flash, - }, - { - .first_vendor = 0x1002, - .first_device = 0x4398, - .first_card_vendor = 0x1458, - .first_card_device = 0x5004, - .second_vendor = 0x1002, - .second_device = 0x4385, - .second_card_vendor = 0x1458, - .second_card_device = 0x4385, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "GIGABYTE GA-MA78G-DS3H", - .enable = it87xx_probe_spi_flash, - }, - { - .first_vendor = 0x1039, - .first_device = 0x0761, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "gigabyte", - .lb_part = "2761gxdk", - .name = "GIGABYTE GA-2761GXDK", - .enable = it87xx_probe_spi_flash, - }, - { - .first_vendor = 0x1022, - .first_device = 0x7468, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "iwill", - .lb_part = "dk8_htx", - .name = "IWILL DK8-HTX", - .enable = w83627hf_gpio24_raise_2e, - }, - { - .first_vendor = 0x10de, - .first_device = 0x005e, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "msi", - .lb_part = "k8n-neo3", - .name = "MSI K8N Neo3", - .enable = w83627thf_gpio4_4_raise_4e, - }, - { - .first_vendor = 0x1022, - .first_device = 0x746B, - .first_card_vendor = 0x1022, - .first_card_device = 0x36C0, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "AGAMI", - .lb_part = "ARUMA", - .name = "agami Aruma", - .enable = w83627hf_gpio24_raise_2e, - }, - { - .first_vendor = 0x1106, - .first_device = 0x3177, - .first_card_vendor = 0x1106, - .first_card_device = 0xAA01, - .second_vendor = 0x1106, - .second_device = 0x3123, - .second_card_vendor = 0x1106, - .second_card_device = 0xAA01, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "VIA EPIA M/MII/...", - .enable = board_via_epia_m, - }, - { - .first_vendor = 0x1106, - .first_device = 0x3177, - .first_card_vendor = 0x1043, - .first_card_device = 0x80A1, - .second_vendor = 0x1106, - .second_device = 0x3205, - .second_card_vendor = 0x1043, - .second_card_device = 0x8118, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "ASUS A7V8-MX SE", - .enable = board_asus_a7v8x_mx, - }, - { - .first_vendor = 0x1106, - .first_device = 0x3227, - .first_card_vendor = 0x1106, - .first_card_device = 0xAA01, - .second_vendor = 0x1106, - .second_device = 0x0259, - .second_card_vendor = 0x1106, - .second_card_device = 0xAA01, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "VIA EPIA SP", - .enable = board_via_epia_sp, - }, - { - .first_vendor = 0x1106, - .first_device = 0x0314, - .first_card_vendor = 0x1106, - .first_card_device = 0xaa08, - .second_vendor = 0x1106, - .second_device = 0x3227, - .second_card_vendor = 0x1106, - .second_card_device = 0xAA08, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "VIA EPIA-CN", - .enable = board_via_epia_sp, - }, - { - .first_vendor = 0x8086, - .first_device = 0x1076, - .first_card_vendor = 0x8086, - .first_card_device = 0x1176, - .second_vendor = 0x1106, - .second_device = 0x3059, - .second_card_vendor = 0x10f1, - .second_card_device = 0x2498, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "Tyan Tomcat K7M", - .enable = board_asus_a7v8x_mx, - }, - { - .first_vendor = 0x10B9, - .first_device = 0x1541, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x10B9, - .second_device = 0x1533, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "asus", - .lb_part = "p5a", - .name = "ASUS P5A", - .enable = board_asus_p5a, - }, - { - .first_vendor = 0x1166, - .first_device = 0x0205, - .first_card_vendor = 0x1014, - .first_card_device = 0x0347, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "ibm", - .lb_part = "x3455", - .name = "IBM x3455", - .enable = board_ibm_x3455, - }, - { - .first_vendor = 0x8086, - .first_device = 0x7110, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x8086, - .second_device = 0x7190, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "epox", - .lb_part = "ep-bx3", - .name = "EPoX EP-BX3", - .enable = board_epox_ep_bx3, - }, - { - .first_vendor = 0x8086, - .first_device = 0x1130, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x105a, - .second_device = 0x0d30, - .second_card_vendor = 0x105a, - .second_card_device = 0x4d33, - .lb_vendor = "acorp", - .lb_part = "6a815epd", - .name = "Acorp 6A815EPD", - .enable = board_acorp_6a815epd, - }, - { - .first_vendor = 0x1022, - .first_device = 0x2090, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x1022, - .second_device = 0x2080, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "artecgroup", - .lb_part = "dbe61", - .name = "Artec Group DBE61", - .enable = board_artecgroup_dbe6x, - }, - { - .first_vendor = 0x1022, - .first_device = 0x2090, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x1022, - .second_device = 0x2080, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "artecgroup", - .lb_part = "dbe62", - .name = "Artec Group DBE62", - .enable = board_artecgroup_dbe6x, - }, + /* first pci-id set [4], second pci-id set [4], coreboot id [2], boardname, flash enable */ + {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI KT4V", board_msi_kt4v}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS P4B266", ich2_gpio22_raise}, + {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash}, + {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash}, + {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4385, 0x1458, 0x4385, NULL, NULL, "GIGABYTE GA-MA78G-DS3H", it87xx_probe_spi_flash}, + {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK", it87xx_probe_spi_flash}, + {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e}, + {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e}, + {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx}, + {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA EPIA SP", board_via_epia_sp}, + {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA EPIA-CN", board_via_epia_sp}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx}, + {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS P5A", board_asus_p5a}, + {0x1166, 0x0205, 0x1014, 0x0347, 0, 0, 0, 0, "ibm", "x3455", "IBM x3455", board_ibm_x3455}, + {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3}, + {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x}, + {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x}, /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */ - { - .first_vendor = 0x8086, - .first_device = 0x27b8, - .first_card_vendor = 0x0000, - .first_card_device = 0x0000, - .second_vendor = 0x0000, - .second_device = 0x0000, - .second_card_vendor = 0x0000, - .second_card_device = 0x0000, - .lb_vendor = "kontron", - .lb_part = "986lcd-m", - .name = "Kontron 986LCD-M", - .enable = board_kontron_986lcd_m, - }, - { - .first_vendor = 0x10ec, - .first_device = 0x8168, - .first_card_vendor = 0x10ec, - .first_card_device = 0x8168, - .second_vendor = 0x104c, - .second_device = 0x8023, - .second_card_vendor = 0x104c, - .second_card_device = 0x8019, - .lb_vendor = "kontron", - .lb_part = "986lcd-m", - .name = "Kontron 986LCD-M", - .enable = board_kontron_986lcd_m, - }, - { - .first_vendor = 0x1106, - .first_device = 0x3149, - .first_card_vendor = 0x1565, - .first_card_device = 0x3206, - .second_vendor = 0x1106, - .second_device = 0x3344, - .second_card_vendor = 0x1565, - .second_card_device = 0x1202, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "BioStar P4M80-M4", - .enable = board_biostar_p4m80_m4, - }, - { - .first_vendor = 0x1106, - .first_device = 0x3227, - .first_card_vendor = 0x1458, - .first_card_device = 0x5001, - .second_vendor = 0x10ec, - .second_device = 0x8139, - .second_card_vendor = 0x1458, - .second_card_device = 0xe000, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "GIGABYTE GA-7VT600", - .enable = board_biostar_p4m80_m4, - }, - { - .first_vendor = 0x1106, - .first_device = 0x3149, - .first_card_vendor = 0x1462, - .first_card_device = 0x7094, - .second_vendor = 0x10ec, - .second_device = 0x8167, - .second_card_vendor = 0x1462, - .second_card_device = 0x094c, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "MSI K8T Neo2", - .enable = w83627thf_gpio4_4_raise_2e, - }, - { - .first_vendor = 0x1039, - .first_device = 0x5513, - .first_card_vendor = 0x8086, - .first_card_device = 0xd61f, - .second_vendor = 0x1039, - .second_device = 0x6330, - .second_card_vendor = 0x8086, - .second_card_device = 0xd61f, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "Intel Desktop Board D201GLY", - .enable = wbsio_check_for_spi, - }, - { - .first_vendor = 0x8086, - .first_device = 0x2658, - .first_card_vendor = 0x1462, - .first_card_device = 0x7046, - .second_vendor = 0x1106, - .second_device = 0x3044, - .second_card_vendor = 0x1462, - .second_card_device = 0x046d, - .lb_vendor = NULL, - .lb_part = NULL, - .name = "MSI MS-7046", - .enable = ich6_gpio19_raise, - }, - { - .first_vendor = 0x1166, - .first_device = 0x0223, - .first_card_vendor = 0x103c, - .first_card_device = 0x320d, - .second_vendor = 0x102b, - .second_device = 0x0522, - .second_card_vendor = 0x103c, - .second_card_device = 0x31fa, - .lb_vendor = "hp", - .lb_part = "dl145_g3", - .name = "HP DL145 G3", - .enable = board_hp_dl145_g3_enable, - }, - { - .first_vendor = 0x1106, - .first_device = 0x5337, - .first_card_vendor = 0x1458, - .first_card_device = 0xb003, - .second_vendor = 0x1106, - .second_device = 0x287e, - .second_card_vendor = 0x1106, - .second_card_device = 0x337e, - .lb_vendor = "via", - .lb_part = "pc3500g", - .name = "VIA PC3500G", - .enable = it87xx_probe_spi_flash, - }, - { - .first_vendor = 0, - .first_device = 0, - .first_card_vendor = 0, - .first_card_device = 0, - .second_vendor = 0, - .second_device = 0, - .second_card_vendor = 0, - .second_card_device = 0, - .lb_vendor = NULL, - .lb_part = NULL, - } /* Keep this */ + {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m}, + {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m}, + {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "BioStar P4M80-M4", board_biostar_p4m80_m4}, + {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, + {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, "Intel D201GLY", wbsio_check_for_spi}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI MS-7046", ich6_gpio19_raise}, + {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, "hp", "dl145_g3", "HP DL145 G3", board_hp_dl145_g3_enable}, + {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA PC3500G", it87xx_probe_spi_flash}, + { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL}, /* end marker */ }; void print_supported_boards(void)

1 0

[v2] r4141 - trunk/util/flashrom
by svn＠coreboot.org 20 Apr '09

20 Apr '09

Author: stuge Date: 2009-04-20 14:34:30 +0200 (Mon, 20 Apr 2009) New Revision: 4141 Modified: trunk/util/flashrom/README Log: flashrom: Trivial README change Flashrom->flashrom Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/README =================================================================== --- trunk/util/flashrom/README 2009-04-20 12:02:25 UTC (rev 4140) +++ trunk/util/flashrom/README 2009-04-20 12:34:30 UTC (rev 4141) @@ -1,8 +1,8 @@ ------------------------------------------------------------------------------- -Flashrom README +flashrom README ------------------------------------------------------------------------------- -Flashrom is a utility for reading, writing, and erasing flash ROM chips. +flashrom is a utility for reading, writing, and erasing flash ROM chips. It's often used to flash BIOS/coreboot/firmware images. It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and @@ -51,14 +51,14 @@ Exit status ----------- -Flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem +flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. coreboot Table and Mainboard Identification -------------------------------------------- -Flashrom reads the coreboot table to determine the current mainboard. If no +flashrom reads the coreboot table to determine the current mainboard. If no coreboot table could be read or if you want to override these values, you can specify -m, e.g.: @@ -72,7 +72,7 @@ ROM Layout Support ------------------ -Flashrom supports ROM layouts. This allows you to flash certain parts of +flashrom supports ROM layouts. This allows you to flash certain parts of the flash chip only. A ROM layout file looks like follows: 00000000:00008fff gfxrom

1 0

build service results for r4140
by coreboot information 20 Apr '09

20 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4140 to the coreboot repository. This caused the following changes: Change Log: Fix implicit declarations of done_cache_as_ram_main by adding a prototype for these assembler functions. Affected boards: digitallogic/msm800sev pcengines/alix1c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:msm800sev has been fixed Compilation of pcengines:alix1c has been fixed If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH] Fix implicit declarations
by Carl-Daniel Hailfinger 20 Apr '09

20 Apr '09

Fix implicit declarations of done_cache_as_ram_main by adding a prototype for these assembler functions. Affected boards: digitallogic/msm800sev pcengines/alix1c With this patch, there are no more compile errors in the tree. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: coreboot-v2-fix_implicit_declarations/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c =================================================================== --- coreboot-v2-fix_implicit_declarations/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c (revision 4122) +++ coreboot-v2-fix_implicit_declarations/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c (working copy) @@ -114,5 +114,6 @@ /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ + void done_cache_as_ram_main(void); done_cache_as_ram_main(); } Index: coreboot-v2-fix_implicit_declarations/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- coreboot-v2-fix_implicit_declarations/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c (revision 4122) +++ coreboot-v2-fix_implicit_declarations/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c (working copy) @@ -206,5 +206,6 @@ * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ + void done_cache_as_ram_main(void); done_cache_as_ram_main(); } -- http://www.hailfinger.org/ Index: coreboot-v2-fix_implicit_declarations/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c =================================================================== --- coreboot-v2-fix_implicit_declarations/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c (revision 4122) +++ coreboot-v2-fix_implicit_declarations/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c (working copy) @@ -114,5 +114,6 @@ /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ + void done_cache_as_ram_main(void); done_cache_as_ram_main(); } Index: coreboot-v2-fix_implicit_declarations/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- coreboot-v2-fix_implicit_declarations/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c (revision 4122) +++ coreboot-v2-fix_implicit_declarations/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c (working copy) @@ -206,5 +206,6 @@ * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ + void done_cache_as_ram_main(void); done_cache_as_ram_main(); }

2 2

[v2] r4140 - in trunk/coreboot-v2/src/mainboard: digitallogic/msm800sev pcengines/alix1c
by svn＠coreboot.org 20 Apr '09

20 Apr '09

Author: hailfinger Date: 2009-04-20 14:02:25 +0200 (Mon, 20 Apr 2009) New Revision: 4140 Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c Log: Fix implicit declarations of done_cache_as_ram_main by adding a prototype for these assembler functions. Affected boards: digitallogic/msm800sev pcengines/alix1c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c 2009-04-19 23:24:26 UTC (rev 4139) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c 2009-04-20 12:02:25 UTC (rev 4140) @@ -114,5 +114,6 @@ /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ + void done_cache_as_ram_main(void); done_cache_as_ram_main(); } Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2009-04-19 23:24:26 UTC (rev 4139) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c 2009-04-20 12:02:25 UTC (rev 4140) @@ -206,5 +206,6 @@ * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ + void done_cache_as_ram_main(void); done_cache_as_ram_main(); }

1 0

[flashrom]MX25L1605A and MX25L1605D
by stephan.guilloux＠free.fr 20 Apr '09

20 Apr '09

Hello Anyone can tell me how to make the difference between the 1605A and the 1605D ? >From the datasheet, the "D" accept some more opcodes. Great, but, how to differenciate both ? I check the datasheets, but... see no differences in RDID or REMS. Stephan.

3 2

build service results for r4139
by coreboot information 19 Apr '09

19 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 4139 to the coreboot repository. This caused the following changes: Change Log: flashrom: MX25L1605 and 1635 accept Chip Erase opcodes 60 and C7 Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4139&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4139&device=alix1c&vendor=… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r4138
by coreboot information 19 Apr '09

19 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4138 to the coreboot repository. This caused the following changes: Change Log: Add MX25L1635D support, as discussed on #coreboot. Signed-off-by: Stephan Guilloux <stephan.guilloux(a)free.fr> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4138&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4138&device=alix1c&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

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