coreboot October 2009

coreboot@coreboot.org

63 participants
534 discussions

[PATCH] drivers vs. obj
by Myles Watson 23 Feb '10

23 Feb '10

On Thu, Sep 24, 2009 at 12:52 AM, Stefan Reinauer <stepan(a)coresystems.de>wrote: Myles Watson wrote: > Are there other differences? Should I2C devices use objects, since > you can't scan for them? Some structures defined in the code are put in an extra section in the binary for enumeration. Those are: #define __console __attribute__((used, __section__(".rodata.console_drivers"))) #define __cpu_driver __attribute__((used,__section__(".rodata.cpu_driver"))) #define __pci_driver __attribute__((used,__section__(".rodata.pci_driver"))) All others don't need to be "drivers" Stefan --------------- Based on that, here's a patch that changes drivers that aren't console, pci, or cpu, to obj. The most common one was mainboard.c as a driver. Boot tested with Tyan s2895. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles PS. It looks like the rtl8168 driver ought to go somewhere more general in the tree.

3 11

[PATCH] simplify keyboard "API"
by Stefan Reinauer 23 Feb '10

23 Feb '10

Not sure if this is such a good idea.. Opinions? See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 drop runtime configuration checking layer from the code. Don't check for errors we can't handle gracefully anyways. It's always better to try initializing the keyboard controller when IO in the device tree is != 0x60/0x64 than to just drop out. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: src/mainboard/emulation/qemu-x86/mainboard.c =================================================================== --- src/mainboard/emulation/qemu-x86/mainboard.c (revision 4842) +++ src/mainboard/emulation/qemu-x86/mainboard.c (working copy) @@ -24,7 +24,7 @@ /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); /* The PIRQ table is not working well for interrupt routing purposes. * so we'll just set the IRQ directly. Index: src/superio/winbond/w83627thf/superio.c =================================================================== --- src/superio/winbond/w83627thf/superio.c (revision 4842) +++ src/superio/winbond/w83627thf/superio.c (working copy) @@ -49,7 +49,7 @@ case W83627THF_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/winbond/w83977tf/superio.c =================================================================== --- src/superio/winbond/w83977tf/superio.c (revision 4842) +++ src/superio/winbond/w83977tf/superio.c (working copy) @@ -56,7 +56,7 @@ case W83977TF_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/winbond/w83627dhg/superio.c =================================================================== --- src/superio/winbond/w83627dhg/superio.c (revision 4842) +++ src/superio/winbond/w83627dhg/superio.c (working copy) @@ -59,7 +59,7 @@ case W83627DHG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/winbond/w83627thg/superio.c =================================================================== --- src/superio/winbond/w83627thg/superio.c (revision 4842) +++ src/superio/winbond/w83627thg/superio.c (working copy) @@ -48,7 +48,7 @@ case W83627THG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/winbond/w83627ehg/superio.c =================================================================== --- src/superio/winbond/w83627ehg/superio.c (revision 4842) +++ src/superio/winbond/w83627ehg/superio.c (working copy) @@ -124,7 +124,7 @@ case W83627EHG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case W83627EHG_HWM: res0 = find_resource(dev, PNP_IDX_IO0); Index: src/superio/winbond/w83627uhg/superio.c =================================================================== --- src/superio/winbond/w83627uhg/superio.c (revision 4842) +++ src/superio/winbond/w83627uhg/superio.c (working copy) @@ -113,7 +113,7 @@ case W83627UHG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/winbond/w83627hf/superio.c =================================================================== --- src/superio/winbond/w83627hf/superio.c (revision 4842) +++ src/superio/winbond/w83627hf/superio.c (working copy) @@ -116,7 +116,7 @@ case W83627HF_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case W83627HF_HWM: res0 = find_resource(dev, PNP_IDX_IO0); Index: src/superio/winbond/w83977f/superio.c =================================================================== --- src/superio/winbond/w83977f/superio.c (revision 4842) +++ src/superio/winbond/w83977f/superio.c (working copy) @@ -61,7 +61,7 @@ case W83977F_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/ite/it8712f/superio.c =================================================================== --- src/superio/ite/it8712f/superio.c (revision 4842) +++ src/superio/ite/it8712f/superio.c (working copy) @@ -78,7 +78,7 @@ res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); set_kbc_ps2_mode(); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case IT8712F_KBCM: /* TODO. */ break; Index: src/superio/ite/it8671f/superio.c =================================================================== --- src/superio/ite/it8671f/superio.c (revision 4842) +++ src/superio/ite/it8671f/superio.c (working copy) @@ -53,7 +53,7 @@ case IT8671F_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case IT8671F_KBCM: /* TODO. */ break; Index: src/superio/ite/it8716f/superio.c =================================================================== --- src/superio/ite/it8716f/superio.c (revision 4842) +++ src/superio/ite/it8716f/superio.c (working copy) @@ -112,7 +112,7 @@ case IT8716F_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/ite/it8673f/superio.c =================================================================== --- src/superio/ite/it8673f/superio.c (revision 4842) +++ src/superio/ite/it8673f/superio.c (working copy) @@ -55,7 +55,7 @@ case IT8673F_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case IT8673F_KBCM: /* TODO. */ break; Index: src/superio/ite/it8718f/superio.c =================================================================== --- src/superio/ite/it8718f/superio.c (revision 4842) +++ src/superio/ite/it8718f/superio.c (working copy) @@ -55,7 +55,7 @@ case IT8718F_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case IT8718F_KBCM: /* TODO. */ break; Index: src/superio/nsc/pc87366/superio.c =================================================================== --- src/superio/nsc/pc87366/superio.c (revision 4842) +++ src/superio/nsc/pc87366/superio.c (working copy) @@ -37,7 +37,7 @@ case PC87366_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/nsc/pc8374/superio.c =================================================================== --- src/superio/nsc/pc8374/superio.c (revision 4842) +++ src/superio/nsc/pc8374/superio.c (working copy) @@ -37,7 +37,7 @@ case PC8374_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/nsc/pc87351/superio.c =================================================================== --- src/superio/nsc/pc87351/superio.c (revision 4842) +++ src/superio/nsc/pc87351/superio.c (working copy) @@ -43,7 +43,7 @@ case PC87351_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/nsc/pc87360/superio.c =================================================================== --- src/superio/nsc/pc87360/superio.c (revision 4842) +++ src/superio/nsc/pc87360/superio.c (working copy) @@ -37,7 +37,7 @@ case PC87360_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/nsc/pc97307/superio.c =================================================================== --- src/superio/nsc/pc97307/superio.c (revision 4842) +++ src/superio/nsc/pc97307/superio.c (working copy) @@ -38,7 +38,7 @@ res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case PC97307_FDC: Index: src/superio/nsc/pc87309/superio.c =================================================================== --- src/superio/nsc/pc87309/superio.c (revision 4842) +++ src/superio/nsc/pc87309/superio.c (working copy) @@ -48,7 +48,7 @@ case PC87309_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/nsc/pc87417/superio.c =================================================================== --- src/superio/nsc/pc87417/superio.c (revision 4842) +++ src/superio/nsc/pc87417/superio.c (working copy) @@ -39,7 +39,7 @@ case PC87417_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/nsc/pc97317/superio.c =================================================================== --- src/superio/nsc/pc97317/superio.c (revision 4842) +++ src/superio/nsc/pc97317/superio.c (working copy) @@ -38,7 +38,7 @@ res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; #if 0 Index: src/superio/nsc/pc87427/superio.c =================================================================== --- src/superio/nsc/pc87427/superio.c (revision 4842) +++ src/superio/nsc/pc87427/superio.c (working copy) @@ -36,7 +36,7 @@ case PC87427_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/smsc/lpc47m10x/superio.c =================================================================== --- src/superio/smsc/lpc47m10x/superio.c (revision 4842) +++ src/superio/smsc/lpc47m10x/superio.c (working copy) @@ -152,7 +152,7 @@ case LPC47M10X2_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/smsc/fdc37m60x/superio.c =================================================================== --- src/superio/smsc/fdc37m60x/superio.c (revision 4842) +++ src/superio/smsc/fdc37m60x/superio.c (working copy) @@ -53,7 +53,7 @@ case FDC37M60X_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; case FDC37M60X_AUX: /* TODO. */ break; Index: src/superio/smsc/lpc47b272/superio.c =================================================================== --- src/superio/smsc/lpc47b272/superio.c (revision 4842) +++ src/superio/smsc/lpc47b272/superio.c (working copy) @@ -154,7 +154,7 @@ case LPC47B272_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } } Index: src/superio/smsc/smscsuperio/superio.c =================================================================== --- src/superio/smsc/smscsuperio/superio.c (revision 4842) +++ src/superio/smsc/smscsuperio/superio.c (working copy) @@ -230,7 +230,7 @@ } else if (ld == logical_device_table[i].devs[LD_KBC]) { res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); } } Index: src/superio/smsc/lpc47b397/superio.c =================================================================== --- src/superio/smsc/lpc47b397/superio.c (revision 4842) +++ src/superio/smsc/lpc47b397/superio.c (working copy) @@ -68,7 +68,7 @@ case LPC47B397_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + pc_keyboard_init(&conf->keyboard); break; } Index: src/northbridge/via/cx700/cx700_lpc.c =================================================================== --- src/northbridge/via/cx700/cx700_lpc.c (revision 4842) +++ src/northbridge/via/cx700/cx700_lpc.c (working copy) @@ -384,7 +384,7 @@ isa_dma_init(); /* Initialize keyboard controller */ - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); } static struct device_operations cx700_lpc_ops = { Index: src/northbridge/via/vx800/vx800_lpc.c =================================================================== --- src/northbridge/via/vx800/vx800_lpc.c (revision 4842) +++ src/northbridge/via/vx800/vx800_lpc.c (working copy) @@ -342,7 +342,7 @@ setup_i8259(); // make sure interupt controller is configured before keyboard init /* turn on keyboard and RTC, no need to visit this reg twice */ - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); printk_debug ("ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); Index: src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_lpc.c (revision 4842) +++ src/southbridge/via/vt8237r/vt8237r_lpc.c (working copy) @@ -615,7 +615,7 @@ { u8 regval = pci_read_config8(dev, 0x51); if (regval & 0x1) - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); } static void southbridge_init_common(struct device *dev) Index: src/southbridge/via/vt8231/vt8231.c =================================================================== --- src/southbridge/via/vt8231/vt8231.c (revision 4842) +++ src/southbridge/via/vt8231/vt8231.c (working copy) @@ -26,7 +26,7 @@ regval |= 0x0f; pci_write_config8(lpc_dev, 0x51, regval); } - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); } static void com_port_on(void) Index: src/southbridge/via/vt8235/vt8235.c =================================================================== --- src/southbridge/via/vt8235/vt8235.c (revision 4842) +++ src/southbridge/via/vt8235/vt8235.c (working copy) @@ -26,7 +26,7 @@ regval &= 0xfd; pci_write_config8(dev, 0x51, regval); - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); } void dump_south(device_t dev0) Index: src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- src/southbridge/sis/sis966/sis966_lpc.c (revision 4842) +++ src/southbridge/sis/sis966/sis966_lpc.c (working copy) @@ -171,7 +171,7 @@ int nmi_option; printk_debug("LPC_INIT -------->\n"); - init_pc_keyboard(0x60, 0x64, 0); + pc_keyboard_init(0); lpc_usb_legacy_init(dev); lpc_common_init(dev); Index: src/pc80/keyboard.c =================================================================== --- src/pc80/keyboard.c (revision 4842) +++ src/pc80/keyboard.c (working copy) @@ -159,7 +159,7 @@ return regval; } -static void pc_keyboard_init(struct pc_keyboard *keyboard) +void pc_keyboard_init(struct pc_keyboard *keyboard) { u8 regval; printk_debug("Keyboard init...\n"); @@ -242,16 +242,6 @@ } } - -void init_pc_keyboard(unsigned port0, unsigned port1, struct pc_keyboard *kbd) -{ - if ((port0 == 0x60) && (port1 == 0x64)) { - pc_keyboard_init(kbd); - } else { - printk_warning("Unsupported keyboard controller.\n"); - } -} - /* * Support PS/2 mode - oddball SIOs(KBC) need this setup * Not well documented. Google - 0xcb keyboard controller Index: src/include/pc80/keyboard.h =================================================================== --- src/include/pc80/keyboard.h (revision 4842) +++ src/include/pc80/keyboard.h (working copy) @@ -5,7 +5,7 @@ /* No initialization parameters for now */ }; -void init_pc_keyboard(unsigned port0, unsigned port1, struct pc_keyboard *kbd); +void pc_keyboard_init(struct pc_keyboard *keyboard); void set_kbc_ps2_mode(void); #endif /* PC80_KEYBOARD_H */

2 1

#104: flashrom: Change flash drivers to never erase data before writing
by coreboot 16 Jan '10

16 Jan '10

#104: flashrom: Change flash drivers to never erase data before writing ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase write | Dependencies: #103 Patchstatus: there is no patch | ---------------------------------+------------------------------------------ The user should be responsible for ensuring that the flash chip has been erased where new data should be written. At the moment, flashrom will erase at least one full page and then rewrite it, when the user asks to only write a few bytes using -l/-i/-s/-e. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104> coreboot <http://www.coreboot.org/>

2 18

#101: flashrom: Remove pciutils check from Makefile
by coreboot 16 Jan '10

16 Jan '10

#101: flashrom: Remove pciutils check from Makefile ---------------------------------------------+------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: pciutils libpci build ldflags | Dependencies: Patchstatus: patch needs review | ---------------------------------------------+------------------------------ The check belongs in a configure script or similar, the check also claims that packages can not be found for any build error, which is not good enough. Has confused more than one user already. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/101> coreboot <http://www.coreboot.org/>

3 6

#120: flashrom failure to read
by coreboot 16 Jan '10

16 Jan '10

#120: flashrom failure to read ---------------------------------+------------------------------------------ Reporter: toc@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Running flashrom -r rom.file results in an output file of all null bytes. Standard output: {{{ Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... tried to set 0xdc to 0x3 on Intel ICH9R failed (WARNING ONLY) FAILED! Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Reading flash... done. }}} Verbose output indicates failure of opcode 0x03. {{{ Reading flash... ich_spi_read_page: offset=0, number=256, buf=0xb7cf0008 Opcode 3 not found. run OPCODE 0x03 failed Error readingdone. }}} Full verbose output attached -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/120> coreboot <http://www.coreboot.org/>

1 25

#113: problem
by coreboot 16 Jan '10

16 Jan '10

#113: problem ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: adlo | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ there is a bug -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/113> coreboot <http://www.coreboot.org/>

1 6

#106: flashrom: Add -T to automatically test all flash chip operations
by coreboot 16 Jan '10

16 Jan '10

#106: flashrom: Add -T to automatically test all flash chip operations ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: testing | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Maybe require -f to actually perform the test, since it will potentially fail to restore the flash chip to it's original state. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/106> coreboot <http://www.coreboot.org/>

1 6

#141: flashrom: Warn the user when trying to read/write chips which are bigger than what the chipset can decode
by coreboot 16 Jan '10

16 Jan '10

#141: flashrom: Warn the user when trying to read/write chips which are bigger than what the chipset can decode ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: critical | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ We should make a table in the flashrom code which tells it how much a given (detected/supported) southbridge can decode. Then, if the user tries to read/write/erase/verify a chip which is _bigger_ (e.g. 512 KB) than what the southbridge can decode (e.g. 256 KB as on the AMD CS5530A for example) flashrom should at the very least warn the user, probably even bail out with an error. I've stumbled upon exactly this problem, trying to make a backup of a 512KB chip in an CS5530A system. I ended up with only one half of the contents (but duplicated) and it _did_ verify OK. That's because I did 'flashrom -r bak.bin' on the box (which effectively got me two equal, broken 256KB halves instead of one correct 512KB image). Then I did 'flashrom -wv bak.bin' onto the other 512KB chip, which also got the incorrect contents, _but_ flashrom said it verified fine (which is actually true) because both the bak.bin _and_ the written contents are crap. I only noticed what was going on after lots of debugging. I finally did a 'dd if=/dev/urandom of=rnd.dd bs=1024c count=512', then 'flashrom -wv rnd.dd' which then FAILED, because here the two 256KB-halves of the image were _not_ the same as in the above case. Then I compared 'hexdump -Cv rnd.dd' and 'flashrom -r readback.dd; hexdump -Cv readback.dd' outputs and noticed that bytes 0x0..0x40000 (256 KB) were _not_ the same, but the other 256 KB _were_ the same. Anyway, this is a nice way for data loss, so we should fix it by throwing an error in such cases. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/141> coreboot <http://www.coreboot.org/>

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#123: layout file
by coreboot 16 Jan '10

16 Jan '10

#123: layout file -------------------------------------+-------------------------------------- Reporter: vivanov@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: v2 Keywords: layout address offset | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- Hello, I am trying to update the BIOS "ST M50FW080" and get the following incomprehensibility - layout file works in a strange way 1) saved the current BIOS {{{ $ flashrom --read flash18_saved.rom }}} 2) then I filled first 512K of this file with zeros (it is needed because new BIOS will have 512K size) 3) then I created rom.layout file to use the normal image only: {{{ 00000000:0007ffff stuff 00080000:000fffff normal }}} 4) and started to upgrade BIOS {{{ $ flashrom --write --layout rom.layout --image flash18_saved.rom }}} And get the following: {{{ Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED '''0007 at address: 0x00070000DONE BLOCK 0x70000''' 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED }}} '''Next''' I changed the rom.layout file like follows: {{{ # cat rom.layout 00000000:00080000 stuff 00080000:000fffff normal }}} and get the '''right''' behaviour: {{{ # flashrom --write --layout rom.layout --image normal --verify flash18_saved.rom Looking for "normal"... found. Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH4/ICH4-L", enabling flash write... OK. Found chip "ST M50FW080" (1024 KB) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0000 at address: 0x00000000SKIPPED 0001 at address: 0x00010000SKIPPED 0002 at address: 0x00020000SKIPPED 0003 at address: 0x00030000SKIPPED 0004 at address: 0x00040000SKIPPED 0005 at address: 0x00050000SKIPPED 0006 at address: 0x00060000SKIPPED 0007 at address: 0x00070000SKIPPED 0008 at address: 0x00080000SKIPPED 0009 at address: 0x00090000SKIPPED 0010 at address: 0x000a0000SKIPPED 0011 at address: 0x000b0000SKIPPED 0012 at address: 0x000c0000SKIPPED 0013 at address: 0x000d0000SKIPPED 0014 at address: 0x000e0000SKIPPED 0015 at address: 0x000f0000SKIPPED Verifying flash... VERIFIED. }}} Please explain me which rom layout I should use to update the last 512K of 1M BIOS? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/123> coreboot <http://www.coreboot.org/>

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#133: Create a typical failures FAQ
by coreboot 16 Jan '10

16 Jan '10

#133: Create a typical failures FAQ ---------------------------------------+------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: faq documentation debug | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ Briefly describe what flashrom needs to do to successfully identify, read and write/erase the different type of chips to optimize the remote debugging process with new users. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/133> coreboot <http://www.coreboot.org/>

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