coreboot October 2009

coreboot@coreboot.org

63 participants
534 discussions

#130: flashrom segfault (with backtrace)
by coreboot 16 Jan '10

16 Jan '10

#130: flashrom segfault (with backtrace) ---------------------------------+------------------------------------------ Reporter: fragabr@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I want to test flashrom with a supported motherboard (Asus M2N-E with Linux 2.6.30-rc4) and it segfaults when I run it. I'm using the latest libpci (3.1.2): {{{ Calibrating delay loop... OK. No coreboot table found. Segmentation fault }}} Backtrace: {{{ #0 0x00007f1395141d49 in pci_fill_info_v31 () from /usr/local/lib/libpci.so.3 #1 0x00007f1395143c59 in pci_filter_match () from /usr/local/lib/libpci.so.3 #2 0x000000000040732f in ?? () #3 0x00000000004016f8 in ?? () #4 0x0000000000406d46 in ?? () #5 0x00007f1394df24f6 in __libc_start_main () from /lib64/libc.so.6 #6 0x0000000000401619 in ?? () #7 0x00007fff9d579e98 in ?? () #8 0x000000000000001c in ?? () #9 0x0000000000000001 in ?? () #10 0x00007fff9d57ab55 in ?? () #11 0x0000000000000000 in ?? () }}} -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/130> coreboot <http://www.coreboot.org/>

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#140: flashrom: Consistently use stderr for error printing
by coreboot 16 Jan '10

16 Jan '10

#140: flashrom: Consistently use stderr for error printing ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ We're not very consistent with error printing in flashrom. Many errors go to stdout instead of stderr. We should fix that by using fprintf(stderr, "Foo") where needed. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/140> coreboot <http://www.coreboot.org/>

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#144: TYAN S7012 support
by coreboot 16 Jan '10

16 Jan '10

#144: TYAN S7012 support --------------------------------------------------------+------------------- Reporter: john@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: TYAN S7012 Intel ICH10R SST SST25VF032B | Dependencies: Patchstatus: there is no patch | --------------------------------------------------------+------------------- I'm unable to flash a system that runs on a TYAN S7012 motherboard. # flashrom -w bios.bin flashrom v0.9.0-r659 No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF032B" (4096 KB, SPI) at physical address 0xffc00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... COMPLETE. Verifying flash... VERIFY FAILED at 0x00002000! Expected=0x00, Read=0xff Running it with verbose the following error messages are printed out (repeating). Writing flash chip... Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP Transaction error! run OPCODE 0x02 failed spi_byte_program failed during command execution Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP Transaction error! run OPCODE 0x02 failed spi_byte_program failed during command execution Invalid OPCODE 0x06 CONFIG_STRICT_DEVMEM is not set in my kernel. Anything I should try out? -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/144> coreboot <http://www.coreboot.org/>

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[PATCH] ACPI updates + S3 Resume without hole at 31MB
by Stefan Reinauer 10 Nov '09

10 Nov '09

See patch. This works nicely on two i945 machines I have here (unfortunately not the Kontron 986lcd-m due to some other reason) Probably needs some fixing for the AMD board that Rudolf got running with Resume. Rudolf, can you jump in, I don't have that hardware.. Stefan * Simplify acpi_add_table * fix some comments * Simplify ACPI wakeup code and make it work without a memory hole * Add resume entries to global GDT so we don't need our own for resume. * add ECDT description to acpi.h for anyone who might need it ;-) * remove rather stupid math to get the right number of MAX_ACPI_TABLES and just define a reasonable maximum for now. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: src/arch/i386/boot/acpi.c =================================================================== --- src/arch/i386/boot/acpi.c (revision 4861) +++ src/arch/i386/boot/acpi.c (working copy) @@ -18,7 +18,8 @@ * write_acpi_tables() * acpi_dump_apics() * - * See AMD Solo, Island Aruma or Via Epia-M port for more details. + * See Kontron 986LCD-M port for a good example of an ACPI implementation + * in coreboot. */ #include <console/console.h> @@ -26,6 +27,7 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <device/pci.h> +#include <cbmem.h> u8 acpi_checksum(u8 *table, u32 length) { @@ -37,54 +39,67 @@ return -ret; } -/* - * add an acpi table to rsdt structure, and recalculate checksum +/** + * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length and checksum */ void acpi_add_table(acpi_rsdp_t *rsdp, void *table) { - int i; + int i, entries_num; acpi_rsdt_t *rsdt; acpi_xsdt_t *xsdt = NULL; + /* The RSDT is mandatory ... */ rsdt = (acpi_rsdt_t *)rsdp->rsdt_address; + + /* ... while the XSDT is not */ if (rsdp->xsdt_address) { xsdt = (acpi_xsdt_t *)((u32)rsdp->xsdt_address); } - int entries_num = ARRAY_SIZE(rsdt->entry); + /* This should always be MAX_ACPI_TABLES */ + entries_num = ARRAY_SIZE(rsdt->entry); - for (i=0; i<entries_num; i++) { - if(rsdt->entry[i]==0) { - rsdt->entry[i]=(u32)table; - /* fix length to stop kernel whining about invalid entries */ - rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i+1)); - /* fix checksum */ - /* hope this won't get optimized away */ - rsdt->header.checksum=0; - rsdt->header.checksum=acpi_checksum((u8 *)rsdt, - rsdt->header.length); + for (i = 0; i < entries_num; i++) { + if(rsdt->entry[i] == 0) + break; + } - /* And now the same thing for the XSDT. We use the same - * index as we want the XSDT and RSDT to always be in - * sync in coreboot. - */ - if (xsdt) { - xsdt->entry[i]=(u64)(u32)table; - xsdt->header.length = sizeof(acpi_header_t) + - (sizeof(u64) * (i+1)); - xsdt->header.checksum=0; - xsdt->header.checksum=acpi_checksum((u8 *)xsdt, - xsdt->header.length); - } - - printk_debug("ACPI: added table %d/%d Length now %d\n", - i+1, entries_num, rsdt->header.length); - return; - } + if (i >= entries_num) { + printk_err("ACPI: Error: Could not add ACPI table, too many tables.\n"); + return; } - printk_err("ACPI: Error: Could not add ACPI table, too many tables.\n"); + /* Add table to the RSDT */ + rsdt->entry[i] = (u32)table; + + /* Fix RSDT length or the kernel will assume invalid entries */ + rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i+1)); + + /* Re-calculate checksum */ + rsdt->header.checksum = 0; /* Hope this won't get optimized away */ + rsdt->header.checksum = acpi_checksum((u8 *)rsdt, + rsdt->header.length); + + /* And now the same thing for the XSDT. We use the same index as for + * now we want the XSDT and RSDT to always be in sync in coreboot. + */ + if (xsdt) { + /* Add table to the XSDT */ + xsdt->entry[i]=(u64)(u32)table; + + /* Fix XSDT length */ + xsdt->header.length = sizeof(acpi_header_t) + + (sizeof(u64) * (i+1)); + + /* Re-calculate checksum */ + xsdt->header.checksum=0; + xsdt->header.checksum=acpi_checksum((u8 *)xsdt, + xsdt->header.length); + } + + printk_debug("ACPI: added table %d/%d Length now %d\n", + i+1, entries_num, rsdt->header.length); } int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) @@ -222,7 +237,8 @@ } /* this can be overriden by platform ACPI setup code, - if it calls acpi_create_ssdt_generator */ + * if it calls acpi_create_ssdt_generator + */ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { return current; @@ -559,10 +575,29 @@ extern char *lowmem_backup_ptr; extern int lowmem_backup_size; +#define WAKEUP_BASE 0x600 + +void (*acpi_do_wakeup)(u32 vector, u32 backup_source, u32 backup_target, u32 + backup_size) __attribute__((regparm(0))) = (void *)WAKEUP_BASE; + +extern unsigned char __wakeup, __wakeup_size; + void acpi_jump_to_wakeup(void *vector) { + u32 acpi_backup_memory = (u32) cbmem_find(CBMEM_ID_RESUME); + + if (!acpi_backup_memory) { + printk(BIOS_WARNING, "ACPI: Backup memory missing. No S3 Resume.\n"); + return; + } + + // FIXME this should go into the ACPI backup memory, too. No pork saussages. /* just restore the SMP trampoline and continue with wakeup on assembly level */ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); - acpi_jmp_to_realm_wakeup((u32) vector); + + /* copy wakeup trampoline in place */ + memcpy(WAKEUP_BASE, &__wakeup, &__wakeup_size); + + acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } #endif Index: src/arch/i386/boot/wakeup.S =================================================================== --- src/arch/i386/boot/wakeup.S (revision 4861) +++ src/arch/i386/boot/wakeup.S (working copy) @@ -2,10 +2,11 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License v2 as published by - * the Free Software Foundation. + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -16,76 +17,89 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - .text + +#define WAKEUP_BASE 0x600 +#define RELOCATED(x) (x - __wakeup + WAKEUP_BASE) + +/* CR0 bits */ +#define PE (1 << 0) + .code32 - .globl acpi_jmp_to_realm_wakeup - /* This function does the PM -> RM switch, but - it can run >1MB even in real mode */ - -acpi_jmp_to_realm_wakeup: - mov 0x4(%esp), %eax + .globl __wakeup +__wakeup: + /* First prepare the jmp to the resume vector */ + mov 0x4(%esp), %eax /* vector */ /* last 4 bits of linear addr are taken as offset */ andw $0x0f, %ax - movw %ax, (jmp_off) + movw %ax, (__wakeup_offset) mov 0x4(%esp), %eax /* the rest is taken as segment */ shr $4, %eax - movw %ax, (jmp_seg) - lgdt gdtaddr_wakeup - movl $0x008,%eax - mov %eax,%ds - movl %eax,%es - movl %eax,%ss - movl %eax,%fs - movl %eax,%gs - ljmp $0x0010,$reload_cs - .code16gcc -reload_cs: - /* switch off PE */ + movw %ax, (__wakeup_segment) + + /* Then overwrite coreboot with our backed up memory */ + movl 8(%esp), %esi + movl 12(%esp), %edi + movl 16(%esp), %ecx + shrl $4, %ecx +1: + movl 0(%esi),%eax + movl 4(%esi),%edx + movl 8(%esi),%ebx + movl 12(%esi),%ebp + addl $16,%esi + subl $1,%ecx + movl %eax,0(%edi) + movl %edx,4(%edi) + movl %ebx,8(%edi) + movl %ebp,12(%edi) + leal 16(%edi),%edi + jne 1b + + /* Activate the right segment descriptor real mode. */ + ljmp $0x28, $RELOCATED(1f) +1: +.code16 + /* 16 bit code from here on... */ + + /* Load the segment registers w/ properly configured + * segment descriptors. They will retain these + * configurations (limits, writability, etc.) once + * protected mode is turned off. + */ + mov $0x30, %ax + mov %ax, %ds + mov %ax, %es + mov %ax, %fs + mov %ax, %gs + mov %ax, %ss + + /* Turn off protection */ movl %cr0, %eax - andb $0xfe,%al + andl $~PE, %eax movl %eax, %cr0 - ljmpl $0x0, $cpu_flushed -cpu_flushed: + + /* Now really going into real mode */ + ljmp $0, $RELOCATED(1f) +1: movw $0x0, %ax movw %ax, %ds movw %ax, %es movw %ax, %ss movw %ax, %fs movw %ax, %gs - /* far jump to OS waking vector. The linear addr is changed to SEG and OFFSET - check ACPI specs or above code for details */ + + /* This is a FAR JMP to the OS waking vector. The C code changed + * the address to be correct. + */ .byte 0xea -jmp_off: - .word 0 -jmp_seg: - .word 0 -.code32 -gdt_wakeup_limit = gdt_wakeup_end - gdt_wakeup - 1 /* compute the table limit */ - gdtaddr_wakeup: - .word gdt_wakeup_limit /* the table limit */ - .long gdt_wakeup /* we know the offset */ +__wakeup_offset = RELOCATED(.) + .word 0x0000 - .data +__wakeup_segment = RELOCATED(.) + .word 0x0000 - /* This is the gdt for GCC part of coreboot. - * It is different from the gdt in ROMCC/ASM part of coreboot - * which is defined in entry32.inc */ -gdt_wakeup: - /* selgdt 0, unused */ - .word 0x0000, 0x0000 /* dummy */ - .byte 0x00, 0x00, 0x00, 0x00 + .globl __wakeup_size +__wakeup_size = ( . - __wakeup) - /* selgdt 8, flat data segment 16bit */ - .word 0x0000, 0x0000 /* dummy */ - .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ - - /* selgdt 0x10, flat code segment 16bit */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ - -gdt_wakeup_end: - - .previous -.code32 Index: src/arch/i386/include/arch/acpi.h =================================================================== --- src/arch/i386/include/arch/acpi.h (revision 4861) +++ src/arch/i386/include/arch/acpi.h (working copy) @@ -1,16 +1,27 @@ /* * coreboot ACPI Support - headers and defines. - * + * * written by Stefan Reinauer <stepan(a)coresystems.de> * Copyright (C) 2004 SUSE LINUX AG + * Copyright (C) 2004 Nick Barker * Copyright (C) 2008-2009 coresystems GmbH * - * The ACPI table structs are based on the Linux kernel sources. - * ACPI FADT & FACS added by Nick Barker <nick.barker9(a)btinternet.com> - * those parts (C) 2004 Nick Barker + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA */ - #ifndef __ASM_ACPI_H #define __ASM_ACPI_H @@ -48,6 +59,12 @@ u32 addrh; } __attribute__ ((packed)) acpi_addr_t; +#define ACPI_ADDRESS_SPACE_MEMORY 0 +#define ACPI_ADDRESS_SPACE_IO 1 +#define ACPI_ADDRESS_SPACE_PCI 2 +#define ACPI_ADDRESS_SPACE_FIXED 0x7f + + /* Generic ACPI Header, provided by (almost) all tables */ typedef struct acpi_table_header /* ACPI common table header */ @@ -63,13 +80,9 @@ u32 asl_compiler_revision; /* ASL compiler revision number */ } __attribute__ ((packed)) acpi_header_t; -/* FIXME: This is very fragile: - * MCONFIG, HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU - * pstate - */ +/* A maximum number of 32 ACPI tables ought to be enough for now */ +#define MAX_ACPI_TABLES 32 -#define MAX_ACPI_TABLES (7 + CONFIG_ACPI_SSDTX_NUM + CONFIG_MAX_CPUS) - /* RSDT */ typedef struct acpi_rsdt { struct acpi_table_header header; @@ -330,6 +343,16 @@ // #define ACPI_FACS_S4BIOS_F (1 << 0) +typedef struct acpi_ecdt { + struct acpi_table_header header; + struct acpi_gen_regaddr ec_control; + struct acpi_gen_regaddr ec_data; + u32 uid; + u8 gpe_bit; + u8 ec_id[]; +} __attribute__ ((packed)) acpi_ecdt_t; + + /* These are implemented by the target port */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); @@ -382,7 +405,7 @@ void suspend_resume(void); void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); -void acpi_jmp_to_realm_wakeup(u32 linear_addr); +void acpi_jmp_to_realm_wakeup(u32 linear_addr) __attribute__((regparm(0))); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); Index: src/arch/i386/lib/c_start.S =================================================================== --- src/arch/i386/lib/c_start.S (revision 4861) +++ src/arch/i386/lib/c_start.S (working copy) @@ -253,7 +253,16 @@ /* This is the gdt for GCC part of coreboot. * It is different from the gdt in ROMCC/ASM part of coreboot - * which is defined in entry32.inc */ /* BUT WHY?? */ + * which is defined in entry32.inc + * + * When the machine is initially started, we use a very simple + * gdt from rom (that in entry32.inc) which only contains those + * entries we need for protected mode. + * + * When we're executing code from RAM, we want to do more complex + * stuff, like initializing PCI option roms in real mode, or doing + * a resume from a suspend to ram. + */ gdt: /* selgdt 0, unused */ .word 0x0000, 0x0000 /* dummy */ @@ -275,6 +284,8 @@ .word 0x0000, 0x0000 /* dummy */ .byte 0x00, 0x00, 0x00, 0x00 + /* The next two entries are used for executing VGA option ROMs */ + /* selgdt 0x28 16-bit 64k code at 0x00000000 */ .word 0xffff, 0x0000 .byte 0, 0x9a, 0, 0 @@ -282,6 +293,16 @@ /* selgdt 0x30 16-bit 64k data at 0x00000000 */ .word 0xffff, 0x0000 .byte 0, 0x92, 0, 0 + + /* The next two entries are used for ACPI S3 RESUME */ + + /* selgdt 0x38, flat data segment 16bit */ + .word 0x0000, 0x0000 /* dummy */ + .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + + /* selgdt 0x40, flat code segment 16bit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ gdt_end: idtarg:

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[PATCH] WPCD376I Super I/O support
by Sean Young 09 Nov '09

09 Nov '09

On the Intel DG33TL motherboard, the Super I/O is an WPCD376I. Output: # ./superiotool -d Found Winbond WPCD376I (sid=0xf1, srid=0x91) at 0x2e Register dump: idx 10 12 13 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 00 00 00 f1 91 00 00 c0 01 00 91 00 91 00 00 00 00 00 00 def 00 00 00 f1 11 00 00 00 RR 00 MM RR 01 2e RR RR RR RR RR LDN 0x00 (Floppy) idx 30 60 61 70 71 74 75 f0 f1 f8 val 00 00 00 06 03 02 04 24 00 24 def 00 03 f2 06 03 02 04 24 00 24 LDN 0x01 (Parallel port) idx 30 60 61 70 71 74 75 f0 f8 val 00 00 00 07 02 04 04 92 04 def 00 02 78 07 02 04 04 f2 07 LDN 0x02 (IR) idx 30 60 61 70 71 74 75 f0 val 00 00 00 03 03 04 04 02 def 00 02 f8 03 03 04 04 02 LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 02 def 00 03 f8 04 03 04 04 02 LDN 0x04 (System wake-up control (SWC)) idx 30 50 60 61 62 63 70 71 74 75 val 01 00 06 d0 06 c0 00 03 04 04 def 00 00 00 00 00 00 00 03 04 04 LDN 0x05 (Mouse) idx 30 70 71 74 75 val 01 0c 02 04 04 def 00 0c 02 04 04 LDN 0x06 (Keyboard) idx 30 60 61 62 63 70 71 74 75 f0 val 01 00 60 00 64 01 02 04 04 40 def 00 00 60 00 64 01 02 04 04 40 LDN 0x07 (GPIO) idx 30 50 60 61 70 71 74 75 f0 f1 f2 f3 f8 val 01 00 06 80 00 03 04 04 07 00 00 00 00 def 00 00 00 00 00 03 04 04 00 MM 00 MM 01 Signed-off-by: Sean Young <sean(a)mess.org> Index: nsc.c =================================================================== --- nsc.c (revision 4887) +++ nsc.c (working copy) @@ -400,7 +400,7 @@ {EOT}}}, {0xf0, "PC87372", { {EOT}}}, - {0xf1, "PC8374L", { + {0x0f1, "PC8374L", { {NOLDN, NULL, {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26, 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, @@ -442,6 +442,45 @@ {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x05,EOT}}, {EOT}}}, + {0x8f1, "WPCD376I", { + {NOLDN, NULL, + {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26, + 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x00,0xf1,0x11,0x00,0x00,0x00,RSVD,0x00, + MISC,RSVD,0x01,0x2e,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf8, + EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,0x24, + EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf8,EOT}, + {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,0x07,EOT}}, + {0x2, "IR", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x4, "System wake-up control (SWC)", + {0x30,0x50,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04, + EOT}}, + {0x5, "Mouse", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x02,0x04,0x04,EOT}}, + {0x6, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40, + EOT}}, + {0x7, "GPIO", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1, + 0xf2,0xf3,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC, + 0x00,MISC,0x01,EOT}}, + {EOT}}}, {0xf2, "PC87427", { /* SRID[7..5] is marked as "not applicable for the PC87427". */ {NOLDN, NULL, @@ -512,6 +551,7 @@ void probe_idregs_nsc(uint16_t port) { uint8_t id, rev; + int16_t magic; probing_for("NSC", "", port); @@ -532,17 +572,28 @@ rev = INB(port + 1); } - if (superio_unknown(reg_table, id)) { + /* + * NSC PC8374L has id 0xf1, rev 0b000x xxxx according to datasheet + * Winbond WPCD376I has id 0xf1, rev 0b100x xxxx according to datasheet + */ + if (id == 0xf1) + magic = ((rev & 0xe0) << 4) | id; + else + magic = id; + + if (superio_unknown(reg_table, magic)) { if (verbose) printf(NOTFOUND "sid=0x%02x, srid=0x%02x\n", id, rev); return; } - printf("Found NSC %s (sid=0x%02x, srid=0x%02x) at 0x%x\n", - get_superio_name(reg_table, id), id, rev, port); + printf("Found %s %s (sid=0x%02x, srid=0x%02x) at 0x%x\n", + magic == 0x8f1 ? "Winbond" : "NSC", + get_superio_name(reg_table, magic), id, rev, port); chip_found = 1; - dump_superio("NSC", reg_table, port, id, LDN_SEL); + dump_superio(magic == 0x8f1 ? "Winbond" : "NSC", + reg_table, port, magic, LDN_SEL); } void print_nsc_chips(void)

2 3

Re: [coreboot] grub as coreboot payload
by Robert Millan 09 Nov '09

09 Nov '09

On Mon, Oct 26, 2009 at 09:20:53PM +0100, Andreas B. Mundt wrote: > Hi, > > first, congratulations to the 1.97-release! > > I vainly tried to run the latest grub2 (Revision: 2663) as payload to > coreboot (Revision: 4852) following the wikipage: > > http://grub.enbug.org/CoreBoot > > Is this page still up to date and does anybody use grub2 as payload > successfully? How? Hi, It appears that since r4534 (move to Kconfig), Multiboot information is no longer built in by default. You have to enable it in "System tables" / "Generate Multiboot tables (for GRUB2)", then GRUB works fine (at least on QEMU, which I just tested). Coreboot developers: would you consider enabling it again? The overhead is minimal, and it would make this less confusing for users. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

4 5

[PATCH]cbfs locate function
by Patrick Georgi 09 Nov '09

09 Nov '09

Hi, attached patch adds a "locate" function cbfstool, which helps you find out a suitable address to put a XIP stage to. Specifically, you pass it the file (to get its filesize), its filename (as the header has a variable length that depends on it), and the granularity requirement it has to fit in (for XIP). The granularity is MTRR-style: when you request 0x10000, cbfstool looks for a suitable place in a 64kb-aligned 64kb block. cbfstool simply prints out a hex value which is the start address of a suitably located free memory block. That value can then be used with cbfs add-stage to store the file in the ROM image. I need this function for my "newfailover" project, which will push most of the current bootblock code into CBFS (everything but enable_rom). It's a two-step operation (instead of being merged into cbfs add-stage) because the image must be linked twice: First, with some bogus, but safe base address (eg. 0) to figure out the target address (based on file size). Then a second time at the target address. The approximative code flow is: link file, cbfstool locate, link file again, cbfstool add-stage. I'm not quite sure about the failure modes yet, so all it does for now is returning an address of "0" if no suitable place could be found. Maybe returning "1" is a better idea, as "0" is the value used when cbfstool add-stage can freely choose the location. "1" should already lead to an error. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

2 2

[PATCH] Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb
by Uwe Hermann 06 Nov '09

06 Nov '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

5 9

[PATCH] __ROMCC__ ifdefs
by Myles Watson 06 Nov '09

06 Nov '09

I think it's time to separate the two meanings of __ROMCC__. Right now it is used for: 1. Use simple functions and data types since we don't have RAM 2. Don't use prototypes, romcc doesn't support them. Right now the patch creates __PRE_RAMINIT__ The name is not the most important part of the patch, and can easily be changed. Here are some of the suggestions so far: __PRE_RAM__ __NO_RAM_YET__ __DURING_RAMINIT__ __USE_NO_RAM__ Unless it was obvious to me which meaning was the correct one for a file, I added both for now. Abuild tested. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 3

[PATCH] Various x86emu fixes
by Mark Marshall 06 Nov '09

06 Nov '09

Below are three small patches, they all seemed useful while I have been working with VGA option ROMs. Thanks for the great work. MM

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coreboot October 2009