coreboot October 2009

coreboot@coreboot.org

63 participants
534 discussions

build service results for r4811
by coreboot information 19 Oct '09

19 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4811 to the coreboot repository. This caused the following changes: Change Log: Fix builds of amd/db800 and digitallogic/msm800sev with smaller bootblocks. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of digitallogic:msm800sev has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Re: [coreboot] [v2] r4806 - in trunk/coreboot-v2/src: cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/socket_F_1207 mainboard/amd/serengeti_cheetah_fam10 mainboard/kontron/kt690 mainboard/supermicro/x6dhe_g mainboard/supermicro/x6dhe_g2 mainboard/tyan/
by Myles Watson 19 Oct '09

19 Oct '09

On Sun, Oct 18, 2009 at 7:47 AM, <svn(a)coreboot.org> wrote: > Author: uwe > Date: 2009-10-18 15:47:30 +0200 (Sun, 18 Oct 2009) > New Revision: 4806 > > Modified: > trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig > trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig > trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig > trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig > trunk/coreboot-v2/src/mainboard/kontron/kt690/Kconfig > trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Kconfig > trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Kconfig > trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig > trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig > trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig > trunk/coreboot-v2/src/northbridge/amd/lx/Kconfig > trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig > Log: > Simplify Kconfig files by using "select" where possible (trivial). > Care needs to be taken that select doesn't break things. It has no effect and fails silently when the CONFIG_* isn't defined. > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-18 > 13:42:50 UTC (rev 4805) > +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-18 > 13:47:30 UTC (rev 4806) > @@ -20,20 +20,12 @@ > config NORTHBRIDGE_AMD_AMDFAM10 > bool > select HAVE_HIGH_TABLES > + select HYPERTRANSPORT_PLUGIN_SUPPORT > + select HT3_SUPPORT > > HT3_SUPPORT is no longer defined. I think this is the right place to put it since it is the only northbridge that supports HT3. I guess it could go in src/devices/Kconfig by HYPERTRANSPORT_PLUGIN_SUPPORT, but the code there doesn't use it. Either way it needs to be defined somewhere. Thanks, Myles

1 0

build service results for r4810
by coreboot information 19 Oct '09

19 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4810 to the coreboot repository. This caused the following changes: Change Log: Unselect AP_CODE_IN_CAR in tyan/s289x. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4810&device=msm800sev&vend… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[sassmann@redhat.com: boot interrupts - the next step]
by Peter Stuge 19 Oct '09

19 Oct '09

This from linux-kernel today. I'm glad to see this forward thinking. :) //Peter ----- Forwarded message from Stefan Assmann <sassmann(a)redhat.com> ----- From: Stefan Assmann <sassmann(a)redhat.com> To: Linux Kernel Mailing List <linux-kernel(a)vger.kernel.org> CC: linux-acpi(a)vger.kernel.org, andi(a)firstfloor.org, Arjan van de Ven <arjan(a)infradead.org>, Ingo Molnar <mingo(a)elte.hu>, Jon Masters <jcm(a)redhat.com>, Len Brown <lenb(a)kernel.org>, tokunaga.keiich(a)jp.fujitsu.com, Olaf Dabrunz <Olaf.Dabrunz(a)gmx.net>, greg(a)kroah.com Subject: boot interrupts - the next step Date: Mon, 19 Oct 2009 12:31:15 +0200 Hi all, boot interrupts are a major pain for linux interrupt handling. I'm not going into detail here, explaining it all over again. In case you want to know more refer to the links below. http://lkml.org/lkml/2009/9/4/350 http://lkml.org/lkml/2008/6/2/269 http://people.redhat.com/sassmann/publications/boot_irq_quirks_rtlws10.pdf http://people.redhat.com/sassmann/publications/Boot_Interrupts_and_IRQ_Thre… While we're still fighting this chipset generations boot interrupts there's something we can do to prevent next gens chipsets from generating these. Therefore we need support from BIOS people. In fact ACPI has a method to "report to the BIOS the current interrupt model used by the OS"¹. That method is called _PIC. So calling _PIC(1) tells the BIOS the OS has chosen to run in APIC mode and gives the BIOS the possibility to make adjustments. Now that is where the BIOS should _disable_ all sources of boot interrupts. As the implementation of how to disable boot interrupts is really chipset specific it's the BIOSes task to disable them in the APIC mode case. All the boot interrupt quirks we've been adding to the kernel are just workarounds for buggy BIOSes! An example of how this can look like, taken from the AMD SB700/710/750 BIOS developers guide²: During the BIOS POST, the BIOS will do normal PCI IRQ routing through port C00h/C01h. Once APIC is fully enabled by the OS, the routing in C00h/C01 must be all cleared to zero. The following is a sample ASL code that may be incorporated into the BIOS: Name(PICF,0x00) Method(_PIC, 0x01, NotSerialized) { Store (Arg0, PICF) If(Arg0) { \_SB.PCI0.LPC0.DSPI() // clear interrupt at 0xC00/0xC01 } } [...] (full implementation snipped) Note: 0xC00/0xC01 are the PCI interrupt mapping registers in this case. It's not that hard to do once you're aware of it. This is a call to all chipset manufacturers/BIOS developers/everyone involved: Please get the appropriate changes into your BIOS/BIOS developers guide! Thanks! ¹ ACPI Specification 4.0 (sec 5.8.1) ² http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf (sec 10.5) Stefan -- Stefan Assmann | Red Hat GmbH Software Engineer | Otto-Hahn-Strasse 20, 85609 Dornach | HR: Amtsgericht Muenchen HRB 153243 | GF: Brendan Lane, Charlie Peters, sassmann at redhat.com | Michael Cunningham, Charles Cachera -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo(a)vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ ----- End forwarded message -----

1 0

[v2] r4811 - in trunk/coreboot-v2/src/mainboard: amd/db800 digitallogic/msm800sev
by svn＠coreboot.org 19 Oct '09

19 Oct '09

Author: myles Date: 2009-10-19 18:58:51 +0200 (Mon, 19 Oct 2009) New Revision: 4811 Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb Log: Fix builds of amd/db800 and digitallogic/msm800sev with smaller bootblocks. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-10-19 16:48:32 UTC (rev 4810) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-10-19 16:58:51 UTC (rev 4811) @@ -97,7 +97,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 32768 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-10-19 16:48:32 UTC (rev 4810) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-10-19 16:58:51 UTC (rev 4811) @@ -97,7 +97,7 @@ ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_ROM_IMAGE_SIZE = 32768 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ##

1 0

build service results for r4809
by coreboot information 19 Oct '09

19 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4809 to the coreboot repository. This caused the following changes: Change Log: Clean up some #ifdef CONFIG_* Change HAVE_FAN_CTL to be specific to the SuperIO that supports it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:db800 has been fixed Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4809&device=msm800sev&vend… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

2 1

[v2] r4810 - in trunk/coreboot-v2/src/mainboard/tyan: s2891 s2892 s2895
by svn＠coreboot.org 19 Oct '09

19 Oct '09

Author: myles Date: 2009-10-19 18:48:32 +0200 (Mon, 19 Oct 2009) New Revision: 4810 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig Log: Unselect AP_CODE_IN_CAR in tyan/s289x. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-19 16:21:30 UTC (rev 4809) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-19 16:48:32 UTC (rev 4810) @@ -11,7 +11,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SERIAL_CPU_INIT - select AP_CODE_IN_CAR select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-19 16:21:30 UTC (rev 4809) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-19 16:48:32 UTC (rev 4810) @@ -11,7 +11,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SERIAL_CPU_INIT - select AP_CODE_IN_CAR select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-19 16:21:30 UTC (rev 4809) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-19 16:48:32 UTC (rev 4810) @@ -11,7 +11,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SERIAL_CPU_INIT - select AP_CODE_IN_CAR select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024

1 0

[PATCH] ifdef & config problems
by Myles Watson 19 Oct '09

19 Oct '09

Try to make CONFIG_ options more standard. config_console.diff: #ifdef->#if fan_ctl.diff: make CONFIG_HAVE_FANCTL specific to the SuperIO that supports it vt8237r.diff: #ifdef->#if Config options used with #ifdef makes it so your board can break silently when someone makes a simple change in Kconfig. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[v2] r4809 - in trunk/coreboot-v2/src: arch/i386/boot config cpu/x86/mtrr mainboard/gigabyte/m57sli northbridge/amd/amdk8 northbridge/intel/i82810 northbridge/via/cx700 southbridge/via/vt8237r superio/ite/it8716f
by svn＠coreboot.org 19 Oct '09

19 Oct '09

Author: myles Date: 2009-10-19 18:21:30 +0200 (Mon, 19 Oct 2009) New Revision: 4809 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c trunk/coreboot-v2/src/superio/ite/it8716f/superio.c Log: Clean up some #ifdef CONFIG_* Change HAVE_FAN_CTL to be specific to the SuperIO that supports it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -99,7 +99,7 @@ static struct lb_serial *lb_serial(struct lb_header *header) { -#if defined(CONFIG_TTYS0_BASE) +#if CONFIG_CONSOLE_SERIAL8250 struct lb_record *rec; struct lb_serial *serial; rec = lb_new_record(header); @@ -126,22 +126,22 @@ static void lb_console(struct lb_header *header) { -#ifdef CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL8250 add_console(header, LB_TAG_CONSOLE_SERIAL8250); #endif -#ifdef CONFIG_CONSOLE_VGA +#if CONFIG_CONSOLE_VGA add_console(header, LB_TAG_CONSOLE_VGA); #endif -#ifdef CONFIG_CONSOLE_BTEXT +#if CONFIG_CONSOLE_BTEXT add_console(header, LB_TAG_CONSOLE_BTEXT); #endif -#ifdef CONFIG_CONSOLE_LOGBUF +#if CONFIG_CONSOLE_LOGBUF add_console(header, LB_TAG_CONSOLE_LOGBUF); #endif -#ifdef CONFIG_CONSOLE_SROM +#if CONFIG_CONSOLE_SROM add_console(header, LB_TAG_CONSOLE_SROM); #endif -#ifdef CONFIG_USBDEBUG_DIRECT +#if CONFIG_USBDEBUG_DIRECT add_console(header, LB_TAG_CONSOLE_EHCI); #endif } Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-19 16:21:30 UTC (rev 4809) @@ -712,8 +712,8 @@ comment "PCIBIOS IRQ support" end define CONFIG_IOAPIC - default none - export used + default 0 + export always comment "IOAPIC support" end @@ -845,7 +845,7 @@ # Misc device options ############################################### -define CONFIG_HAVE_FANCTL +define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL default 0 export used comment "Include board specific FAN control initialization" @@ -1103,14 +1103,14 @@ end define CONFIG_VIDEO_MB - default none - export used + default 0 + export always comment "Integrated graphics with UMA has dynamic setup" end define CONFIG_GFXUMA - default none - export used + default 0 + export always comment "GFX UMA" end Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -37,7 +37,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> -#ifdef CONFIG_GFXUMA +#if CONFIG_GFXUMA extern uint64_t uma_memory_base, uma_memory_size; #endif Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-10-19 16:21:30 UTC (rev 4809) @@ -150,7 +150,7 @@ end end -if CONFIG_HAVE_FANCTL +if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL object fanctl.o end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-19 16:21:30 UTC (rev 4809) @@ -7,6 +7,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_ITE_IT8716F + select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select USE_PRINTK_IN_CAR @@ -143,9 +144,3 @@ int default 11 depends on BOARD_GIGABYTE_M57SLI - -# not globally defined yet, so can't "select" this -config HAVE_FANCTL - bool - default y - depends on BOARD_GIGABYTE_M57SLI Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-19 16:21:30 UTC (rev 4809) @@ -29,7 +29,7 @@ obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o -obj-$(CONFIG_HAVE_FANCTL) += fanctl.o +obj-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.o # This is part of the conversion to init-obj and away from included code. initobj-y += crt0.o Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-19 16:21:30 UTC (rev 4809) @@ -115,7 +115,7 @@ uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_HAVE_FANCTL +uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL ### ### Build options ### @@ -141,7 +141,7 @@ ## ## Set-up automatic fan control ## -default CONFIG_HAVE_FANCTL=1 +default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1 ## ## Build code for the fallback boot Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -357,7 +357,7 @@ resource->gran = log2(HT_MEM_HOST_ALIGN); resource->limit = 0xffffffffffULL; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; -#ifdef CONFIG_PCI_64BIT_PREF_MEM +#if CONFIG_PCI_64BIT_PREF_MEM resource->flags |= IORESOURCE_BRIDGE; #endif } Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -147,7 +147,7 @@ /* Convert tomk from MB to KB. */ tomk = tomk << 10; -#ifdef CONFIG_VIDEO_MB +#if CONFIG_VIDEO_MB /* Check for VGA reserved memory. */ if (CONFIG_VIDEO_MB == 512) { tomk -= 512; Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/raminit.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -371,7 +371,7 @@ /* Set size for onboard-VGA framebuffer. */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM); reg8 &= 0x3f; /* Disable graphics (for now). */ -#ifdef CONFIG_VIDEO_MB +#if CONFIG_VIDEO_MB if (CONFIG_VIDEO_MB == 512) reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */ else if (CONFIG_VIDEO_MB == 1) Modified: trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/northbridge/via/cx700/cx700_lpc.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -37,7 +37,7 @@ #define HPET_ADDR 0xfe800000UL #define IOAPIC_ADDR 0xfec00000ULL -#ifdef CONFIG_IOAPIC +#if CONFIG_IOAPIC struct ioapicreg { unsigned int reg; unsigned int value_low, value_high; @@ -368,7 +368,7 @@ { cx700_set_lpc_registers(dev); -#ifdef CONFIG_IOAPIC +#if CONFIG_IOAPIC setup_ioapic(); #endif Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_ide.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -97,7 +97,7 @@ (sb->ide1_80pin_cable << 4); pci_write_config32(dev, IDE_UDMA, cablesel); -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Set PATA Output Drive Strength */ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -51,7 +51,7 @@ extern void dump_south(device_t dev); static void southbridge_init_common(struct device *dev); -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Interrupts for INT# A B C D */ static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; @@ -119,7 +119,7 @@ ioapic_table[0].value_high = (lapicid()) << (56 - 32); l = (u32 *)ioapic_base; -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Set APIC to APIC Serial bus. */ l[0] = 0x3; l[4] = 0; @@ -157,7 +157,7 @@ /** Set up PCI IRQ routing, route everything through APIC. */ static void pci_routing_fixup(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT device_t pdev; u8 reg; #endif @@ -171,7 +171,7 @@ /* Gate Interrupts until RAM Writes are flushed */ pci_write_config8(dev, 0x49, 0x20); -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ pci_write_config8(dev, 0x46, 0x00); @@ -256,7 +256,7 @@ /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ pci_write_config16(dev, 0x84, 0x3052); #else @@ -288,7 +288,7 @@ * 0 = USB Wakeup */ -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else pci_write_config8(dev, 0x95, 0xcc); @@ -343,7 +343,7 @@ { u8 enables, reg8; -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT printk_spew("Entering vt8237r_init, for EPIA.\n"); /* * TODO: Looks like stock BIOS can do this but causes a hang @@ -386,7 +386,7 @@ enables |= 0x08; pci_write_config8(dev, 0x4f, enables); -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* * Set Read Pass Write Control Enable */ @@ -401,7 +401,7 @@ southbridge_init_common(dev); -#ifndef CONFIG_EPIA_VT8237R_INIT +#if !CONFIG_EPIA_VT8237R_INIT /* FIXME: Intel needs more bit set for C2/C3. */ /* @@ -460,7 +460,7 @@ pci_write_config8(dev, PCI_COMMAND, byte); /* EPIA-N(L) Uses CN400 for BIOS Access */ -#ifndef CONFIG_EPIA_VT8237R_INIT +#if !CONFIG_EPIA_VT8237R_INIT /* Enable the internal I/O decode. */ enables = pci_read_config8(dev, 0x6C); enables |= 0x80; @@ -499,7 +499,7 @@ /* Delay transaction control */ pci_write_config8(dev, 0x43, 0xb); -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT /* I/O recovery time, default IDE routing */ pci_write_config8(dev, 0x4c, 0x04); Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_nic.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -27,7 +27,7 @@ static void vt8237_eth_read_resources(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT struct resource *res; /* Fix the I/O Resources of the USB2.0 Interface */ Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_usb.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -24,14 +24,14 @@ #include <device/pci_ids.h> #include "vt8237r.h" -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; #endif static void usb_i_init(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT u8 reg8; printk_debug("Entering %s\n", __func__); @@ -70,7 +70,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT struct resource *res; u8 function = (u8) dev->path.pci.devfn & 0x7; @@ -95,7 +95,7 @@ static void usb_ii_init(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT u8 reg8; printk_debug("Entering %s\n", __func__); @@ -117,7 +117,7 @@ static void vt8237_usb_ii_read_resources(struct device *dev) { -#ifdef CONFIG_EPIA_VT8237R_INIT +#if CONFIG_EPIA_VT8237R_INIT struct resource *res; /* Fix the I/O Resources of the USB2.0 Interface */ Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2009-10-18 18:35:50 UTC (rev 4808) +++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2009-10-19 16:21:30 UTC (rev 4809) @@ -51,7 +51,7 @@ pnp_write_config(dev, 0x02, 0x02); } -#ifdef CONFIG_HAVE_FANCTL +#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL extern void init_ec(uint16_t base); #else static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value)

1 0

[PATCH] Updated vx800 patch, NOT merge-ready
by Uwe Hermann 19 Oct '09

19 Oct '09

This is an updated version of the VX800 patch from http://www.coreboot.org/pipermail/coreboot/2009-July/050785.html It contains the following changes to make it build (vx800example board): - Add CONFIG_ prefix to lots of variables (I may have missed some). - Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP (which is in bytes not KB now). - Fix acpi_write_rsdp() call (not enough parameters). - ram/ramtest.c moved to lib/ramtest.c. - Renames a la s/HAVE_ACPI_TABLES/CONFIG_GENERATE_ACPI_TABLES/ etc. - Disable ACPI table stuff for now, doesn't build yet. - Disable CONFIG_HAVE_ACPI_RESUME for now. - Disable CONFIG_GENERATE_ACPI_TABLES for now. - Drop no longer available variables: - CONFIG_MAX_PCI_BUSES - CONFIG_CBFS - CONFIG_ROM_PAYLOAD_START - PAYLOAD_SIZE - Disable vga.o in Config.lb for now, doesn't build. - Comment out acpi_slp_type usage for now, won't build otherwise. - Drop Config-abuild.lb, it's not needed (abuild works fine). IMPORTANT: This patch should not be merged as is (yet), it will definately break the VIA EPIA-M700 target and also has lots of whitespace breakage in it which I want to remove first (will post updated patch). Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

← Newer
1
...
22
23
24
25
26
27
28
...
54
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2009