coreboot October 2009

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[PATCH] Improve coreboot build output and eliminate some warnings
by Uwe Hermann 27 Oct '09

27 Oct '09

Build-tested on ASUS P2B-F where 80% of the warnings are now gone. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4874 - in trunk/coreboot-v2: . src/arch/i386/boot src/arch/i386/lib src/console src/devices src/include/device src/northbridge/intel/i440bx src/southbridge/intel/i82371eb util/romcc util/sconfig util/x86emu
by svn＠coreboot.org 27 Oct '09

27 Oct '09

Author: uwe Date: 2009-10-27 22:49:33 +0100 (Tue, 27 Oct 2009) New Revision: 4874 Modified: trunk/coreboot-v2/Makefile trunk/coreboot-v2/src/arch/i386/boot/gdt.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c trunk/coreboot-v2/src/console/vsprintf.c trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/devices/pci_device.c trunk/coreboot-v2/src/devices/pciexp_device.c trunk/coreboot-v2/src/include/device/device.h trunk/coreboot-v2/src/include/device/pci.h trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_ide.c trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c trunk/coreboot-v2/util/romcc/romcc.c trunk/coreboot-v2/util/sconfig/config.g trunk/coreboot-v2/util/sconfig/parsedesc.g trunk/coreboot-v2/util/sconfig/yapps2.py trunk/coreboot-v2/util/x86emu/x86.c Log: Improve coreboot build output and eliminate some warnings: - Add static and const where possible. - Turn some #warning entries into TODO comments. - Add missing prototypes. - Remove unused variables. - Fix printf arguments or cast them as needed. - Make sconfig output look better. Drop useless "PARSED THE TREE" output. - Print "(this may take a while)" while building romcc. Add missing "\n". Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watosn <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/Makefile =================================================================== --- trunk/coreboot-v2/Makefile 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/Makefile 2009-10-27 21:49:33 UTC (rev 4874) @@ -311,7 +311,7 @@ awk '/^#define ([^"])* ([^"])*$$/ {print $$2 " = " $$3 ";";}' $< > $@ $(obj)/romcc: $(top)/util/romcc/romcc.c - @printf " HOSTCC romcc" + @printf " HOSTCC romcc (this may take a while)\n" $(HOSTCC) -g -O2 -Wall -o $@ $< .PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot Modified: trunk/coreboot-v2/src/arch/i386/boot/gdt.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/gdt.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/arch/i386/boot/gdt.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -47,11 +47,11 @@ printk(BIOS_ERR, "Error: Could not relocate GDT.\n"); return; } - printk_debug("Moving GDT to %#lx...", newgdt); + printk_debug("Moving GDT to %p...", newgdt); memcpy((void*)newgdt, &gdt, num_gdt_bytes); } - gdtarg.base = newgdt; + gdtarg.base = (u32)newgdt; gdtarg.limit = num_gdt_bytes - 1; __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -191,7 +191,7 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) post_code(0x9d); - high_table_pointer = cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE); if (high_table_pointer) { unsigned long new_high_table_pointer; @@ -202,7 +202,7 @@ if (new_high_table_pointer > (high_table_pointer + MAX_COREBOOT_TABLE_SIZE)) - printk_err("%s: coreboot table didn't fit (%llx)\n", + printk_err("%s: coreboot table didn't fit (%lx)\n", __func__, new_high_table_pointer - high_table_pointer); Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/arch/i386/lib/pci_ops_auto.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -43,7 +43,7 @@ struct pci_bus_operations *pci_bus_fallback_ops = NULL; -const struct pci_bus_operations *pci_check_direct(void) +static const struct pci_bus_operations *pci_check_direct(void) { unsigned int tmp; @@ -86,7 +86,7 @@ const struct pci_bus_operations *pci_remember_direct(void) { if (!pci_bus_fallback_ops) - pci_bus_fallback_ops = pci_check_direct(); + pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct(); return pci_bus_fallback_ops; } Modified: trunk/coreboot-v2/src/console/vsprintf.c =================================================================== --- trunk/coreboot-v2/src/console/vsprintf.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/console/vsprintf.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -48,6 +48,8 @@ return i; } +int sprintf(char *buf, const char *fmt, ...); + int sprintf(char *buf, const char *fmt, ...) { va_list args; Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/devices/device.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -671,8 +671,11 @@ device_t vga_pri = 0; static void set_vga_bridge_bits(void) { -#warning "FIXME modify set_vga_bridge so it is less pci centric!" -#warning "This function knows too much about PCI stuff, it should be just a iterator/visitor." + /* + * FIXME: Modify set_vga_bridge so it is less PCI centric! + * This function knows too much about PCI stuff, it should be just + * an iterator/visitor. + */ /* FIXME: Handle the VGA palette snooping. */ struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last; Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/devices/pci_device.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -809,7 +809,7 @@ for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { if ((driver->vendor == dev->vendor) && (driver->device == dev->device)) { - dev->ops = driver->ops; + dev->ops = (struct device_operations *)driver->ops; printk_spew("%s [%04x/%04x] %sops\n", dev_path(dev), driver->vendor, driver->device, Modified: trunk/coreboot-v2/src/devices/pciexp_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pciexp_device.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/devices/pciexp_device.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -34,8 +34,8 @@ /* error... */ return; } - printk_debug("PCIe: tuning %s\n", dev_path(dev)); -#warning "IMPLEMENT PCI EXPRESS TUNING" + // printk_debug("PCIe: tuning %s\n", dev_path(dev)); + /* TODO: Implement PCI Express tuning. */ } unsigned int pciexp_scan_bus(struct bus *bus, Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/include/device/device.h 2009-10-27 21:49:33 UTC (rev 4874) @@ -86,7 +86,7 @@ unsigned int links; struct device_operations *ops; - struct chip_operations *chip_ops; + const struct chip_operations *chip_ops; void *chip_info; }; Modified: trunk/coreboot-v2/src/include/device/pci.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci.h 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/include/device/pci.h 2009-10-27 21:49:33 UTC (rev 4874) @@ -38,7 +38,7 @@ }; struct pci_driver { - struct device_operations *ops; + const struct device_operations *ops; unsigned short vendor; unsigned short device; }; Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/northbridge.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -85,7 +85,6 @@ pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; if (mc_dev) { - uint16_t tolm_r; unsigned long tomk, tolmk; int idx; @@ -98,7 +97,7 @@ /* Convert to KB. */ tomk *= (8 * 1024); - printk_debug("Setting RAM size to %d MB\n", tomk / 1024); + printk_debug("Setting RAM size to %ld MB\n", tomk / 1024); /* Compute the top of low memory. */ tolmk = pci_tolm / 1024; Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_ide.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_ide.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -144,7 +144,7 @@ } /* Intel 82371FB/SB */ -static struct device_operations ide_ops_fb_sb = { +static const struct device_operations ide_ops_fb_sb = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, @@ -155,7 +155,7 @@ }; /* Intel 82371AB/EB/MB */ -static struct device_operations ide_ops_ab_eb_mb = { +static const struct device_operations ide_ops_ab_eb_mb = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -69,7 +69,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -const struct device_operations isa_ops = { +static const struct device_operations isa_ops = { .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, Modified: trunk/coreboot-v2/util/romcc/romcc.c =================================================================== --- trunk/coreboot-v2/util/romcc/romcc.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/util/romcc/romcc.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -23843,12 +23843,12 @@ long ref; ref = next_label(state); fprintf(fp, ".section \"" DATA_SECTION "\"\n"); - fprintf(fp, ".balign %ld\n", align_of_in_bytes(state, ins->type)); + fprintf(fp, ".balign %ld\n", (long int)align_of_in_bytes(state, ins->type)); fprintf(fp, "L%s%lu:\n", state->compiler->label_prefix, ref); print_const(state, ins, fp); fill_bytes = bits_to_bytes(size - size_of(state, ins->type)); if (fill_bytes) { - fprintf(fp, ".fill %ld, 1, 0\n", fill_bytes); + fprintf(fp, ".fill %ld, 1, 0\n", (long int)fill_bytes); } fprintf(fp, ".section \"" TEXT_SECTION "\"\n"); return ref; @@ -24657,7 +24657,7 @@ struct triple *ins, FILE *fp) { fprintf(fp, ".section \"" DATA_SECTION "\"\n"); - fprintf(fp, ".balign %ld\n", align_of_in_bytes(state, ins->type)); + fprintf(fp, ".balign %ld\n", (long int)align_of_in_bytes(state, ins->type)); fprintf(fp, "L%s%lu:\n", state->compiler->label_prefix, (unsigned long)(ins->u.cval)); print_const(state, MISC(ins, 0), fp); Modified: trunk/coreboot-v2/util/sconfig/config.g =================================================================== --- trunk/coreboot-v2/util/sconfig/config.g 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/util/sconfig/config.g 2009-10-27 21:49:33 UTC (rev 4874) @@ -886,7 +886,7 @@ def writecode(image): filename = os.path.join(img_dir, "static.c") - print "Creating", filename + print " SCONFIG Creating", os.path.basename(filename) file = safe_open(filename, 'w+') file.write("#include <device/device.h>\n") file.write("#include <device/pci.h>\n") @@ -920,7 +920,7 @@ def writegraph(image): filename = os.path.join(img_dir, "static.dot") - print "Creating", filename + print " SCONFIG Creating", os.path.basename(filename) file = safe_open(filename, 'w+') file.write("digraph devicetree {\n") file.write(" rankdir=LR\n") @@ -1015,7 +1015,6 @@ fp = safe_open(config_file, 'r') if (not parse('devicetree', fp.read())): fatal("Could not parse file") - print "PARSED THE TREE" partstack.pop() img_dir = argv[3] Modified: trunk/coreboot-v2/util/sconfig/parsedesc.g =================================================================== --- trunk/coreboot-v2/util/sconfig/parsedesc.g 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/util/sconfig/parsedesc.g 2009-10-27 21:49:33 UTC (rev 4874) @@ -126,8 +126,8 @@ if inputfilename[-2:]=='.g': outputfilename = inputfilename[:-2]+'.py' else: raise "Invalid Filename", outputfilename - print 'Input Grammar:', inputfilename - print 'Output File:', outputfilename + print ' SCONFIG Input Grammar:', os.path.basename(inputfilename) + print ' SCONFIG Output File:', os.path.basename(outputfilename) DIVIDER = '\n%%\n' # This pattern separates the pre/post parsers preparser, postparser = None, None # Code before and after the parser desc Modified: trunk/coreboot-v2/util/sconfig/yapps2.py =================================================================== --- trunk/coreboot-v2/util/sconfig/yapps2.py 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/util/sconfig/yapps2.py 2009-10-27 21:49:33 UTC (rev 4874) @@ -18,6 +18,7 @@ from string import * from yappsrt import * import re +import os.path INDENT = " "*4 @@ -709,8 +710,8 @@ if inputfilename[-2:]=='.g': outputfilename = inputfilename[:-2]+'.py' else: raise "Invalid Filename", outputfilename - print 'Input Grammar:', inputfilename - print 'Output File:', outputfilename + print ' SCONFIG Input Grammar:', os.path.basename(inputfilename) + print ' SCONFIG Output File:', os.path.basename(outputfilename) DIVIDER = '\n%%\n' # This pattern separates the pre/post parsers preparser, postparser = None, None # Code before and after the parser desc Modified: trunk/coreboot-v2/util/x86emu/x86.c =================================================================== --- trunk/coreboot-v2/util/x86emu/x86.c 2009-10-27 16:24:22 UTC (rev 4873) +++ trunk/coreboot-v2/util/x86emu/x86.c 2009-10-27 21:49:33 UTC (rev 4874) @@ -149,6 +149,14 @@ u32 ebp, u32 esp, u32 ebx, u32 edx, u32 ecx, u32 eax, + u32 cs_ip, u16 stackflags); + +int __attribute__((regparm(0))) interrupt_handler(u32 intnumber, + u32 gsfs, u32 dses, + u32 edi, u32 esi, + u32 ebp, u32 esp, + u32 ebx, u32 edx, + u32 ecx, u32 eax, u32 cs_ip, u16 stackflags) { u32 ip;

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[v2] r4873 - in trunk/coreboot-v2/src: cpu/amd/mtrr lib
by svn＠coreboot.org 27 Oct '09

27 Oct '09

Author: myles Date: 2009-10-27 17:24:22 +0100 (Tue, 27 Oct 2009) New Revision: 4873 Modified: trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c trunk/coreboot-v2/src/lib/cbmem.c Log: Remove redundant declarations. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c 2009-10-27 15:53:27 UTC (rev 4872) +++ trunk/coreboot-v2/src/cpu/amd/mtrr/amd_mtrr.c 2009-10-27 16:24:22 UTC (rev 4873) @@ -101,8 +101,6 @@ } -extern void enable_fixed_mtrr(void); - void amd_setup_mtrrs(void) { unsigned long address_bits; Modified: trunk/coreboot-v2/src/lib/cbmem.c =================================================================== --- trunk/coreboot-v2/src/lib/cbmem.c 2009-10-27 15:53:27 UTC (rev 4872) +++ trunk/coreboot-v2/src/lib/cbmem.c 2009-10-27 16:24:22 UTC (rev 4873) @@ -176,7 +176,6 @@ } #ifndef __ROMCC__ -void cbmem_arch_init(void); #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif

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[PATCH] smm files in top directory
by Myles Watson 27 Oct '09

27 Oct '09

Add $(obj) paths for a couple of smm files so they don't end up in the top directory. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4872 - trunk/coreboot-v2/src/cpu/x86/smm
by svn＠coreboot.org 27 Oct '09

27 Oct '09

Author: myles Date: 2009-10-27 16:53:27 +0100 (Tue, 27 Oct 2009) New Revision: 4872 Modified: trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc Log: Add $(obj) paths for a couple of smm files so they don't end up in the top directory. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc 2009-10-27 14:29:29 UTC (rev 4871) +++ trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc 2009-10-27 15:53:27 UTC (rev 4872) @@ -33,12 +33,12 @@ $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions - $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o - $(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map - $(OBJCOPY) -O binary smm.elf smm + $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o + $(CONFIG_CROSS_COMPILE)nm -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map + $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm $(obj)/cpu/x86/smm/smm_bin.c: $(obj)/cpu/x86/smm/smm - (echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';') > $@ + (echo 'unsigned char smm[] = {'; od -vtx1 $(obj)/cpu/x86/smm/smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c $(obj)/cpu/x86/smm/smm |awk '{print $$1;}' ; echo ';') > $@ endif

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IBM ThinkPad X32 support status?
by intrigeri 27 Oct '09

27 Oct '09

Hello, I'd like to know the coreboot status for the IBM ThinkPad X32 [1] laptop. Please find, attached, the lspci, superiotool and flashrom output as asked in the FAQ. Thanks for your great work! [1] http://www-307.ibm.com/pc/support/site.wss/MIGR-59144.html Bye, -- intrigeri <intrigeri(a)boum.org> | GnuPG key @ https://gaffer.ptitcanardnoir.org/intrigeri/intrigeri.asc | OTR fingerprint @ https://gaffer.ptitcanardnoir.org/intrigeri/otr-fingerprint.asc flashrom v0.9.1-r736 No coreboot table found. Found chipset "Intel ICH4-M", enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 465M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0xb3, id2 0xb1 Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for AMD Am29F080B, 1024 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0x4e, id2 0x41 Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xdd, id2 0x7c Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xdd, id2 0x7c Probing for Intel 28F001BX-B, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Intel 28F001BX-T, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xdd, id2 0xb2 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x80, id2 0xfe Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x80, id2 0xfe Probing for PMC Pm39LV010, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x4e, id2 0x41 Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xdd, id2 0xb2 Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xdd, id2 0xb2 Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xbf, id2 0x5a Lock status for 0x000000 (size 0x010000) is 01, write locked Lock status for 0x010000 (size 0x010000) is 01, write locked Lock status for 0x020000 (size 0x010000) is 01, write locked Lock status for 0x030000 (size 0x010000) is 01, write locked Lock status for 0x040000 (size 0x010000) is 01, write locked Lock status for 0x050000 (size 0x010000) is 01, write locked Lock status for 0x060000 (size 0x010000) is 01, write locked Lock status for 0x070000 (size 0x010000) is 01, write locked Lock status for 0x080000 (size 0x010000) is 01, write locked Lock status for 0x090000 (size 0x010000) is 01, write locked Lock status for 0x0a0000 (size 0x010000) is 01, write locked Lock status for 0x0b0000 (size 0x010000) is 01, write locked Lock status for 0x0c0000 (size 0x010000) is 01, write locked Lock status for 0x0d0000 (size 0x010000) is 01, write locked Lock status for 0x0e0000 (size 0x010000) is 01, write locked Lock status for 0x0f0000 (size 0x010000) is 03, write locked down Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address 0xfff00000. Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x4e, id2 0x41 Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xdd, id2 0x7c Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for ST M50FLW040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for ST M50FLW040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for ST M50FLW080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for ST M50FLW080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x80, id2 0xfe Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xdd, id2 0xb2 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for TI TMS29F002RB, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for TI TMS29F002RT, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No operations were specified. -[0000:00]-+-00.0 Intel Corporation 82855PM Processor to I/O Controller [8086:3340] +-01.0-[01]----00.0 ATI Technologies Inc Radeon Mobility M6 LY [1002:4c59] +-1d.0 Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 [8086:24c2] +-1d.1 Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 [8086:24c4] +-1d.2 Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 [8086:24c7] +-1d.7 Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller [8086:24cd] +-1e.0-[02-08]--+-00.0 Ricoh Co Ltd RL5c476 II [1180:0476] | +-00.1 Ricoh Co Ltd RL5c476 II [1180:0476] | +-00.2 Ricoh Co Ltd R5C552 IEEE 1394 Controller [1180:0552] | +-01.0 Intel Corporation 82540EP Gigabit Ethernet Controller (Mobile) [8086:101e] | \-02.0 Intel Corporation PRO/Wireless 2200BG [Calexico2] Network Connection [8086:4220] +-1f.0 Intel Corporation 82801DBM (ICH4-M) LPC Interface Bridge [8086:24cc] +-1f.1 Intel Corporation 82801DBM (ICH4-M) IDE Controller [8086:24ca] +-1f.3 Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller [8086:24c3] +-1f.5 Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller [8086:24c5] \-1f.6 Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller [8086:24c6] superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x1700, id=0x11ea Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0000, id=0x0000 Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xea11, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xea11, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xea11, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xea11, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x0000, rev=0x0 Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Found NSC PC8739x (sid=0xea, srid=0x03) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val ea 11 00 00 17 a0 00 03 00 1e b7 00 00 00 00 00 def ea 11 MM MM MM 80 00 NA 00 MM 37 RR RR RR RR RR LDN 0x00 (Floppy) idx 30 60 61 70 71 74 75 f0 f1 val 01 03 f0 06 03 02 04 44 02 def 00 03 f2 06 03 02 04 24 00 LDN 0x01 (Parallel port) idx 30 60 61 70 71 74 75 f0 val 01 03 bc 07 03 04 04 22 def 00 02 78 07 02 04 04 f2 LDN 0x02 (COM2 / FIR) idx 30 60 61 70 71 74 75 f0 val 00 02 f8 03 03 04 04 82 def 00 02 f8 03 03 04 04 02 LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 82 def 00 03 f8 04 03 04 04 02 LDN 0x07 (GPIO) idx 30 60 61 70 71 74 75 f0 f1 f2 val 01 16 20 00 03 04 04 23 03 00 def 00 00 00 00 03 04 04 00 44 01 LDN 0x0a (Watchdog timer (WDT)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 02 def 00 00 00 00 03 04 04 02 LDN 0x0b (Game port) idx 30 60 61 70 71 74 75 f0 val 00 02 01 00 03 04 04 00 def 00 02 01 00 03 04 04 00 LDN 0x0c (MIDI port) idx 30 60 61 70 71 74 75 f0 val 00 03 30 00 03 04 04 00 def 00 03 30 00 03 04 04 00 LDN 0x0f (X-Bus) idx 30 60 61 70 71 74 75 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 val 00 00 00 00 00 04 04 00 00 00 00 50 00 00 00 00 00 def 00 00 00 00 00 04 04 00 00 00 00 00 00 00 00 00 00 Probing for NSC Super I/O at 0x4e... Failed. Returned data: sid=0x00, srid=0x00 Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xea, rev=0x11 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xaa, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xea/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xea/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xea/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xea/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0x00/0x06, rev=0x00 Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0x00/0x06, rev=0x00 Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0x00/0x06, rev=0x00 Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0x00/0x06, rev=0x00 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff

1 0

[v2] r4871 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/lib src/boot src/devices src/include src/include/cpu/x86 src/include/device src/lib src/pc80 src/southbridge/intel/i82371eb util/x86emu
by svn＠coreboot.org 27 Oct '09

27 Oct '09

Author: myles Date: 2009-10-27 15:29:29 +0100 (Tue, 27 Oct 2009) New Revision: 4871 Modified: trunk/coreboot-v2/src/arch/i386/boot/gdt.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/include/div64.h trunk/coreboot-v2/src/arch/i386/lib/exception.c trunk/coreboot-v2/src/arch/i386/lib/printk_init.c trunk/coreboot-v2/src/boot/hardwaremain.c trunk/coreboot-v2/src/devices/device_util.c trunk/coreboot-v2/src/include/cbmem.h trunk/coreboot-v2/src/include/cpu/x86/mtrr.h trunk/coreboot-v2/src/include/cpu/x86/tsc.h trunk/coreboot-v2/src/include/device/device.h trunk/coreboot-v2/src/lib/cbmem.c trunk/coreboot-v2/src/lib/clog2.c trunk/coreboot-v2/src/lib/lzma.c trunk/coreboot-v2/src/pc80/mc146818rtc.c trunk/coreboot-v2/src/pc80/udelay_io.c trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb.h trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c trunk/coreboot-v2/util/x86emu/x86.c trunk/coreboot-v2/util/x86emu/x86_interrupts.c Log: Add few missing prototypes, and remove few unused (thus lonelly) variables. TODO - x86emu need (imo) some common header with prototypes at least - clog2, ulzma, hardwaremain prototypes added by this patch probably should be moved to some header too. - in src/devices/device_util.c prototype is before function because seems, it is used only within same file, if not it should be moved to debug section of prototypes in include/device/device.h Signed-off-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/gdt.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/gdt.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/arch/i386/boot/gdt.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -33,6 +33,7 @@ } __attribute__((packed)); // Copy GDT to new location and reload it +void move_gdt(void); void move_gdt(void) { void *newgdt; Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -34,8 +34,6 @@ uint64_t high_tables_base = 0; uint64_t high_tables_size; -void cbmem_list(void); - void move_gdt(void); void cbmem_arch_init(void) { Modified: trunk/coreboot-v2/src/arch/i386/include/div64.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/div64.h 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/arch/i386/include/div64.h 2009-10-27 14:29:29 UTC (rev 4871) @@ -36,6 +36,9 @@ #define div_long_long_rem(a,b,c) div_ll_X_l_rem(a,b,c) extern inline long +div_ll_X_l_rem(long long divs, long div, long *rem); + +extern inline long div_ll_X_l_rem(long long divs, long div, long *rem) { long dum2; Modified: trunk/coreboot-v2/src/arch/i386/lib/exception.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/exception.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/arch/i386/lib/exception.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -361,6 +361,8 @@ #include <arch/registers.h> +void x86_exception(struct eregs *info); + void x86_exception(struct eregs *info) { #if CONFIG_GDB_STUB == 1 Modified: trunk/coreboot-v2/src/arch/i386/lib/printk_init.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/printk_init.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/arch/i386/lib/printk_init.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -32,6 +32,9 @@ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL #endif +void console_tx_byte(unsigned char byte); +int do_printk(int msg_level, const char *fmt, ...); + void console_tx_byte(unsigned char byte) { if (byte == '\n') Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -52,6 +52,8 @@ * In the dev_enumerate() phase, */ +void hardwaremain(int boot_complete); + void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; Modified: trunk/coreboot-v2/src/devices/device_util.c =================================================================== --- trunk/coreboot-v2/src/devices/device_util.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/devices/device_util.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -556,7 +556,7 @@ } } -void resource_tree(struct device *root, int debug_level, int depth) +static void resource_tree(struct device *root, int debug_level, int depth) { int i = 0, link = 0; struct device *child; Modified: trunk/coreboot-v2/src/include/cbmem.h =================================================================== --- trunk/coreboot-v2/src/include/cbmem.h 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/include/cbmem.h 2009-10-27 14:29:29 UTC (rev 4871) @@ -45,5 +45,7 @@ int cbmem_reinit(u64 baseaddr); void *cbmem_add(u32 id, u64 size); void *cbmem_find(u32 id); +void cbmem_list(void); +void cbmem_arch_init(void); #endif Modified: trunk/coreboot-v2/src/include/cpu/x86/mtrr.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/x86/mtrr.h 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/include/cpu/x86/mtrr.h 2009-10-27 14:29:29 UTC (rev 4871) @@ -34,10 +34,14 @@ #if !defined(__ROMCC__) && !defined (ASSEMBLY) +#include <device/device.h> +void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); +void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); +void x86_setup_fixed_mtrrs(void); #endif /* __ROMCC__ */ Modified: trunk/coreboot-v2/src/include/cpu/x86/tsc.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/x86/tsc.h 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/include/cpu/x86/tsc.h 2009-10-27 14:29:29 UTC (rev 4871) @@ -24,6 +24,8 @@ asm volatile ("rdtsc" : "=A" (val)); return val; } + +void init_timer(void); #endif Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/include/device/device.h 2009-10-27 14:29:29 UTC (rev 4871) @@ -132,6 +132,7 @@ void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum); void show_devs_subtree(struct device *root, int debug_level, const char *msg); void show_all_devs(int debug_level, const char *msg); +void show_all_devs_tree(int debug_level, const char *msg); void show_one_resource(int debug_level, struct device *dev, struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char* msg); @@ -152,4 +153,5 @@ void root_dev_enable_resources(device_t dev); unsigned int root_dev_scan_bus(device_t root, unsigned int max); void root_dev_init(device_t dev); +void root_dev_reset(struct bus *bus); #endif /* DEVICE_H */ Modified: trunk/coreboot-v2/src/lib/cbmem.c =================================================================== --- trunk/coreboot-v2/src/lib/cbmem.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/lib/cbmem.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -90,7 +90,7 @@ struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - debug("Re-Initializing CBMEM area to 0x%lx\n", baseaddr); + debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); #ifndef __ROMCC__ bss_cbmem_toc = cbmem_toc; #endif @@ -212,7 +212,7 @@ #endif if (cbmem_toc == NULL) - return NULL; + return; for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { Modified: trunk/coreboot-v2/src/lib/clog2.c =================================================================== --- trunk/coreboot-v2/src/lib/clog2.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/lib/clog2.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -7,6 +7,8 @@ /* Assume 8 bits per byte */ #define CHAR_BIT 8 +unsigned long log2(unsigned long x); + unsigned long log2(unsigned long x) { // assume 8 bits per byte. Modified: trunk/coreboot-v2/src/lib/lzma.c =================================================================== --- trunk/coreboot-v2/src/lib/lzma.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/lib/lzma.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -14,6 +14,7 @@ #include <console/console.h> #include <string.h> +unsigned long ulzma(unsigned char * src, unsigned char * dst); unsigned long ulzma(unsigned char * src, unsigned char * dst) { Modified: trunk/coreboot-v2/src/pc80/mc146818rtc.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -133,8 +133,10 @@ void rtc_init(int invalid) { +#if CONFIG_HAVE_OPTION_TABLE unsigned char x; int cmos_invalid, checksum_invalid; +#endif printk_debug("RTC Init\n"); Modified: trunk/coreboot-v2/src/pc80/udelay_io.c =================================================================== --- trunk/coreboot-v2/src/pc80/udelay_io.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/pc80/udelay_io.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -1,4 +1,5 @@ #include <arch/io.h> +#include <delay.h> void udelay(unsigned usecs) { Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb.h 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb.h 2009-10-27 14:29:29 UTC (rev 4871) @@ -24,6 +24,7 @@ #ifndef __ROMCC__ #include "chip.h" void i82371eb_enable(device_t dev); +void i82371eb_hard_reset(void); #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -29,7 +29,6 @@ static void isa_init(struct device *dev) { - u16 reg16; u32 reg32; /* Initialize the real time clock (RTC). */ Modified: trunk/coreboot-v2/util/x86emu/x86.c =================================================================== --- trunk/coreboot-v2/util/x86emu/x86.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/util/x86emu/x86.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -36,6 +36,7 @@ }; void x86_exception(struct eregs *info); +void run_bios(struct device *dev, unsigned long addr); extern unsigned char __idt_handler, __idt_handler_size; extern unsigned char __realmode_code, __realmode_code_size; @@ -124,8 +125,6 @@ void run_bios(struct device *dev, unsigned long addr) { - int i; - /* clear vga bios data area */ memset(0x400, 0, 0x200); Modified: trunk/coreboot-v2/util/x86emu/x86_interrupts.c =================================================================== --- trunk/coreboot-v2/util/x86emu/x86_interrupts.c 2009-10-27 14:05:21 UTC (rev 4870) +++ trunk/coreboot-v2/util/x86emu/x86_interrupts.c 2009-10-27 14:29:29 UTC (rev 4871) @@ -51,6 +51,10 @@ PCIBIOS_BADREG = 0x8700 }; +int int12_handler(struct eregs *regs); +int int1a_handler(struct eregs *regs); +int int15_handler(struct eregs *regs); + int int12_handler(struct eregs *regs) { regs->eax = 64 * 1024;

1 0

[v2] r4870 - trunk/coreboot-v2/src/mainboard/arima/hdama
by svn＠coreboot.org 27 Oct '09

27 Oct '09

Author: myles Date: 2009-10-27 15:05:21 +0100 (Tue, 27 Oct 2009) New Revision: 4870 Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c Log: Update arima/hdama to detect how many nodes there are. Compare to tyan/s2892. Fixes booting for Hugh. Various white space fixes as well. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-10-26 23:52:34 UTC (rev 4869) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-10-27 14:05:21 UTC (rev 4870) @@ -1,6 +1,6 @@ #define ASSEMBLY 1 #define __ROMCC__ - + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -95,7 +95,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" - #if CONFIG_USE_FALLBACK_IMAGE == 1 #include "southbridge/amd/amd8111/amd8111_enable_rom.c" @@ -103,40 +102,40 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { - unsigned last_boot_normal_x = last_boot_normal(); + unsigned last_boot_normal_x = last_boot_normal(); - /* Is this a cpu only reset? or Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal_x) { - goto normal_image; - } else { - goto fallback_image; - } - } + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ - enumerate_ht_chain(); + enumerate_ht_chain(); - amd8111_enable_rom(); + amd8111_enable_rom(); - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal_x) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } normal_image: - __asm__ volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ - ); + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ + ); fallback_image: ; @@ -149,71 +148,70 @@ { #if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); + failover_process(bist, cpu_init_detectedx); #endif - real_main(bist, cpu_init_detectedx); - + real_main(bist, cpu_init_detectedx); } void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, #endif }; - int needs_reset; + int needs_reset; + unsigned bsp_apicid = 0; + struct mem_controller ctrl[8]; + unsigned nodes; - if (bist == 0) { - init_cpus(cpu_init_detectedx); - } + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx); + } pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); + uart_init(); + console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - setup_default_resource_map(); + setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + /* This is needed to be able to call udelay(). It could be moved to + * memreset_setup, since udelay is called in memreset. */ + init_timer(); + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x(); + if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); + print_info("ht reset -\r\n"); + soft_reset(); } + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + + fill_mem_ctrl(nodes, ctrl, spd_addr); + enable_smbus(); memreset_setup(); - sdram_initialize(ARRAY_SIZE(cpu), cpu); - post_cache_as_ram(); + sdram_initialize(nodes, ctrl); + post_cache_as_ram(); }

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[PATCH] Add kconfig menus for most chipset VIDEO_MB values
by Uwe Hermann 27 Oct '09

27 Oct '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 8

P6T
by Master Mkl 26 Oct '09

26 Oct '09

Hello folks! You are doing a great job! I buy a ASUS P6T (socket1366) with a broken VT-d. (VT-x Okay: vmx on) core i7 920. http://www.nabble.com/Re:-Re:-VT-D-RMRR-is-incorrect-p22022061.html I'd like to know if your project is still quite active, if you plan to support this motherboard, and if you are able to support VT-d. If yes, when? Also if yes, and required, I could first give you a root access to a shell on this computer. Then could I simply cross over EHCI USB Debug port to another computer USB port for debug purpose? Thanks in advance for your answer, Best Regards, mkl. _________________________________________________________________ Nouveau! Découvrez le Windows phone Samsung Omnia II disponible chez SFR. http://clk.atdmt.com/FRM/go/175819072/direct/01/

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coreboot October 2009