coreboot October 2009

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[v2] r4859 - in trunk/coreboot-v2/src/cpu/intel: model_6ex model_6fx
by svn＠coreboot.org 26 Oct '09

26 Oct '09

Author: stepan Date: 2009-10-26 17:49:16 +0100 (Mon, 26 Oct 2009) New Revision: 4859 Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc Log: intel core and core 2: - small preprocessor fix - leave some space in the CAR area for the usbdebug structure if usbdebug is used Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc 2009-10-26 16:48:27 UTC (rev 4858) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram.inc 2009-10-26 16:49:16 UTC (rev 4859) @@ -94,7 +94,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif /* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax @@ -117,10 +116,16 @@ /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax - movl %eax, %cr0 + movl %eax, %cr0 +#endif /* Set up stack pointer */ +#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) + /* leave some space for the struct ehci_debug_info */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif movl %eax, %esp /* Restore the BIST result */ Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc 2009-10-26 16:48:27 UTC (rev 4858) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram.inc 2009-10-26 16:49:16 UTC (rev 4859) @@ -101,7 +101,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif /* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax @@ -124,10 +123,16 @@ /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax - movl %eax, %cr0 + movl %eax, %cr0 +#endif /* Set up stack pointer */ +#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) + /* leave some space for the struct ehci_debug_info */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif movl %eax, %esp /* Restore the BIST result */

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[v2] r4858 - trunk/coreboot-v2/src/mainboard/intel/eagleheights
by svn＠coreboot.org 26 Oct '09

26 Oct '09

Author: stepan Date: 2009-10-26 17:48:27 +0100 (Mon, 26 Oct 2009) New Revision: 4858 Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c Log: Use Intel Core code for eagleheights CAR init, not Intel Core 2, as any of the CPUs might be used. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb 2009-10-26 16:47:05 UTC (rev 4857) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Config.lb 2009-10-26 16:48:27 UTC (rev 4858) @@ -109,7 +109,8 @@ ## ## Setup Cache-As-Ram ## -mainboardinit cpu/intel/model_6fx/cache_as_ram.inc +## Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +mainboardinit cpu/intel/model_6ex/cache_as_ram.inc ### ### This is the early phase of coreboot startup Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc 2009-10-26 16:47:05 UTC (rev 4857) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc 2009-10-26 16:48:27 UTC (rev 4858) @@ -14,6 +14,7 @@ crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc crt0-y += ../../../../src/arch/i386/lib/id.inc +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc crt0-y += auto.inc Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c 2009-10-26 16:47:05 UTC (rev 4857) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/auto.c 2009-10-26 16:48:27 UTC (rev 4858) @@ -238,4 +238,5 @@ sdram_initialize(ARRAY_SIZE(mch), mch); } -#include "cpu/intel/model_6fx/cache_as_ram_disable.c" +/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */ +#include "cpu/intel/model_6ex/cache_as_ram_disable.c"

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[v2] r4857 - trunk/coreboot-v2/src/devices
by svn＠coreboot.org 26 Oct '09

26 Oct '09

Author: stepan Date: 2009-10-26 17:47:05 +0100 (Mon, 26 Oct 2009) New Revision: 4857 Modified: trunk/coreboot-v2/src/devices/device.c Log: Now that the resource allocator is working nicely we can turn down the debug level output and make some output SPEW only. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-10-26 15:14:07 UTC (rev 4856) +++ trunk/coreboot-v2/src/devices/device.c 2009-10-26 16:47:05 UTC (rev 4857) @@ -890,11 +890,10 @@ printk_info("Enumerating buses...\n"); root = &dev_root; - show_all_devs(BIOS_DEBUG, "Before Device Enumeration."); - printk_debug("Compare with tree...\n"); + show_all_devs(BIOS_SPEW, "Before Device Enumeration."); + printk_spew("Compare with tree...\n"); + show_devs_tree(root, BIOS_SPEW, 0, 0); - show_devs_tree(root, BIOS_DEBUG, 0, 0); - if (root->chip_ops && root->chip_ops->enable_dev) { root->chip_ops->enable_dev(root); } @@ -945,7 +944,7 @@ read_resources(&root->link[0]); printk_info("Done reading resources.\n"); - print_resource_tree(root, BIOS_DEBUG, "After reading."); + print_resource_tree(root, BIOS_SPEW, "After reading."); /* Compute resources for all domains. */ for (child = root->link[0].children; child; child = child->sibling) { @@ -1021,7 +1020,7 @@ } assign_resources(&root->link[0]); printk_info("Done setting resources.\n"); - print_resource_tree(root, BIOS_DEBUG, "After assigning values."); + print_resource_tree(root, BIOS_SPEW, "After assigning values."); printk_info("Done allocating resources.\n"); } @@ -1068,5 +1067,5 @@ } } printk_info("Devices initialized\n"); - show_all_devs(BIOS_DEBUG, "After init."); + show_all_devs(BIOS_SPEW, "After init."); }

1 0

[PATCH] More Kconfig changes
by Myles Watson 26 Oct '09

26 Oct '09

Define some variables that were not defined. There are a couple left. Do kbuildall then grep not.defined kbuildall.results/* The interesting ones were GENERATE_* I had to put them in twice to make it work correctly. Once outside the menu setting the defaults, and once inside the menu. Now they show up when they should, and are always defined Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0 in newconfig. Define MEM_TRAIN_SEQ to be an integer and set it correctly. Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10 MOVNTI is a performance enhancement, and should default to 0 so it doesn't break boards that forget to define it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

5 13

[v2] r4856 - in trunk/coreboot-v2/src: . config console cpu/amd/car cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/socket_AM2r2 cpu/amd/socket_F_1207 mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8n_e mainboard/digitallogic/adl855pc mainboard/digitallogic/msm586seg mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli mainboard/msi/ms7135 mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicro/h8d
by svn＠coreboot.org 26 Oct '09

26 Oct '09

Author: myles Date: 2009-10-26 16:14:07 +0100 (Mon, 26 Oct 2009) New Revision: 4856 Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig Log: Define some variables that were not defined. There are a couple left. Do kbuildall then grep not.defined kbuildall.results/* The interesting ones were GENERATE_* I had to put them in twice to make it work correctly: once outside the menu setting the defaults, and once inside the menu. Now they show up when they should, and are always defined Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0 in newconfig. Define MEM_TRAIN_SEQ to be an integer and set it correctly. Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10 MOVNTI is a performance enhancement, and should default to 0 so it doesn't break boards that forget to define it. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -74,10 +74,6 @@ int default 36 -config AGP_APERTURE_SIZE - hex - default 0x0 - config XIP_ROM_BASE hex default 0xfffe0000 @@ -181,7 +177,7 @@ config HAVE_INIT_TIMER bool - default n + default y config HAVE_MAINBOARD_RESOURCES bool @@ -189,7 +185,7 @@ config HAVE_MOVNTI bool - default y + default n config HAVE_OPTION_TABLE bool @@ -216,6 +212,7 @@ default n config VIDEO_MB + default 0 int config USE_WATCHDOG_ON_BOOT @@ -230,6 +227,7 @@ config GFXUMA bool + default n help Enable Unified Memory Architecture for graphics. @@ -238,6 +236,27 @@ # # endmenu +#TODO Remove this option or make it useful. +config HAVE_LOW_TABLES + bool + default y + help + This Option is unused in the code. Since two boards try to set it to + 'n', they may be broken. We either need to make the option useful or + get rid of it. The broken boards are: + asus/m2v-mx_se + supermicro/h8dme + +config HAVE_HIGH_TABLES + bool + default n + help + This variable specifies whether a given northbridge has high table + support. + It is set in northbridge/*/Kconfig. + Whether or not the high tables are actually written by coreboot is + configurable by the user via WRITE_HIGH_TABLES. + config HAVE_ACPI_TABLES bool help @@ -262,16 +281,28 @@ Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. -config HAVE_HIGH_TABLES +#These Options are here to avoid "undefined" warnings. +#The actual selection and help texts are in the following menu. + +config GENERATE_ACPI_TABLES bool + default HAVE_ACPI_TABLES -menu "System tables" +config GENERATE_MP_TABLE + bool + default HAVE_MP_TABLE -config HAVE_LOW_TABLES +config GENERATE_PIRQ_TABLE bool - default y + default HAVE_PIRQ_TABLE config WRITE_HIGH_TABLES + bool + default HAVE_HIGH_TABLES + +menu "System tables" + +config WRITE_HIGH_TABLES bool "Write 'high' tables to avoid being overwritten in F segment" depends on HAVE_HIGH_TABLES default y @@ -409,3 +440,16 @@ config LIFT_BSP_APIC_ID bool default n + +# These probably belong somewhere else, but they are needed somewhere. +config AP_CODE_IN_CAR + bool + default n + +config USE_INIT + bool + default n + +config ENABLE_APIC_EXT_ID + bool + default n Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -299,11 +299,6 @@ export always comment "Use data cache as temporary RAM if possible" end -define CONFIG_CAR_FAM10 - default 0 - export always - comment "AMD family 10 CAR requires additional setup" -end define CONFIG_DCACHE_RAM_BASE default 0xc0000 format "0x%x" Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/console/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -275,3 +275,14 @@ endmenu +config CONSOLE_BTEXT + bool + default n + +config CONSOLE_SROM + bool + default n + +config CONSOLE_LOGBUF + bool + default n Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-10-26 15:14:07 UTC (rev 4856) @@ -24,7 +24,7 @@ /* leave some space for global variable to pass to RAM stage */ #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -/* for CONFIG_CAR_FAM10 */ +/* for CAR with FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ #define MSR_FAM10 0xC001102A Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -103,9 +103,6 @@ // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif set_sysinfo_in_ram(1); // So other core0 could start to train mem #if CONFIG_MEM_TRAIN_SEQ == 1 Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_10XXX bool - select HAVE_INIT_TIMER select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -306,11 +306,6 @@ stop_this_cpu(); } - -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif - #if RAMINIT_SYSINFO == 1 static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo) #else @@ -478,8 +473,8 @@ /* Enable routing table */ printk_debug("Start node %02x", node); -#if CONFIG_CAR_FAM10 == 1 - /* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 + /* For FAM10 support, we need to set Dram base/limit for the new node */ pci_write_config32(NODE_MP(node), 0x44, 0); pci_write_config32(NODE_MP(node), 0x40, 3); #endif Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_FXX bool - select HAVE_INIT_TIMER select HAVE_MOVNTI select USE_PRINTK_IN_CAR select USE_DCACHE_RAM Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -215,11 +215,6 @@ stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... } -#ifndef CONFIG_MEM_TRAIN_SEQ -#define CONFIG_MEM_TRAIN_SEQ 0 -#endif - - #if CONFIG_MEM_TRAIN_SEQ == 1 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); #endif Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Config.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -27,7 +27,6 @@ uses CONFIG_CBB uses CONFIG_CDB uses CONFIG_PCI_BUS_SEGN_BITS -uses CONFIG_CAR_FAM10 config chip.h @@ -39,8 +38,6 @@ default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_CPU_SOCKET_TYPE=0x11 -default CONFIG_CAR_FAM10=1 - if CONFIG_EXT_RT_TBL_SUPPORT default CONFIG_CBB=0xff default CONFIG_CDB=0 Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -2,7 +2,6 @@ bool select CPU_AMD_MODEL_10XXX select HT3_SUPPORT - select CAR_FAM10 config CPU_SOCKET_TYPE hex Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Config.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -27,7 +27,6 @@ uses CONFIG_CBB uses CONFIG_CDB uses CONFIG_PCI_BUS_SEGN_BITS -uses CONFIG_CAR_FAM10 config chip.h @@ -39,8 +38,6 @@ default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG default CONFIG_CPU_SOCKET_TYPE=0x10 -default CONFIG_CAR_FAM10=1 - if CONFIG_EXT_RT_TBL_SUPPORT default CONFIG_CBB=0xff default CONFIG_CDB=0 Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -2,7 +2,6 @@ bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT - select CAR_FAM10 config CPU_SOCKET_TYPE hex Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -14,7 +14,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select AP_CODE_IN_CAR select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT @@ -81,6 +80,11 @@ default n depends on BOARD_AMD_SERENGETI_CHEETAH +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_AMD_SERENGETI_CHEETAH + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -67,6 +67,11 @@ default n depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 +config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -111,7 +111,6 @@ uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE ### Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -49,7 +49,7 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -87,7 +87,7 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -34,6 +34,11 @@ default 0x10 depends on BOARD_ASUS_A8N_E +config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_ASUS_A8N_E + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -24,3 +24,8 @@ int default 5 depends on BOARD_DIGITALLOGIC_ADL855PC + +config HAVE_INIT_TIMER + bool + default n + depends on BOARD_DIGITALLOGIC_ADL855PC Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -20,3 +20,7 @@ default 2 depends on BOARD_DIGITALLOGIC_MSM586SEG +config HAVE_INIT_TIMER + bool + default n + depends on BOARD_DIGITALLOGIC_MSM586SEG Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -12,7 +12,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -42,6 +41,11 @@ default 16 depends on BOARD_GIGABYTE_GA_2761GXDK +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_GIGABYTE_GA_2761GXDK + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -14,7 +14,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT @@ -45,6 +44,11 @@ default 16 depends on BOARD_GIGABYTE_M57SLI +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_GIGABYTE_M57SLI + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -22,6 +22,11 @@ default 0x10 depends on BOARD_MSI_MS7135 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_MSI_MS7135 + config SB_HT_CHAIN_ON_BUS0 int default 2 @@ -52,11 +57,6 @@ default 0x100000 depends on BOARD_MSI_MS7135 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_MSI_MS7135 - config MAX_CPUS int default 2 @@ -67,11 +67,6 @@ default 1 depends on BOARD_MSI_MS7135 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_MSI_MS7135 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ default 16 depends on BOARD_MSI_MS7260 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_MSI_MS7260 + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -12,7 +12,6 @@ select USE_DCACHE_RAM select HAVE_HARD_RESET select IOAPIC - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ default 16 depends on BOARD_NVIDIA_L1_2PVV +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_NVIDIA_L1_2PVV + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -41,6 +41,11 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DME +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DME + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -40,6 +40,11 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DMR +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DMR + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -41,6 +41,11 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DMR_FAM10 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -114,7 +114,6 @@ uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE ### Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c 2009-10-26 15:14:07 UTC (rev 4856) @@ -49,7 +49,7 @@ * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, @@ -88,7 +88,7 @@ * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ - // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR_FAM10 + // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select USE_DCACHE_RAM select HAVE_HARD_RESET select IOAPIC - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -43,9 +43,3 @@ bool default n depends on BOARD_TYAN_S1846 - -#Override manually, as in Config.lb (FIXME) -config IRQ_SLOT_COUNT - int - default 0 - depends on BOARD_TYAN_S1846 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2880 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2880 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2880 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2880 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2881 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2881 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2881 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2881 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2882 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2882 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2882 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2882 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -51,11 +51,6 @@ default 0x100000 depends on BOARD_TYAN_S2885 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2885 - config MAX_CPUS int default 4 @@ -66,11 +61,6 @@ default 2 depends on BOARD_TYAN_S2885 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2885 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -53,11 +53,6 @@ default 0x100000 depends on BOARD_TYAN_S2891 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2891 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ default 2 depends on BOARD_TYAN_S2891 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2891 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -53,11 +53,6 @@ default 0x100000 depends on BOARD_TYAN_S2892 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2892 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ default 2 depends on BOARD_TYAN_S2892 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2892 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -53,11 +53,6 @@ default 0x100000 depends on BOARD_TYAN_S2895 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2895 - config MAX_CPUS int default 4 @@ -68,11 +63,6 @@ default 2 depends on BOARD_TYAN_S2895 -config MEM_TRAIN_SEQ - bool - default n - depends on BOARD_TYAN_S2895 - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select K8_REV_F_SUPPORT select BOARD_ROMSIZE_KB_512 @@ -43,6 +42,11 @@ default 16 depends on BOARD_TYAN_S2912 +config MEM_TRAIN_SEQ + int + default 1 + depends on BOARD_TYAN_S2912 + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -13,7 +13,6 @@ select HAVE_HARD_RESET select IOAPIC select LIFT_BSP_APIC_ID - select MEM_TRAIN_SEQ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID @@ -44,6 +43,11 @@ default 16 depends on BOARD_TYAN_S2912_FAM10 +config MEM_TRAIN_SEQ + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + config SB_HT_CHAIN_ON_BUS0 int default 2 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-26 15:14:07 UTC (rev 4856) @@ -114,7 +114,6 @@ uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_CAR_FAM10 uses CONFIG_AMD_UCODE_PATCH_FILE ### Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -21,11 +21,35 @@ bool select HAVE_HIGH_TABLES select HYPERTRANSPORT_PLUGIN_SUPPORT - select HT3_SUPPORT config AGP_APERTURE_SIZE hex default 0x4000000 depends on NORTHBRIDGE_AMD_AMDFAM10 +config HT3_SUPPORT + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config AMDMCT + bool + default y + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config MEM_TRAIN_SEQ + int + default 0 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on NORTHBRIDGE_AMD_AMDFAM10 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + source src/northbridge/amd/amdfam10/root_complex/Kconfig Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-10-26 00:12:02 UTC (rev 4855) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-10-26 15:14:07 UTC (rev 4856) @@ -32,4 +32,19 @@ default n depends on NORTHBRIDGE_AMD_AMDK8 +config MEM_TRAIN_SEQ + int + default 0 + depends on NORTHBRIDGE_AMD_AMDK8 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on NORTHBRIDGE_AMD_AMDK8 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on NORTHBRIDGE_AMD_AMDK8 + source src/northbridge/amd/amdk8/root_complex/Kconfig

1 0

CBFS looking smbus for option rom?
by Joseph Smith 26 Oct '09

26 Oct '09

Why would CBFS look for a option rom for the ICH4 SMBUS device? From boot log: PCI: 00:1f.3 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8049 + align -> fff880c0 Check pci8086,3577.rom CBFS: follow chain: fff880c0 + 38 + 10000 + align -> fff98100 Check CBFS: follow chain: fff98100 + 28 + 57eb8 + align -> ffff0000 CBFS: Could not find file pci8086,24c3.rom In cbfs, rom address for PCI: 00:1f.3 = 00000000 On mainboard, rom address for PCI: 00:1f.3 = 0 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 1

[PATCH] x86.c and x86emu/YABEL updates
by Stefan Reinauer 26 Oct '09

26 Oct '09

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Option ROM init x86/x86emu update - use default display in int 15 5f35 - move REALMODE_BASE to 0x600, 0x500 can be BDA - add regparm for assembler functions - use memset instead of own implementation - YABEL: copy back the IVT, BDA and VBIOS. Some Xorg drivers require this. - YABEL: use hardware timer instead of emulated timer, because the emulated timer's base is never initialized (leading to division by zero if the timer is really used) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: util/x86emu/x86_interrupts.c =================================================================== --- util/x86emu/x86_interrupts.c (revision 4842) +++ util/x86emu/x86_interrupts.c (working copy) @@ -206,6 +206,7 @@ regs->eax = 0x860f; break; /* And now Intel IGD code */ +#define BOOT_DISPLAY_DEFAULT 0 #define BOOT_DISPLAY_CRT (1 << 0) #define BOOT_DISPLAY_TV (1 << 1) #define BOOT_DISPLAY_EFP (1 << 2) @@ -217,7 +218,7 @@ case 0x5f35: regs->eax = 0x5f; - regs->ecx = BOOT_DISPLAY_LCD|BOOT_DISPLAY_CRT; + regs->ecx = BOOT_DISPLAY_DEFAULT; res = 0; break; case 0x5f40: Index: util/x86emu/x86.c =================================================================== --- util/x86emu/x86.c (revision 4842) +++ util/x86emu/x86.c (working copy) @@ -29,7 +29,7 @@ #include <console.h> #endif -#define REALMODE_BASE ((void *)0x500) +#define REALMODE_BASE ((void *)0x600) struct realmode_idt { u16 offset, cs; @@ -41,8 +41,8 @@ extern unsigned char __realmode_code, __realmode_code_size; extern unsigned char __run_optionrom, __run_interrupt; -void (*run_optionrom)(u32 devfn) = (void *)&__run_optionrom; -void (*vga_enable_console)(void) = (void *)&__run_interrupt; +void (*run_optionrom)(u32 devfn) __attribute__((regparm(0))) = (void *)&__run_optionrom; +void (*vga_enable_console)(void) __attribute__((regparm(0))) = (void *)&__run_interrupt; int (*intXX_handler[256])(struct eregs *regs) = { NULL }; @@ -127,9 +127,7 @@ int i; /* clear vga bios data area */ - for (i = 0x400; i < 0x500; i++) { - *(unsigned char *) i = 0; - } + memset(0x400, 0, 0x200); /* Set up C interrupt handlers */ setup_interrupt_handlers(); Index: util/x86emu/x86_asm.S =================================================================== --- util/x86emu/x86_asm.S (revision 4842) +++ util/x86emu/x86_asm.S (working copy) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. */ -#define REALMODE_BASE 0x500 +#define REALMODE_BASE 0x600 #define RELOCATED(x) (x - __realmode_code + REALMODE_BASE) /* CR0 bits */ Index: util/x86emu/yabel/compat/functions.c =================================================================== --- util/x86emu/yabel/compat/functions.c (revision 4842) +++ util/x86emu/yabel/compat/functions.c (working copy) @@ -17,6 +17,7 @@ #ifndef CONFIG_COREBOOT_V2 #include <config.h> #endif +#include <string.h> #include <device/device.h> #define VMEM_SIZE 1024 *1024 /* 1 MB */ @@ -33,6 +34,9 @@ void run_bios(struct device * dev, unsigned long addr) { biosemu(vmem, VMEM_SIZE, dev, addr); + memcpy(0x0, vmem + 0x0, 0x400); + memcpy(0x400, vmem + 0x400, 0x100); + memcpy(0xc0000, vmem + 0xc0000, 0x10000); } u64 get_time(void) Index: util/x86emu/yabel/io.c =================================================================== --- util/x86emu/yabel/io.c (revision 4842) +++ util/x86emu/yabel/io.c (working copy) @@ -36,6 +36,9 @@ //defined in net-snk/kernel/timer.c extern u64 get_time(void); +#ifdef COREBOOT_V2 +#include <arch/io.h> +#else // these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs // with the functions and struct below void @@ -82,7 +85,7 @@ HALT_SYS(); return 0; } - +#endif u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size); void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size); u8 handle_port_61h(void); @@ -106,7 +109,8 @@ switch (addr) { case 0x61: //8254 KB Controller / Timer Port - rval = handle_port_61h(); + // rval = handle_port_61h(); + rval = inb(0x61); //DEBUG_PRINTF_IO("%s(%04x) KB / Timer Port B --> %02x\n", __func__, addr, rval); return rval; break;

3 5

[v2] r4855 - in branches/coreboot-v2-newbuild/src/cpu/intel: model_6ex model_6fx
by svn＠coreboot.org 26 Oct '09

26 Oct '09

Author: stepan Date: 2009-10-26 01:12:02 +0100 (Mon, 26 Oct 2009) New Revision: 4855 Modified: branches/coreboot-v2-newbuild/src/cpu/intel/model_6ex/cache_as_ram.inc branches/coreboot-v2-newbuild/src/cpu/intel/model_6fx/cache_as_ram.inc Log: intel core and core 2: - small preprocessor fix - leave some space in the CAR area for the usbdebug structure if usbdebug is used Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: branches/coreboot-v2-newbuild/src/cpu/intel/model_6ex/cache_as_ram.inc =================================================================== --- branches/coreboot-v2-newbuild/src/cpu/intel/model_6ex/cache_as_ram.inc 2009-10-25 23:56:30 UTC (rev 4854) +++ branches/coreboot-v2-newbuild/src/cpu/intel/model_6ex/cache_as_ram.inc 2009-10-26 00:12:02 UTC (rev 4855) @@ -94,7 +94,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif /* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax @@ -117,10 +116,16 @@ /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax - movl %eax, %cr0 + movl %eax, %cr0 +#endif /* Set up stack pointer */ +#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) + /* leave some space for the struct ehci_debug_info */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif movl %eax, %esp /* Restore the BIST result */ Modified: branches/coreboot-v2-newbuild/src/cpu/intel/model_6fx/cache_as_ram.inc =================================================================== --- branches/coreboot-v2-newbuild/src/cpu/intel/model_6fx/cache_as_ram.inc 2009-10-25 23:56:30 UTC (rev 4854) +++ branches/coreboot-v2-newbuild/src/cpu/intel/model_6fx/cache_as_ram.inc 2009-10-26 00:12:02 UTC (rev 4855) @@ -101,7 +101,6 @@ //movl $0x23322332, %eax xorl %eax, %eax rep stosl -#endif /* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax @@ -124,10 +123,16 @@ /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax - movl %eax, %cr0 + movl %eax, %cr0 +#endif /* Set up stack pointer */ +#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1) + /* leave some space for the struct ehci_debug_info */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif movl %eax, %esp /* Restore the BIST result */

1 0

[PATCH] use intel core instead of core 2 on eagleheights
by Stefan Reinauer 26 Oct '09

26 Oct '09

4 4

[v2] r4854 - branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights
by svn＠coreboot.org 26 Oct '09

26 Oct '09

Author: stepan Date: 2009-10-26 00:56:30 +0100 (Mon, 26 Oct 2009) New Revision: 4854 Modified: branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/Config.lb branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/auto.c Log: Use Intel Core code for eagleheights CAR init, not Intel Core 2, as any of the CPUs might be used. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/Config.lb =================================================================== --- branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/Config.lb 2009-10-25 23:47:38 UTC (rev 4853) +++ branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/Config.lb 2009-10-25 23:56:30 UTC (rev 4854) @@ -109,7 +109,7 @@ ## ## Setup Cache-As-Ram ## -mainboardinit cpu/intel/model_6fx/cache_as_ram.inc +mainboardinit cpu/intel/model_6ex/cache_as_ram.inc ### ### This is the early phase of coreboot startup Modified: branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/auto.c =================================================================== --- branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/auto.c 2009-10-25 23:47:38 UTC (rev 4853) +++ branches/coreboot-v2-newbuild/src/mainboard/intel/eagleheights/auto.c 2009-10-25 23:56:30 UTC (rev 4854) @@ -238,4 +238,4 @@ sdram_initialize(ARRAY_SIZE(mch), mch); } -#include "cpu/intel/model_6fx/cache_as_ram_disable.c" +#include "cpu/intel/model_6ex/cache_as_ram_disable.c"

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coreboot October 2009