coreboot September 2008

coreboot@coreboot.org

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415 discussions

r221 - buildrom-devel/packages/filo
by svn＠coreboot.org 11 Sep '08

11 Sep '08

Author: jcrouse Date: 2008-09-11 19:10:52 +0200 (Thu, 11 Sep 2008) New Revision: 221 Modified: buildrom-devel/packages/filo/filo.mk Log: The filo repo has moved lately, fix it up and bump the revision to match. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/filo/filo.mk =================================================================== --- buildrom-devel/packages/filo/filo.mk 2008-08-19 22:48:06 UTC (rev 220) +++ buildrom-devel/packages/filo/filo.mk 2008-09-11 17:10:52 UTC (rev 221) @@ -1,5 +1,5 @@ -FILO_URL=svn://coreboot.org/filo/trunk/filo-0.5 -FILO_TAG=49 +FILO_URL=svn://coreboot.org/filo/branches/filo-0.5 +FILO_TAG=59 FILO_DIR=$(BUILD_DIR)/filo FILO_SRC_DIR=$(FILO_DIR)/svn

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v2: The elfboot process with 128MB RAM
by Mats Erik Andersson 11 Sep '08

11 Sep '08

Hello all, I could use some of your insight into the elfboot stage. Appended to this message are two printouts of the elfboot process for 128MB RAM (which comes to a halt), and for 64MB RAM (which succeeds). It is jmp_to_elf_entry() in src/arch/i386/boot/boot.c that is unable to complete the set task for 128MB RAM. I suspect that the problem lies in the value of 'bounce_buffer' that is determined in src/boot/elfboot.c, but I fail to identify why a large value is causing any problem at all. The informational "Candidate bounce_buffer" is my addition at the loop end in get_bounce_buffer(). Since FILO never starts with 128MB, I cannot verify that the linuxbios_table indeed gets the expected last entry "convert_memmap: 0x00000000100000 0x00000007f00000 1", which the debugging output for FILO for 64MB would suggest. A slightly provocative question: Is the elfboot process implicitly hardcoded to depend on no more than 64MB RAM? My setup makes sure that PAM#, RPS, and PGPOL are correct (to my understanding) for distribution of memory: 64MB, 64MB+64MB, 64MB+0MB+64MB, etc. I will be much obliged for any pointers. They will all help me to understand the code base better than presently. Best regards, Mats E Andersson ## ## 64MB + 64MB RAM ## Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000734 checksum ed60 elfboot: Attempting to load payload. rom_stream: 0xfffe0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 Candidate bounce_buffer: 0x0000054000. Candidate bounce_buffer: 0x0007fb4000. malloc Enter, size 32, free_mem_ptr 0002757c malloc 0x0002757c New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88 (cleaned up) New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88 lb: [0x0000000000004000, 0x000000000002a000) malloc Enter, size 32, free_mem_ptr 0002759c malloc 0x0002759c New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48 (cleaned up) New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48 lb: [0x0000000000004000, 0x000000000002a000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036000 filesz: 0x000000000000cb88 [ 0x0000000000100000, 000000000010cb88, 0x0000000000136000) <- 00000000000000c0 Clearing Segment: addr: 0x000000000010cb88 memsz: 0x0000000000029478 Loading Segment: addr: 0x0000000000136000 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x0000000000136000, 0000000000136048, 0x0000000000136048) <- 000000000000cc60 Loaded segments verified segments closed down stream Jumping to boot code at 0x100078 entry = 0x00100078 lb_start = 0x00004000 lb_size = 0x00026000 buffer = 0x07fb4000 adjust = 0x07fd6000 elf_boot_notes = 0x0001f640 adjusted_boot_notes = 0x07ff5640 ## The system is stuck here! ## ## Next case: ## ## 64MB ## Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000734 checksum ab60 elfboot: Attempting to load payload. rom_stream: 0xfffe0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 Candidate bounce_buffer: 0x0000054000. Candidate bounce_buffer: 0x0003fb4000. malloc Enter, size 32, free_mem_ptr 0002757c malloc 0x0002757c New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88 (cleaned up) New segment addr 0x100000 size 0x36000 offset 0xc0 filesize 0xcb88 lb: [0x0000000000004000, 0x000000000002a000) malloc Enter, size 32, free_mem_ptr 0002759c malloc 0x0002759c New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48 (cleaned up) New segment addr 0x136000 size 0x48 offset 0xcc60 filesize 0x48 lb: [0x0000000000004000, 0x000000000002a000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000036000 filesz: 0x000000000000cb88 [ 0x0000000000100000, 000000000010cb88, 0x0000000000136000) <- 00000000000000c0 Clearing Segment: addr: 0x000000000010cb88 memsz: 0x0000000000029478 Loading Segment: addr: 0x0000000000136000 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x0000000000136000, 0000000000136048, 0x0000000000136048) <- 000000000000cc60 Loaded segments verified segments closed down stream Jumping to boot code at 0x100078 entry = 0x00100078 lb_start = 0x00004000 lb_size = 0x00026000 buffer = 0x03fb4000 adjust = 0x03fd6000 elf_boot_notes = 0x0001f640 adjusted_boot_notes = 0x03ff5640 FILO version 0.5.6 (mats@asus) Thu Sep 4 22:51:36 CEST 2008 collect_linuxbios_info: Searching for LinuxBIOS tables... find_lb_table: Found candidate at: 00000530 find_lb_table: header checksum o.k. find_lb_table: table checksum o.k. find_lb_table: record count o.k. collect_linuxbios_info: Found LinuxBIOS table at: 00000530 convert_memmap: 0x00000000000000 0x00000000001000 16 convert_memmap: 0x00000000001000 0x0000000009f000 1 convert_memmap: 0x000000000c0000 0x00000000030000 1 convert_memmap: 0x000000000f0000 0x00000000010000 16 convert_memmap: 0x00000000100000 0x00000003f00000 1 Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 usr=flash IDE time out reset failed, but we may be on SATA Drive 0 does not exist boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200 usr=flash

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r3572 build service
by coreboot information 11 Sep '08

11 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3572 to the coreboot source repository and caused the following changes: Change Log: >From Vincent Legoll: Use dev_path() to have nice debug output patch is run-time tested Trivial, thus: Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3572&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3572&device=epia-cn&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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#115: Enhance debug printk for pci_device
by coreboot 11 Sep '08

11 Sep '08

#115: Enhance debug printk for pci_device ---------------------------------------------------------+------------------ Reporter: Vincent Legoll <vincent.legoll(a)gmail.com> | Owner: somebody Type: enhancement | Status: new Priority: trivial | Milestone: Component: adlo | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | ---------------------------------------------------------+------------------ Use dev_path() to have nice debug output patch is run-time tested -- Ticket URL: </trac/ticket/115> coreboot <http://www.coreboot.org/>

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r3572 - trunk/coreboot-v2/src/devices
by svn＠coreboot.org 11 Sep '08

11 Sep '08

Author: stepan Date: 2008-09-11 08:52:22 +0200 (Thu, 11 Sep 2008) New Revision: 3572 Modified: trunk/coreboot-v2/src/devices/pci_device.c Log: >From Vincent Legoll: Use dev_path() to have nice debug output patch is run-time tested Trivial, thus: Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2008-09-10 20:40:46 UTC (rev 3571) +++ trunk/coreboot-v2/src/devices/pci_device.c 2008-09-11 06:52:22 UTC (rev 3572) @@ -923,7 +923,7 @@ if ( (id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { - printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id); + printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id); return NULL; } dev = alloc_dev(bus, &dummy.path);

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r3571 build service
by coreboot information 10 Sep '08

10 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3571 to the coreboot source repository and caused the following changes: Change Log: Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, this changes the superio to a Fintek F71805F as described at http://www.coreboot.org/Jetway_J7F2_Build_Tutorial It also creates the mainboard tree for this series of motherboards (Jetway J7F2 and J7F4). I've tested it with one motherboard (J7F2WE1G3), and I believe it works with the others, as the differences among them are mostly trivial (processor speed, chipset and quantity of LAN cards, audio chipset, etc.). A list of the relevant motherboards with specs can be found at http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 The irq_tables.c is copied directly from the epia-cn, because the one generated by getpir with the factory BIOS did not work properly while the EPIA-CN one did. Minor changes on checkin to cope with moved romcc in latest revision. NOTE: This board is broken until the issue introduced in r3567 is resolved. Signed-off-by: Alex Mauer <hawke(a)hawkesnest.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3571&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3571&device=epia-cn&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] Add VIA VT8237S support
by Rudolf Marek 10 Sep '08

10 Sep '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Its here! SATA issue solved (thanks for hint VIA!). This patch adds support for the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested on mine desktop) except of reverting the small change introduced by Bari (gpio/inta setup reg 0x5b). This should go for some board specific file. The change would broke at least mine board. But seems to be needed for jakllsch. Please someone try to fix it. Ok now back to patch. VT8237S peripherals: SPI flash - works, flashing fine SATA - now works, maybe need adjustments for your PCB USB - OK works IDE - OK works Network - OK works even if the board has no own flash - new code has to be called, default MAC will be 00:00:DE:AD:BE:EF. Sound - untested may work ACPI - works APIC - works Please try to ack the patch quickly, because a lot of people needs to dig into those files :) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFIwGW53J9wPJqZRNURAoLyAJoCFu/QwvZhTjnINYl6QPe4oNcCngCgiej+ PdLlpDgskjraKY/Y14LI1wU= =3s3C -----END PGP SIGNATURE-----

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r3571 - in trunk/coreboot-v2/src/mainboard: . jetway jetway/j7f24
by svn＠coreboot.org 10 Sep '08

10 Sep '08

Author: stepan Date: 2008-09-10 22:40:46 +0200 (Wed, 10 Sep 2008) New Revision: 3571 Added: trunk/coreboot-v2/src/mainboard/jetway/ trunk/coreboot-v2/src/mainboard/jetway/j7f24/ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c trunk/coreboot-v2/src/mainboard/jetway/j7f24/chip.h trunk/coreboot-v2/src/mainboard/jetway/j7f24/cmos.layout trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c trunk/coreboot-v2/src/mainboard/jetway/j7f24/mainboard.c Log: Add the "jetway j7f[24]*" mainboard. As compared to the Via Epia CN, this changes the superio to a Fintek F71805F as described at http://www.coreboot.org/Jetway_J7F2_Build_Tutorial It also creates the mainboard tree for this series of motherboards (Jetway J7F2 and J7F4). I've tested it with one motherboard (J7F2WE1G3), and I believe it works with the others, as the differences among them are mostly trivial (processor speed, chipset and quantity of LAN cards, audio chipset, etc.). A list of the relevant motherboards with specs can be found at http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16 The irq_tables.c is copied directly from the epia-cn, because the one generated by getpir with the factory BIOS did not work properly while the EPIA-CN one did. Minor changes on checkin to cope with moved romcc in latest revision. NOTE: This board is broken until the issue introduced in r3567 is resolved. Signed-off-by: Alex Mauer <hawke(a)hawkesnest.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Config.lb 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,144 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE object irq_tables.o end +if HAVE_MP_TABLE object mptable.o end +if HAVE_ACPI_TABLES + object fadt.o + object dsdt.o + object acpi_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc +dir /pc80 +config chip.h + +chip northbridge/via/cn700 # Northbridge + device pci_domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + device pci f.0 on end # IDE + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci 10.0 on end # OHCI + device pci 10.1 on end # OHCI + device pci 10.2 on end # OHCI + device pci 10.3 on end # OHCI + device pci 10.4 on end # EHCI + device pci 10.5 on end # UDCI + device pci 11.0 on # Southbridge LPC + chip superio/fintek/f71805f # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end + end + device pci 11.5 on end # AC'97 audio + # device pci 11.6 off end # AC'97 Modem + device pci 12.0 on end # Ethernet + end + end + device apic_cluster 0 on # APIC cluster + chip cpu/via/model_c7 # VIA C7 + device apic 0 on end # APIC + end + end +end Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,108 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses HAVE_ACPI_TABLES +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_PCI_ROM_RUN +uses CONFIG_CONSOLE_VGA +uses CONFIG_MAX_PCI_BUSES +uses TTYS0_BAUD +uses CONFIG_CHIP_NAME +uses CONFIG_VIDEO_MB +uses CONFIG_IOAPIC + +default ROM_SIZE = 512 * 1024 +default CONFIG_IOAPIC = 0 +default CONFIG_VIDEO_MB = 32 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_CONSOLE_VGA = 0 +default CONFIG_CHIP_NAME = 1 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_HARD_RESET = 0 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 10 +default HAVE_ACPI_TABLES = 0 +default HAVE_OPTION_TABLE = 1 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = ROM_SIZE +default USE_FALLBACK_IMAGE = 1 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default HOSTCC = "gcc" + +## +## Set this to the max PCI bus number you would ever use for PCI config I/O. +## Setting this number very high will make pci_locate_device() take a long +## time when it can't find a device. +## +default CONFIG_MAX_PCI_BUSES = 3 + +end + Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/auto.c 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/via/cn700/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "southbridge/via/vt8235/vt8235_early_serial.c" + +static void memreset_setup(void) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/via/cn700/raminit.c" + +static void enable_mainboard_devices(void) +{ + device_t dev; + u8 reg; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Southbridge not found!!!\n"); + + /* bit=0 means enable function (per CX700 datasheet) + * 5 16.1 USB 2 + * 4 16.0 USB 1 + * 3 15.0 SATA and PATA + * 2 16.2 USB 3 + * 1 16.4 USB EHCI + */ + pci_write_config8(dev, 0x50, 0x80); + + /* bit=1 means enable internal function (per CX700 datasheet) + * 3 Internal RTC + * 2 Internal PS2 Mouse + * 1 Internal KBC Configuration + * 0 Internal Keyboard Controller + */ + pci_write_config8(dev, 0x51, 0x1d); +} + +static const struct mem_controller ctrl = { + .d0f0 = 0x0000, + .d0f2 = 0x2000, + .d0f3 = 0x3000, + .d0f4 = 0x4000, + .d0f7 = 0x7000, + .d1f0 = 0x8000, + .channel0 = { 0x50 }, +}; + +static void main(unsigned long bist) +{ + unsigned long x; + device_t dev; + + /* Enable multifunction for northbridge. */ + pci_write_config8(ctrl.d0f0, 0x4f, 0x01); + + enable_vt8235_serial(); + uart_init(); + console_init(); + + print_spew("In auto.c:main()\r\n"); + + enable_smbus(); + smbus_fixup(&ctrl); + + if (bist == 0) { + print_debug("doing early_mtrr\r\n"); + early_mtrr_init(); + } + + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + print_debug("Enabling mainboard devices\r\n"); + enable_mainboard_devices(); + + ddr_ram_setup(&ctrl); + + /* ram_check(0, 640 * 1024); */ + + print_spew("Leaving auto.c:main()\r\n"); +} Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/chip.h 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_jetway_j7f24_ops; + +struct mainboard_jetway_j7f24_config { + int nothing; +}; Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/cmos.layout 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/irq_tables.c 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x11 << 3) | 0x0, /* Interrupt router device */ + 0x828, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x596, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3e, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/mainboard.c 2008-09-10 20:40:46 UTC (rev 3571) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_jetway_j7f24_ops = { + CHIP_NAME("Jetway J7F[24]* Mainboard") +};

1 0

Please list soldered/non-soldered BIOS
by David Englund 10 Sep '08

10 Sep '08

http://www.coreboot.org/GIGABYTE_GA-M57SLI-S4_Build_Tutorial#Before_you_begin "The fact that the BIOS is soldered onto the board complicates matters considerably, because it means that one flash of a faulty image will render your board unusable (it will be 'bricked')." Can anyone please list if the BIOS is soldered or non-soldered for each board at http://www.coreboot.org/Supported_Motherboards ? If you don't do this, then I have to do this by my self in my own research for coreboot supported boards so please answer. I also suggest that you make a contact link or a email address visible on the page. Can you do that? I'm looking forward to use coreboot so thank you for bringin up this fine piece of software to the community.

3 2

r3570 build service
by coreboot information 10 Sep '08

10 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3570 to the coreboot source repository and caused the following changes: Change Log: flashrom: Winbond W49V002A TEST_OK_ PROBE READ ERASE WRITE Per report from Kevin O'Connor. Thanks Kevin! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3570&device=epia-cn&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

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coreboot September 2008