coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

[PATCH] v3: Sanity-check file name length in LAR
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

Check that the filename in the LAR does neither overrun the archive nor exceed MAX_PATHLEN. Needs a generic max() function to compile. Where do we want that function? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-lar_overrun_prevention/lib/lar.c =================================================================== --- corebootv3-lar_overrun_prevention/lib/lar.c (Revision 785) +++ corebootv3-lar_overrun_prevention/lib/lar.c (Arbeitskopie) @@ -69,6 +69,7 @@ { char *walk, *fullname; struct lar_header *header; + int headroom; printk(BIOS_INFO, "LAR: Attempting to open '%s'.\n", filename); printk(BIOS_SPEW, "LAR: Start %p len 0x%x\n", archive->start, @@ -123,7 +124,11 @@ printk(BIOS_SPEW, "LAR: seen member %s\n", fullname); // FIXME: check checksum - if (strcmp(fullname, filename) == 0) { + /* Check that the name does neither overrun the archive nor + * exceed MAX_PATHLEN. + */ + headroom = max(archive->len - (int)((char *)archive->start - fullname), MAX_PATHLEN); + if (strncmp(fullname, filename, headroom) == 0) { printk(BIOS_SPEW, "LAR: CHECK %s @ %p\n", fullname, header); result->start = walk + ntohl(header->offset); result->len = ntohl(header->len); -- http://www.hailfinger.org/

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Re: [coreboot] r788 - in coreboot-v3: device include/arch/x86/amd/k8 mainboard/amd/serengeti northbridge/amd/k8
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

On 18.08.2008 22:31, svn(a)coreboot.org wrote: > Author: rminnich > Date: 2008-08-18 22:31:34 +0200 (Mon, 18 Aug 2008) > New Revision: 788 > > Log: > per discussion w/AMD, remove all conditionals based on REV_F. > > It's all REV_F now and we're wasting time pretending otherwise. This > change simplifies the code and will continue to simplify the code. > > Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> > Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> > Nice! Regards, Carl-Daniel

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r788 - in coreboot-v3: device include/arch/x86/amd/k8 mainboard/amd/serengeti northbridge/amd/k8
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: rminnich Date: 2008-08-18 22:31:34 +0200 (Mon, 18 Aug 2008) New Revision: 788 Modified: coreboot-v3/device/hypertransport.c coreboot-v3/include/arch/x86/amd/k8/k8.h coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/cpu.c coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/incoherent_ht.c coreboot-v3/northbridge/amd/k8/raminit.c Log: per discussion w/AMD, remove all conditionals based on REV_F. It's all REV_F now and we're wasting time pretending otherwise. This change simplifies the code and will continue to simplify the code. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/hypertransport.c =================================================================== --- coreboot-v3/device/hypertransport.c 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/device/hypertransport.c 2008-08-18 20:31:34 UTC (rev 788) @@ -95,13 +95,7 @@ } /* AMD K8 unsupported 1GHz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { -#if K8_HT_FREQ_1G_SUPPORT == 1 -#if K8_REV_F_SUPPORT == 0 - if (is_cpu_pre_e0()) { // Only e0 later support 1GHz HT. - freq_cap &= ~(1 << HT_FREQ_1000Mhz); - } -#endif -#else +#ifndef K8_HT_FREQ_1G_SUPPORT freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h =================================================================== --- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-18 20:31:34 UTC (rev 788) @@ -306,61 +306,17 @@ #ifndef ASSEMBLY /* Steppings of the K8 cpu */ -enum steppings { - A0, - A1, - A2, - B0, - C0, - CG, +enum { + A0= 0x0f00, + B3= 0x0f41, + C0= 0x0f48, + CG, /* value not yet known */ + D0= 0x10f00, + E0= 0x20f00, + F0= 0x40f00, + F2= 0x40f02, }; -/* cpu version -- no support for f0 yet */ -static inline int is_cpu_rev_a0(void) -{ - return (cpuid_eax(1) & 0xfffef) == 0x0f00; -} -static inline int is_cpu_pre_c0(void) -{ - return (cpuid_eax(1) & 0xfffef) < 0x0f48; -} -static inline int is_cpu_c0(void) -{ - return (cpuid_eax(1) & 0xfffef) == 0x0f48; -} - -static inline int is_cpu_pre_b3(void) -{ - return (cpuid_eax(1) & 0xfffef) < 0x0f41; -} - -static inline int is_cpu_b3(void) -{ - return (cpuid_eax(1) & 0xfffef) == 0x0f41; -} -//AMD_D0_SUPPORT -static inline int is_cpu_pre_d0(void) -{ - return (cpuid_eax(1) & 0xfff0f) < 0x10f00; -} - -static inline int is_cpu_d0(void) -{ - return (cpuid_eax(1) & 0xfff0f) == 0x10f00; -} - -//AMD_E0_SUPPORT -static inline int is_cpu_pre_e0(void) -{ - return (cpuid_eax(1) & 0xfff0f) < 0x20f00; -} - -static inline int is_cpu_e0(void) -{ - return (cpuid_eax(1) & 0xfff00) == 0x20f00; -} - - /* note: we'd like to have this sysinfo common to all K8, there's no need to * have one different kind per different kind of k8 at this point. */ Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-08-18 20:31:34 UTC (rev 788) @@ -26,6 +26,7 @@ $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/northbridge/amd/k8/incoherent_ht.c \ $(src)/northbridge/amd/k8/libstage1.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/lib/clog2.c INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-18 20:31:34 UTC (rev 788) @@ -286,10 +286,7 @@ freq_cap = pci_conf1_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 - #if CONFIG_K8_REV_F_SUPPORT == 0 - if (!is_cpu_pre_e0()) - #endif +#ifdef CONFIG_K8_HT_FREQ_1G_SUPPORT { return freq_cap; } @@ -1595,9 +1592,6 @@ { unsigned node; int dual_core = 0; -#if CONFIG_K8_REV_F_SUPPORT == 0 - int rev_a0; -#endif #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; @@ -1617,9 +1611,6 @@ */ printk(BIOS_SPEW, "coherent_ht_finalize\r\n"); -#if CONFIG_K8_REV_F_SUPPORT == 0 - rev_a0 = is_cpu_rev_a0(); -#endif for (node = 0; node < nodes; node++) { u32 dev; u32 val; @@ -1648,13 +1639,6 @@ (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_conf1_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if CONFIG_K8_REV_F_SUPPORT == 0 - if (rev_a0) { - pci_conf1_write_config32(dev, 0x94, 0); - pci_conf1_write_config32(dev, 0xb4, 0); - pci_conf1_write_config32(dev, 0xd4, 0); - } -#endif } printk(BIOS_SPEW, "done\r\n"); @@ -1668,49 +1652,6 @@ u32 dev; u32 cmd; dev = NODE_MC(node); -#if CONFIG_K8_REV_F_SUPPORT == 0 - if (is_cpu_pre_c0()) { - - /* Errata 66 - * Limit the number of downstream posted requests to 1 - */ - cmd = pci_conf1_read_config32(dev, 0x70); - if ((cmd & (3 << 0)) != 2) { - cmd &= ~(3<<0); - cmd |= (2<<0); - pci_conf1_write_config32(dev, 0x70, cmd ); - needs_reset = 1; - } - cmd = pci_conf1_read_config32(dev, 0x7c); - if ((cmd & (3 << 4)) != 0) { - cmd &= ~(3<<4); - cmd |= (0<<4); - pci_conf1_write_config32(dev, 0x7c, cmd ); - needs_reset = 1; - } - /* Clock Power/Timing Low */ - cmd = pci_conf1_read_config32(dev, 0xd4); - if (cmd != 0x000D0001) { - cmd = 0x000D0001; - pci_conf1_write_config32(dev, 0xd4, cmd); - needs_reset = 1; /* Needed? */ - } - - } - else if (is_cpu_pre_d0()) { // d0 later don't need it - u32 cmd_ref; - /* Errata 98 - * Set Clk Ramp Hystersis to 7 - * Clock Power/Timing Low - */ - cmd_ref = 0x04e20707; /* Registered */ - cmd = pci_conf1_read_config32(dev, 0xd4); - if(cmd != cmd_ref) { - pci_conf1_write_config32(dev, 0xd4, cmd_ref ); - needs_reset = 1; /* Needed? */ - } - } -#endif } return needs_reset; } Modified: coreboot-v3/northbridge/amd/k8/cpu.c =================================================================== --- coreboot-v3/northbridge/amd/k8/cpu.c 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/northbridge/amd/k8/cpu.c 2008-08-18 20:31:34 UTC (rev 788) @@ -129,6 +129,7 @@ } +#warning clean this mess up e0_later_single_core = 0; if (dev && dev->enabled) { j = pci_read_config32(dev, 0xe8); @@ -141,11 +142,7 @@ // That is the typical case if(j == 0 ){ - #ifndef CONFIG_K8_REV_F_SUPPORT - e0_later_single_core = is_e0_later_in_bsp(i); // single core - #else - e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 - #endif + e0_later_single_core = 1; // we are all f0 or later now. is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 } else { e0_later_single_core = 0; } Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-18 20:31:34 UTC (rev 788) @@ -262,9 +262,6 @@ * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ - #ifndef CONFIG_K8_REV_F_SUPPORT - if (!is_cpu_pre_e0()) { - #endif mem_hole = get_hw_mem_hole_info(); @@ -303,12 +300,8 @@ #endif } -#ifndef CONFIG_K8_REV_F_SUPPORT - } // is_cpu_pre_e0 #endif -#endif - idx = 0x10; for(i = 0; i < 8; i++) { u32 base, limit; @@ -346,9 +339,6 @@ } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) - #ifndef CONFIG_K8_REV_F_SUPPORT - if(!is_cpu_pre_e0() ) - #endif sizek += hoist_memory(mmio_basek,i); #endif Modified: coreboot-v3/northbridge/amd/k8/incoherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-18 20:31:34 UTC (rev 788) @@ -158,13 +158,7 @@ /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 - if (is_cpu_pre_e0()) { // only E0 later support 1GHz - freq_cap &= ~(1 << HT_FREQ_1000Mhz); - } - #endif - #else + #ifndef K8_HT_FREQ_1G_SUPPORT freq_cap &= ~(1 << HT_FREQ_1000Mhz); #endif } Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-18 20:18:53 UTC (rev 787) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-18 20:31:34 UTC (rev 788) @@ -24,6 +24,7 @@ 2004.12 yhlu add D0 support 2005.02 yhlu add E0 memory hole support */ +#warning use raminit_f.c not this one. /* not yet #if K8_REV_F_SUPPORT == 1 #include "raminit_f.c"

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[PATCH] [RFC] v3: CS5536 cleanup
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

Clean up Geode companion chip CS5536 code and improve VPCI hiding debug message. This also eliminates a few dev_find_pci_device(). I'm not happy with the new code yet. hide_vpci() should have a variant which takes a struct device *. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Revision 676) +++ LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -175,8 +175,7 @@ static void enable_ide_nand_flash_header(void) { /* Tell VSA to use FLASH PCI header. Not IDE header. */ - outl(0x80007A40, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + hide_vpci(0x800079C4); } #define RTC_CENTURY 0x32 @@ -240,16 +239,13 @@ * * @param sb Southbridge config structure. */ -static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb) +static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb, + struct device *dev) { struct msr msr; u16 addr = 0; u32 gpio_addr; - struct device *dev; - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); - gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); gpio_addr &= ~1; /* Clear I/O bit */ printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr); @@ -418,7 +414,7 @@ { u32 *bar; struct msr msr; - struct device *dev; + struct device *dev, *otg_dev; dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); @@ -440,9 +436,9 @@ *(bar + HCCPARAMS) = 0x00005012; } - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, + otg_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { + if (otg_dev) { bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCMUX) &= PUEN_SET; @@ -472,9 +468,7 @@ *(bar + UDCDEVCTL) |= UDC_SD_SET; } - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { + if (otg_dev) { bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCCTL) |= PADEN_SET; *(bar + UOCCAP) |= APU_SET; @@ -482,15 +476,8 @@ } /* Disable virtual PCI UDC and OTG headers. */ - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if (dev) - pci_write_config32(dev, 0x7C, 0xDEADBEEF); - - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) - pci_write_config32(dev, 0x7C, 0xDEADBEEF); + hide_vpci(0x80007e00); /* UDC */ + hide_vpci(0x80007f00); /* OTG */ } /** @@ -603,9 +590,19 @@ static void hide_vpci(u32 vpci_devid) { - /* Hide unwanted virtual PCI device. */ - printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X\n", - vpci_devid); + /* Hide unwanted virtual PCI device. + * bits 0 -> 1 zero + * bits 2 -> 7 target dword within the target function + * (zero if we're disabling entire pci devices) + * bits 8 -> 10 target function of the device + * bits 11 -> 15 target pci device + * bits 16 -> 23 pci bus + * bits 24 -> 30 reserved and set to zero + * bit 31 triggers the config cycle + */ + printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n", + vpci_devid, (vpci_devid >> 16) & 0xff, + (vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7); outl(vpci_devid + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); } @@ -630,7 +627,7 @@ setup_i8259(); lpc_init(sb); - uarts_init(sb); + uarts_init(sb, dev); if (sb->enable_gpio_int_route) { printk(BIOS_SPEW, "cs5536: call vr_write\n");

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r787 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: hailfinger Date: 2008-08-18 22:18:53 +0200 (Mon, 18 Aug 2008) New Revision: 787 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: - Improve VPCI hiding debug message and add doxygen comments. - Replace a hand-crafted open-coded VPCI hiding sequence. Build tested on all relevant targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-18 20:13:11 UTC (rev 786) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-18 20:18:53 UTC (rev 787) @@ -89,6 +89,28 @@ }; /** + * Hide unwanted virtual PCI device. + * + * @param vpci_devid The bus location of the device to be hidden. + * bits 0 -> 1 zero + * bits 2 -> 7 target dword within the target function + * (zero if we're disabling entire pci devices) + * bits 8 -> 10 target function of the device + * bits 11 -> 15 target pci device + * bits 16 -> 23 pci bus + * bits 24 -> 30 reserved and set to zero + * bit 31 triggers the config cycle + */ +static void hide_vpci(u32 vpci_devid) +{ + printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n", + vpci_devid, (vpci_devid >> 16) & 0xff, + (vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7); + outl(vpci_devid + 0x7C, 0xCF8); + outl(0xDEADBEEF, 0xCFC); +} + +/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -175,8 +197,7 @@ static void enable_ide_nand_flash_header(void) { /* Tell VSA to use FLASH PCI header. Not IDE header. */ - outl(0x80007A40, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + hide_vpci(0x800079C4); } #define RTC_CENTURY 0x32 @@ -621,16 +642,6 @@ pci_write_config32(dev, IDE_CFG, ide_cfg); } - -static void hide_vpci(u32 vpci_devid) -{ - /* Hide unwanted virtual PCI device. */ - printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X\n", - vpci_devid); - outl(vpci_devid + 0x7C, 0xCF8); - outl(0xDEADBEEF, 0xCFC); -} - /** * TODO. *

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Re: [coreboot] r783 - coreboot-v3/arch/x86
by Stefan Reinauer 18 Aug '08

18 Aug '08

Carl-Daniel Hailfinger asked: > > - /* we can't statically init this hack. */ > + /* Why can't we statically init this hack? */ > No global variables in stage 1. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[PATCH] v3: move console log level management to global variable infrastructure
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

Move console log level management to global variable infrastructure. The existing code does not work due to the characteristics of stage1. This has been broken since r729. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-console_loglevel_global_var/include/console.h =================================================================== --- corebootv3-console_loglevel_global_var/include/console.h (Revision 785) +++ corebootv3-console_loglevel_global_var/include/console.h (Arbeitskopie) @@ -37,6 +37,7 @@ void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); +void console_loglevel_init(void); #ifdef CONFIG_CONSOLE_BUFFER void printk_buffer_init(void); void printk_buffer_move(void *newaddr, int newsize); @@ -69,6 +70,7 @@ #ifdef CONFIG_CONSOLE_BUFFER struct printk_buffer *printk_buffer; #endif + unsigned int loglevel; }; int printk(int msg_level, const char *fmt, ...) __attribute__((format (printf, 2, 3))); Index: corebootv3-console_loglevel_global_var/lib/console.c =================================================================== --- corebootv3-console_loglevel_global_var/lib/console.c (Revision 785) +++ corebootv3-console_loglevel_global_var/lib/console.c (Arbeitskopie) @@ -8,8 +8,6 @@ int vtxprintf(void (*)(unsigned char, void *arg), void *arg, const char *, va_list); -static unsigned int loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - /** * set the console log level * There are no invalid settings, although there are ones that @@ -21,7 +19,7 @@ if (level > BIOS_SPEW) printk(BIOS_ALWAYS, "Warning: ridiculous log level setting: %d (max %d)\n", level, BIOS_SPEW); - loglevel = level; + global_vars()->loglevel = level; } /** @@ -31,9 +29,14 @@ */ static unsigned int console_loglevel(void) { - return loglevel; + return global_vars()->loglevel; } +void console_loglevel_init(void) +{ + set_loglevel(CONFIG_DEFAULT_CONSOLE_LOGLEVEL); +} + #ifdef CONFIG_CONSOLE_BUFFER struct printk_buffer *printk_buffer_addr(void) { Index: corebootv3-console_loglevel_global_var/arch/x86/stage1.c =================================================================== --- corebootv3-console_loglevel_global_var/arch/x86/stage1.c (Revision 785) +++ corebootv3-console_loglevel_global_var/arch/x86/stage1.c (Arbeitskopie) @@ -89,6 +89,12 @@ { memset(globvars, 0, sizeof(struct global_vars)); *(struct global_vars **)(bottom_of_stack() - sizeof(struct global_vars *)) = globvars; +#ifdef CONFIG_CONSOLE_BUFFER + /* Initialize the printk buffer. */ + printk_buffer_init(); +#endif + console_loglevel_init(); + } void dump_mem_range(int msg_level, unsigned char *buf, int size) @@ -163,11 +169,6 @@ */ global_vars_init(&globvars); -#ifdef CONFIG_CONSOLE_BUFFER - /* Initialize the printk buffer. NEVER run this on an AP! */ - printk_buffer_init(); -#endif - hardware_stage1(); // -- http://www.hailfinger.org/ Index: corebootv3-console_loglevel_global_var/include/console.h =================================================================== --- corebootv3-console_loglevel_global_var/include/console.h (Revision 785) +++ corebootv3-console_loglevel_global_var/include/console.h (Arbeitskopie) @@ -37,6 +37,7 @@ void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); +void console_loglevel_init(void); #ifdef CONFIG_CONSOLE_BUFFER void printk_buffer_init(void); void printk_buffer_move(void *newaddr, int newsize); @@ -69,6 +70,7 @@ #ifdef CONFIG_CONSOLE_BUFFER struct printk_buffer *printk_buffer; #endif + unsigned int loglevel; }; int printk(int msg_level, const char *fmt, ...) __attribute__((format (printf, 2, 3))); Index: corebootv3-console_loglevel_global_var/lib/console.c =================================================================== --- corebootv3-console_loglevel_global_var/lib/console.c (Revision 785) +++ corebootv3-console_loglevel_global_var/lib/console.c (Arbeitskopie) @@ -8,8 +8,6 @@ int vtxprintf(void (*)(unsigned char, void *arg), void *arg, const char *, va_list); -static unsigned int loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - /** * set the console log level * There are no invalid settings, although there are ones that @@ -21,7 +19,7 @@ if (level > BIOS_SPEW) printk(BIOS_ALWAYS, "Warning: ridiculous log level setting: %d (max %d)\n", level, BIOS_SPEW); - loglevel = level; + global_vars()->loglevel = level; } /** @@ -31,9 +29,14 @@ */ static unsigned int console_loglevel(void) { - return loglevel; + return global_vars()->loglevel; } +void console_loglevel_init(void) +{ + set_loglevel(CONFIG_DEFAULT_CONSOLE_LOGLEVEL); +} + #ifdef CONFIG_CONSOLE_BUFFER struct printk_buffer *printk_buffer_addr(void) { Index: corebootv3-console_loglevel_global_var/arch/x86/stage1.c =================================================================== --- corebootv3-console_loglevel_global_var/arch/x86/stage1.c (Revision 785) +++ corebootv3-console_loglevel_global_var/arch/x86/stage1.c (Arbeitskopie) @@ -89,6 +89,12 @@ { memset(globvars, 0, sizeof(struct global_vars)); *(struct global_vars **)(bottom_of_stack() - sizeof(struct global_vars *)) = globvars; +#ifdef CONFIG_CONSOLE_BUFFER + /* Initialize the printk buffer. */ + printk_buffer_init(); +#endif + console_loglevel_init(); + } void dump_mem_range(int msg_level, unsigned char *buf, int size) @@ -163,11 +169,6 @@ */ global_vars_init(&globvars); -#ifdef CONFIG_CONSOLE_BUFFER - /* Initialize the printk buffer. NEVER run this on an AP! */ - printk_buffer_init(); -#endif - hardware_stage1(); //

2 2

r786 - in coreboot-v3: arch/x86 include lib
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: hailfinger Date: 2008-08-18 22:13:11 +0200 (Mon, 18 Aug 2008) New Revision: 786 Modified: coreboot-v3/arch/x86/stage1.c coreboot-v3/include/console.h coreboot-v3/lib/console.c Log: Move console log level management to global variable infrastructure. The existing code does not work due to the characteristics of stage1. This has been broken since r729. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-08-18 16:54:12 UTC (rev 785) +++ coreboot-v3/arch/x86/stage1.c 2008-08-18 20:13:11 UTC (rev 786) @@ -89,6 +89,12 @@ { memset(globvars, 0, sizeof(struct global_vars)); *(struct global_vars **)(bottom_of_stack() - sizeof(struct global_vars *)) = globvars; +#ifdef CONFIG_CONSOLE_BUFFER + /* Initialize the printk buffer. */ + printk_buffer_init(); +#endif + console_loglevel_init(); + } void dump_mem_range(int msg_level, unsigned char *buf, int size) @@ -163,11 +169,6 @@ */ global_vars_init(&globvars); -#ifdef CONFIG_CONSOLE_BUFFER - /* Initialize the printk buffer. NEVER run this on an AP! */ - printk_buffer_init(); -#endif - hardware_stage1(); // Modified: coreboot-v3/include/console.h =================================================================== --- coreboot-v3/include/console.h 2008-08-18 16:54:12 UTC (rev 785) +++ coreboot-v3/include/console.h 2008-08-18 20:13:11 UTC (rev 786) @@ -37,6 +37,7 @@ void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); +void console_loglevel_init(void); #ifdef CONFIG_CONSOLE_BUFFER void printk_buffer_init(void); void printk_buffer_move(void *newaddr, int newsize); @@ -69,6 +70,7 @@ #ifdef CONFIG_CONSOLE_BUFFER struct printk_buffer *printk_buffer; #endif + unsigned int loglevel; }; int printk(int msg_level, const char *fmt, ...) __attribute__((format (printf, 2, 3))); Modified: coreboot-v3/lib/console.c =================================================================== --- coreboot-v3/lib/console.c 2008-08-18 16:54:12 UTC (rev 785) +++ coreboot-v3/lib/console.c 2008-08-18 20:13:11 UTC (rev 786) @@ -8,8 +8,6 @@ int vtxprintf(void (*)(unsigned char, void *arg), void *arg, const char *, va_list); -static unsigned int loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - /** * set the console log level * There are no invalid settings, although there are ones that @@ -21,7 +19,7 @@ if (level > BIOS_SPEW) printk(BIOS_ALWAYS, "Warning: ridiculous log level setting: %d (max %d)\n", level, BIOS_SPEW); - loglevel = level; + global_vars()->loglevel = level; } /** @@ -31,9 +29,14 @@ */ static unsigned int console_loglevel(void) { - return loglevel; + return global_vars()->loglevel; } +void console_loglevel_init(void) +{ + set_loglevel(CONFIG_DEFAULT_CONSOLE_LOGLEVEL); +} + #ifdef CONFIG_CONSOLE_BUFFER struct printk_buffer *printk_buffer_addr(void) {

1 0

[PATCH] libpayload: correct tinycurses color on the VGA console
by Ulf Jordan 18 Aug '08

18 Aug '08

Hello! The attached patch makes the VGA output from tinycurses match the curses color macros. Build and run tested under QEMU with coreinfo+coreboot-v3, bayou-0.3+coreboot-v3 (now looks very red, just like the color pairs specify...), and tint-0.03b+coreboot-v3. /ulf

2 2

r3517 - in trunk/payloads/libpayload: . curses
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: jcrouse Date: 2008-08-18 21:29:41 +0200 (Mon, 18 Aug 2008) New Revision: 3517 Modified: trunk/payloads/libpayload/Config.in trunk/payloads/libpayload/curses/tinycurses.c Log: Add a kconfig option to choose between outputing ACS characters or their plain ASCII fallbacks over serial console. Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/Config.in =================================================================== --- trunk/payloads/libpayload/Config.in 2008-08-18 19:28:42 UTC (rev 3516) +++ trunk/payloads/libpayload/Config.in 2008-08-18 19:29:41 UTC (rev 3517) @@ -68,6 +68,20 @@ depends on SERIAL_SET_SPEED default 115200 +config SERIAL_ACS_FALLBACK + bool "Use plain ASCII characters for ACS" + default n + depends on SERIAL_CONSOLE + help + The alternate character set (ACS) is used for drawing lines and + displaying a couple of other special graphics characters. The + ACS characters generally look good on screen, but can be difficult + to cut and paste from a terminal window to a text editor. + + Say 'y' here if you want to always use plain ASCII characters to + approximate the appearance of ACS characters on the serial port + console. + config VIDEO_CONSOLE bool "See output on a video console" default y Modified: trunk/payloads/libpayload/curses/tinycurses.c =================================================================== --- trunk/payloads/libpayload/curses/tinycurses.c 2008-08-18 19:28:42 UTC (rev 3516) +++ trunk/payloads/libpayload/curses/tinycurses.c 2008-08-18 19:29:41 UTC (rev 3517) @@ -110,6 +110,9 @@ '|', '<', '>', '*', '!', 'f', 'o', ' ', }; +#ifdef CONFIG_SERIAL_ACS_FALLBACK +chtype serial_acs_map[128]; +#else /* See acsc of vt100. */ chtype serial_acs_map[128] = { @@ -130,6 +133,7 @@ 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~', 0, }; +#endif /* See acsc of linux. */ chtype console_acs_map[128] =

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coreboot August 2008