coreboot August 2008

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r3529 - trunk/coreboot-v2/targets/tyan/s2912_fam10
by svn＠coreboot.org 20 Aug '08

20 Aug '08

Author: stepan Date: 2008-08-20 11:17:30 +0200 (Wed, 20 Aug 2008) New Revision: 3529 Modified: trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb Log: this port seems somehow broken.. Now, is it using FAILOVER, or is it not?! ./s2912_fam10/Options.lb:default FALLBACK_SIZE=ROM_SIZE-0x01000 Please, someone with the board test this and fix it accordingly. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb 2008-08-19 21:51:39 UTC (rev 3528) +++ trunk/coreboot-v2/targets/tyan/s2912_fam10/Config-abuild.lb 2008-08-20 09:17:30 UTC (rev 3529) @@ -23,20 +23,24 @@ __COMPRESSION__ -romimage "fallback" +option ROM_SIZE = 0x80000 +option FALLBACK_SIZE = 0x40000 +option FAILOVER_SIZE = 0x00 + +romimage "normal" option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x3f0000 + option ROM_IMAGE_SIZE=0x24000 option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-fallback" + option COREBOOT_EXTRA_VERSION=".0-Normal" payload __PAYLOAD__ end -romimage "failover" +romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x3f0000 + option ROM_IMAGE_SIZE=0x24000 option XIP_ROM_SIZE=0x40000 - option COREBOOT_EXTRA_VERSION=".0-failover" + option COREBOOT_EXTRA_VERSION=".0-Fallback" payload __PAYLOAD__ end -buildrom ./coreboot.rom ROM_SIZE "fallback" "failover" +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

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r3528 build service
by coreboot information 20 Aug '08

20 Aug '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3528 to the coreboot source repository and caused the following changes: Change Log: Add support for MSI KT4V to flashrom. The KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet). Signed-off-by: Sean Nelson <snelson(a)nmt.edu> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of tyan:s2912_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3528&device=s2912_fam10&ve… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3527 build service
by coreboot information 20 Aug '08

20 Aug '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3527 to the coreboot source repository and caused the following changes: Change Log: trivial fix for memcpy return code in case someone uses it. Thanks to Ulf Jordan for figuring this out! Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of tyan:s2912_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3527&device=s2912_fam10&ve… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3526 build service
by coreboot information 20 Aug '08

20 Aug '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3526 to the coreboot source repository and caused the following changes: Change Log: Add Tyan S2912 platform with AMD Family 10 support. Thanks Arne. Good job. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Compilation of tyan:s2912_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3526&device=s2912_fam10&ve… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[flashrom] MSI KT3 Ultra2 support
by Sean Nelson 20 Aug '08

20 Aug '08

Quick patch to add KT3 Ultra2 support to flashrom; board is autodetected. Signed-off-by: Sean Nelson <snelson(a)nmt.edu> --- IDE's subsystem IDs is the same as the vendor/device IDs; kinda odd, must use original rev of VT8235 Index: board_enable.c =================================================================== --- board_enable.c (revision 3528) +++ board_enable.c (working copy) @@ -626,6 +626,8 @@ }; struct board_pciid_enable board_pciid_enables[] = { + {0x1106, 0x0571, 0x1106, 0x0571, 0x0000, 0x0000, 0x0000, 0x0000, + "msi", "kt3-ultra2", "MSI KT3 ULTRA2", board_msi_kt4v}, {0x1106, 0x0571, 0x1462, 0x7120, 0x0000, 0x0000, 0x0000, 0x0000, "msi", "kt4v", "MSI KT4V", board_msi_kt4v}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028,

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r220 - buildrom-devel/packages/seabios
by svn＠coreboot.org 19 Aug '08

19 Aug '08

Author: myles Date: 2008-08-20 00:48:06 +0200 (Wed, 20 Aug 2008) New Revision: 220 Modified: buildrom-devel/packages/seabios/hardcode.diff buildrom-devel/packages/seabios/seabios.mk Log: This trivial patch changes updates the #defines and a typo for seabios. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/packages/seabios/hardcode.diff =================================================================== --- buildrom-devel/packages/seabios/hardcode.diff 2008-08-11 15:01:35 UTC (rev 219) +++ buildrom-devel/packages/seabios/hardcode.diff 2008-08-19 22:48:06 UTC (rev 220) @@ -1,6 +1,6 @@ ---- a/src/config.h 2008-07-03 15:12:21.000000000 -0600 -+++ b/src/config.h 2008-07-03 15:13:23.000000000 -0600 -@@ -14,31 +14,31 @@ +--- a/src/config.h 2008-07-21 10:56:45.000000000 -0600 ++++ b/src/config.h 2008-07-21 10:59:39.000000000 -0600 +@@ -13,13 +13,13 @@ #endif // Configure as a coreboot payload. @@ -15,29 +15,14 @@ -#define CONFIG_DEBUG_SERIAL 0 +#define CONFIG_DEBUG_SERIAL 1 --#define CONFIG_FLOPPY_SUPPORT 1 -+#define CONFIG_FLOPPY_SUPPORT 0 - #define CONFIG_PS2_MOUSE 1 - #define CONFIG_ATA 1 - #define CONFIG_KBD_CALL_INT15_4F 1 - #define CONFIG_CDROM_BOOT 1 - #define CONFIG_CDROM_EMU 1 - // Support generation of a PIR table in 0xf000 segment (for emulators) --#define CONFIG_PIRTABLE 1 -+#define CONFIG_PIRTABLE 1 - // Support generation of ACPI PIR tables (for emulators) --#define CONFIG_ACPI 1 -+#define CONFIG_ACPI 1 + // Support for int13 floppy drive access + #define CONFIG_FLOPPY_SUPPORT 1 +@@ -36,7 +36,7 @@ // Support int 1a/b1 PCI BIOS calls --#define CONFIG_PCIBIOS 1 -+#define CONFIG_PCIBIOS 1 + #define CONFIG_PCIBIOS 1 + // Maximum number of PCI busses. +-#define CONFIG_PCI_BUS_COUNT 2 ++#define CONFIG_PCI_BUS_COUNT 6 // Support int 15/53 APM BIOS calls --#define CONFIG_APMBIOS 1 -+#define CONFIG_APMBIOS 1 - - /* define it if the (emulated) hardware supports SMM mode */ --#define CONFIG_USE_SMM 1 -+#define CONFIG_USE_SMM 1 - - /* if true, put the MP float table and ACPI RSDT in EBDA and the MP - table in RAM. Unfortunately, Linux has bugs with that, so we prefer + #define CONFIG_APMBIOS 1 + // Support int 19/18 system bootup support Modified: buildrom-devel/packages/seabios/seabios.mk =================================================================== --- buildrom-devel/packages/seabios/seabios.mk 2008-08-11 15:01:35 UTC (rev 219) +++ buildrom-devel/packages/seabios/seabios.mk 2008-08-19 22:48:06 UTC (rev 220) @@ -33,7 +33,7 @@ @ touch $@ $(SEABIOS_STAMP_DIR)/.patched: $(SEABIOS_STAMP_DIR)/.unpacked - @ echo "Patching mkelfimage..." + @ echo "Patching SeaBIOS..." @ $(BIN_DIR)/doquilt.sh $(SEABIOS_SRC_DIR) $(SEABIOS_PATCHES) @ touch $@

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[flashrom] support for MSI KT4V; autodetected
by Sean Nelson 19 Aug '08

19 Aug '08

Patch adds support for MSI KT4V to flashrom; the KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v" Thanks to Eightdot for finding the enable Thanks to Uwe for helping finalize the patch Signed-off-by: Sean Nelson <snelson(a)nmt.edu> --- see patch for details

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r3528 - trunk/util/flashrom
by svn＠coreboot.org 19 Aug '08

19 Aug '08

Author: uwe Date: 2008-08-19 23:51:39 +0200 (Tue, 19 Aug 2008) New Revision: 3528 Modified: trunk/util/flashrom/board_enable.c Log: Add support for MSI KT4V to flashrom. The KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet). Signed-off-by: Sean Nelson <snelson(a)nmt.edu> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-08-19 19:18:58 UTC (rev 3527) +++ trunk/util/flashrom/board_enable.c 2008-08-19 21:51:39 UTC (rev 3528) @@ -548,6 +548,51 @@ } /** + * Winbond W83697HF Super I/O + VIA VT8235 southbridge + * + * Suited for: + * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT3 Ultra2: AMD K7 + VIA KT333 + VT8235 + */ +static int board_msi_kt4v(const char *name) +{ + struct pci_dev *dev; + uint8_t val; + uint32_t val2; + uint16_t port; + + dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + return -1; + } + + val = pci_read_byte(dev, 0x59); + val &= 0x0c; + pci_write_byte(dev, 0x59, val); + + /* We need the I/O Base Address for this board's flash enable. */ + port = pci_read_word(dev, 0x88) & 0xff80; + + /* Starting at 'I/O Base + 0x4c' is the GPO Port Output Value. + * We must assert GPO12 for our enable, which is in 0x4d. + */ + val2 = INB(port + 0x4d); + val2 |= 0x10; + OUTB(val2, port + 0x4d); + + /* Raise ROM MEMW# line on Winbond W83697 Super I/O. */ + w836xx_ext_enter(0x2e); + if (!(wbsio_read(0x2e, 0x24) & 0x02)) { /* Flash ROM enabled? */ + /* Enable MEMW# and set ROM size select to max. (4M). */ + wbsio_mask(0x2e, 0x24, 0x28, 0x28); + } + w836xx_ext_leave(0x2e); + + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -581,6 +626,8 @@ }; struct board_pciid_enable board_pciid_enables[] = { + {0x1106, 0x0571, 0x1462, 0x7120, 0x0000, 0x0000, 0x0000, 0x0000, + "msi", "kt4v", "MSI KT4V", board_msi_kt4v}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS P4B266", ich2_gpio22_raise}, {0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,

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[PATCH 3/6] libpayload memalign
by Stefan Reinauer 19 Aug '08

19 Aug '08

-- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add memalign, get aligned memory. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Index: include/libpayload.h =================================================================== --- include/libpayload.h (revision 3519) +++ include/libpayload.h (working copy) @@ -158,6 +158,7 @@ void *malloc(size_t size); void *calloc(size_t nmemb, size_t size); void *realloc(void *ptr, size_t size); +void *memalign(size_t align, size_t size); /* libc/exec.c */ int exec(long addr, int argc, char **argv); Index: libc/malloc.c =================================================================== --- libc/malloc.c (revision 3519) +++ libc/malloc.c (working copy) @@ -63,6 +63,7 @@ #define IS_FREE(_h) (((_h) & (MAGIC | FLAG_FREE)) == (MAGIC | FLAG_FREE)) #define HAS_MAGIC(_h) (((_h) & MAGIC) == MAGIC) +static int free_aligned(void* addr); void print_malloc_map(void); static void setup(void) @@ -164,6 +165,8 @@ { hdrtype_t hdr; + if (free_aligned(ptr)) return; + ptr -= HDRSIZE; /* Sanity check. */ @@ -237,6 +240,109 @@ return ret; } +struct align_region_t +{ + int alignment; + /* start in memory, and size in bytes */ + void* start; + int size; + /* layout within a region: + - num_elements bytes, 0: free, 1: used, 2: used, combines with next + - padding to alignment + - data section + - waste space + + start_data points to the start of the data section + */ + void* start_data; + /* number of free blocks sized "alignment" */ + int free; + struct align_region_t *next; +}; + +static struct align_region_t* align_regions = 0; + +static struct align_region_t *allocate_region(struct align_region_t *old_first, int alignment, int num_elements) +{ + struct align_region_t *new_region = malloc(sizeof(struct align_region_t)); + new_region->alignment = alignment; + new_region->start = malloc((num_elements+1) * alignment + num_elements); + new_region->start_data = (void*)((u32)(new_region->start + num_elements + alignment - 1) & (~(alignment-1))); + new_region->size = num_elements * alignment; + new_region->free = num_elements; + new_region->next = old_first; + memset(new_region->start, 0, num_elements); + return new_region; +} + + +static int free_aligned(void* addr) +{ + struct align_region_t *reg = align_regions; + while (reg != 0) + { + if ((addr >= reg->start_data) && (addr < reg->start_data + reg->size)) + { + int i = (reg->start_data-addr)/reg->alignment; + while (((u8*)reg->start)[i]==2) + { + ((u8*)reg->start)[i++]=0; + reg->free++; + } + ((u8*)reg->start)[i]=0; + reg->free++; + return 1; + } + reg = reg->next; + } + return 0; +} + +void *memalign(size_t align, size_t size) +{ + if (align_regions == 0) { + align_regions = malloc(sizeof(struct align_region_t)); + memset(align_regions, 0, sizeof(struct align_region_t)); + } + struct align_region_t *reg = align_regions; +look_further: + while (reg != 0) + { + if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align)) + { + break; + } + reg = reg->next; + } + if (reg == 0) + { + align_regions = allocate_region(align_regions, align, (size/align<99)?100:((size/align)+1)); + reg = align_regions; + } + int i = 0, count, target = (size+align-1)/align; + for (count = 0; i < (reg->size/align); i++) + { + if (((u8*)reg->start)[i] == 0) + { + count++; + if (count == target) { + count = i+1-count; + for (i=0; i<target-1; i++) + { + ((u8*)reg->start)[count+i]=2; + } + ((u8*)reg->start)[target]=1; + reg->free -= target; + return reg->start_data+(align*count); + } + } else + { + count = 0; + } + } + goto look_further; // end condition is once a new region is allocated - it always has enough space +} + /* This is for debugging purposes. */ #ifdef TEST void print_malloc_map(void)

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r3527 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 19 Aug '08

19 Aug '08

Author: stepan Date: 2008-08-19 21:18:58 +0200 (Tue, 19 Aug 2008) New Revision: 3527 Modified: trunk/payloads/libpayload/libc/memory.c Log: trivial fix for memcpy return code in case someone uses it. Thanks to Ulf Jordan for figuring this out! Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/libc/memory.c =================================================================== --- trunk/payloads/libpayload/libc/memory.c 2008-08-19 17:59:34 UTC (rev 3526) +++ trunk/payloads/libpayload/libc/memory.c 2008-08-19 19:18:58 UTC (rev 3527) @@ -46,6 +46,7 @@ void *memcpy(void *dst, const void *src, size_t n) { int i; + void *ret = dst; for(i = 0; i < n % sizeof(unsigned long); i++) ((unsigned char *) dst)[i] = ((unsigned char *) src)[i]; @@ -57,7 +58,7 @@ for(i = 0; i < n / sizeof(unsigned long); i++) ((unsigned long *) dst)[i] = ((unsigned long *) src)[i]; - return dst; + return ret; } void *memmove(void *dst, const void *src, size_t n)

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coreboot August 2008