coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

r798 - in coreboot-v3: . arch/x86 util/xcompile
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: hailfinger Date: 2008-08-22 03:22:21 +0200 (Fri, 22 Aug 2008) New Revision: 798 Modified: coreboot-v3/Makefile coreboot-v3/arch/x86/Makefile coreboot-v3/util/xcompile/xcompile Log: Add objdump and readelf to xcompile and use the results. This kills a few hardcodes introduced with my checker. Tested on Linux and OSX. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/Makefile =================================================================== --- coreboot-v3/Makefile 2008-08-22 01:19:25 UTC (rev 797) +++ coreboot-v3/Makefile 2008-08-22 01:22:21 UTC (rev 798) @@ -96,6 +96,8 @@ LD := $(LD_$(ARCH)) NM := $(NM_$(ARCH)) OBJCOPY := $(OBJCOPY_$(ARCH)) +OBJDUMP := $(OBJDUMP_$(ARCH)) +READELF := $(READELF_$(ARCH)) AR := $(AR_$(ARCH)) CFLAGS += $(CFLAGS_$(ARCH)) Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-08-22 01:19:25 UTC (rev 797) +++ coreboot-v3/arch/x86/Makefile 2008-08-22 01:22:21 UTC (rev 798) @@ -145,7 +145,7 @@ $(Q)# .data and .bss must be empty because they aren't handled $(Q)printf " CHECK stage0 (non-empty writable/allocatable sections)\n" - $(Q)./util/sectionchecker/sectionchecker objdump readelf $(STAGE0_OBJ) + $(Q)./util/sectionchecker/sectionchecker $(OBJDUMP) $(READELF) $(STAGE0_OBJ) $(Q)# Note: we invoke gcc (instead of ld directly) here, as we hit $(Q)# strange problems in the past. It seems that only gcc knows how @@ -271,7 +271,7 @@ $(Q)# .data and .bss must be empty because they aren't handled $(Q)printf " CHECK initram (non-empty writable/allocatable sections)\n" - $(Q)./util/sectionchecker/sectionchecker objdump readelf $(obj)/coreboot.initram_partiallylinked.o + $(Q)./util/sectionchecker/sectionchecker $(OBJDUMP) $(READELF) $(obj)/coreboot.initram_partiallylinked.o $(Q)printf " WRAP $(subst $(shell pwd)/,,$(@)) (PIC->non-PIC)\n" $(Q)$(NM) --undefined-only $(obj)/coreboot.initram_partiallylinked.o |\ Modified: coreboot-v3/util/xcompile/xcompile =================================================================== --- coreboot-v3/util/xcompile/xcompile 2008-08-22 01:19:25 UTC (rev 797) +++ coreboot-v3/util/xcompile/xcompile 2008-08-22 01:22:21 UTC (rev 798) @@ -63,6 +63,8 @@ searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld) -b elf32-i386 -melf_i386" searchgnu nm >/dev/null && echo "NM_x86 := $(searchgnu nm)" searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" + searchgnu objdump >/dev/null && echo "OBJDUMP_x86 := $(searchgnu objdump)" + searchgnu readelf >/dev/null && echo "READELF_x86 := $(searchgnu readelf)" ;; "x86") if [ "$OS" != "Darwin" ]; then @@ -74,6 +76,8 @@ searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld)" searchgnu nm >/dev/null && echo "NM_x86 := $(searchgnu nm)" searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" + searchgnu objdump >/dev/null && echo "OBJDUMP_x86 := $(searchgnu objdump)" + searchgnu readelf >/dev/null && echo "READELF_x86 := $(searchgnu readelf)" else CC=`find /opt/local/bin/ -name "i386-elf-gcc-*"` if [ "$CC" == "" ]; then @@ -86,6 +90,8 @@ echo "LD_x86 := i386-elf-ld" echo "NM_x86 := i386-elf-nm" echo "OBJCOPY_x86 := i386-elf-objcopy" + echo "OBJDUMP_x86 := i386-elf-objdump" + echo "READELF_x86 := i386-elf-readelf" echo "INTLCFLAGS := -I/opt/local/include" echo "INTLLIBS := -L/opt/local/lib -lintl" fi @@ -99,6 +105,8 @@ echo "LD_x86 := i386-linux-ld" echo "NM_x86 := i386-linux-nm" echo "OBJCOPY_x86 := i386-linux-objcopy" + echo "OBJDUMP_x86 := i386-linux-objdump" + echo "READELF_x86 := i386-elf-readelf" ;; esac

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r797 - coreboot-v3/northbridge/intel/i440bxemulation
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: hailfinger Date: 2008-08-22 03:19:25 +0200 (Fri, 22 Aug 2008) New Revision: 797 Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c Log: Look for statictree.h in the standard search path. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-22 00:34:28 UTC (rev 796) +++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-22 01:19:25 UTC (rev 797) @@ -44,7 +44,7 @@ #include <device/pci.h> #include <string.h> #include "i440bx.h" -#include "statictree.h" +#include <statictree.h> /* Here are the ops for 440BX as a PCI domain. */

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r796 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: hailfinger Date: 2008-08-22 02:34:28 +0200 (Fri, 22 Aug 2008) New Revision: 796 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c Log: CS5536 UART: better depbug prints. This is the part of the acked patch which was to become r649 but missed in the check in. I'm reusing the signoff and ack. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-21 19:38:32 UTC (rev 795) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-22 00:34:28 UTC (rev 796) @@ -360,23 +360,26 @@ msr = rdmsr(MDD_LEG_IO); msr.lo |= addr << 20; wrmsr(MDD_LEG_IO, msr); + printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address); /* Set the IRQ. */ msr = rdmsr(MDD_IRQM_YHIGH); msr.lo |= sb->com2_irq << 28; wrmsr(MDD_IRQM_YHIGH, msr); + printk(BIOS_SPEW, "uarts_init: set COM2 irq\n"); /* GPIO3 - UART2_RX */ /* Set: Output Enable (0x4) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); - + printk(BIOS_SPEW, "uarts_init: set output enable\n"); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); + printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n"); /* GPIO4 - UART2_TX */ /* Set: Input Enable (0x20) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE); - + printk(BIOS_SPEW, "uarts_init: set COM2 input enable\n"); /* Set: INAUX1 Select (0x34) */ /* this totally disables com2 for serial, leave it out until we can * figure it out @@ -384,9 +387,10 @@ // outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX2_SELECT); // printk(BIOS_SPEW, "uarts_init: set INAUX2 for COM2\n"); - /* Set: GPIO 3 + 3 Pull Up (0x18) */ + /* Set: GPIO 3 + 4 Pull Up (0x18) */ outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); + printk(BIOS_SPEW, "uarts_init: set pullup COM2\n"); /* Enable COM2. * @@ -664,6 +668,7 @@ lpc_init(sb); uarts_init(sb, dev); + printk(BIOS_SPEW, "cs5536: done uarts_init\n"); if (sb->enable_gpio_int_route) { printk(BIOS_SPEW, "cs5536: call vr_write\n"); vr_write((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,

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r795 - coreboot-v3/util/sectionchecker
by svn＠coreboot.org 21 Aug '08

21 Aug '08

Author: hailfinger Date: 2008-08-21 21:38:32 +0200 (Thu, 21 Aug 2008) New Revision: 795 Modified: coreboot-v3/util/sectionchecker/sectionchecker Log: Make the section checker executable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Property changes on: coreboot-v3/util/sectionchecker/sectionchecker ___________________________________________________________________ Added: svn:executable + *

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[coreboot] Subject=%5Bcoreboot%5D%20Geode%20GX%20/%20CS5535%20/%20PIC&In-Reply-To=200802290
by pancho martines 21 Aug '08

21 Aug '08

Martin Trautmann: If you still need the schematics on the PIC geode GX/CS5535 you are welcome to have them just send me a mail Thank's Pancho

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Intel G31/33 Chipsets compatibility
by Faizan Azeez 21 Aug '08

21 Aug '08

I have Gigabyte GA-G31M-S2L and a Gigabyte GA-G33M-S2L motherboards with the Intel G31/33 chipsets. Could someone plz tell me if coreboot is compatible with these chipsets. There is no information about this on the Gigabyte website. Thanks. Faizan Unlimited freedom, unlimited storage. Get it now, on http://help.yahoo.com/l/in/yahoo/mail/yahoomail/tools/tools-08.html/

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[PATCH] v3: section correctness checker
by Carl-Daniel Hailfinger 21 Aug '08

21 Aug '08

v3 does not handle .data and .bss sections in stage1 and initram. We simply hope they are unused/empty and will get runtime crashes/corruption/malfunction if they are not empty. Check for the emptiness of these sections and abort the build on error. This triggers on all stage1/initram global variables which are not declared the right way. This found a long-standing bug introduced in r729 and fixed in r576. It also breaks the build of every Geode target in the v3 tree because they have multiple bugs. And it breaks the build of the K8 code because of a bug there. Tested for all possible variations of .data and .bss usage. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-check_illegal_global_vars/arch/x86/Makefile =================================================================== --- corebootv3-check_illegal_global_vars/arch/x86/Makefile (revision 789) +++ corebootv3-check_illegal_global_vars/arch/x86/Makefile (working copy) @@ -143,9 +143,22 @@ $(Q)# 0x4000 - 0x100, we will end up with a 4 gig file. $(Q)# I wonder if that behavior is on purpose. + $(Q)# .data and .bss must be empty because they aren't handled + $(Q)printf " CHECK stage0 (non-empty .data sections)\n" + $(Q)objdump -h $(STAGE0_OBJ)| grep "^$(obj)/\|\.data"|\ + grep -v "\.data[[:blank:]]\+00000000[[:blank:]]"|\ + grep -B1 "\.data"| grep "^$(obj)/"|\ + cut -f 1 -d:| grep "^$(obj)/"; test $$? -ne 0 + $(Q)printf " CHECK stage0 (non-empty .bss sections)\n" + $(Q)objdump -h $(STAGE0_OBJ)| grep "^$(obj)/\|\.bss"|\ + grep -v "\.bss[[:blank:]]\+00000000[[:blank:]]"|\ + grep -B1 "\.bss"| grep "^$(obj)/"|\ + cut -f 1 -d:| grep "^$(obj)/"; test $$? -ne 0 + $(Q)# Note: we invoke gcc (instead of ld directly) here, as we hit $(Q)# strange problems in the past. It seems that only gcc knows how $(Q)# to properly invoke ld. + $(Q)#printf "STAGE0_OBJ is $(STAGE0_OBJ)\n" $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) -nostdlib -static -T $(src)/arch/x86/ldscript.ld \ $(STAGE0_OBJ) -o $(obj)/stage0.o @@ -264,6 +277,19 @@ $(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC) $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" $(Q)$(CC) $(INITCFLAGS) -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o + + $(Q)# .data and .bss must be empty because they aren't handled + $(Q)printf " CHECK initram (non-empty .data sections)\n" + $(Q)objdump -h $(obj)/coreboot.initram_partiallylinked.o|\ + grep "\.data"|\ + grep -vq "\.data[[:blank:]]\+00000000[[:blank:]]";\ + test $$? -ne 0 + $(Q)printf " CHECK initram (non-empty .bss sections)\n" + $(Q)objdump -h $(obj)/coreboot.initram_partiallylinked.o|\ + grep "\.bss"|\ + grep -vq "\.bss[[:blank:]]\+00000000[[:blank:]]";\ + test $$? -ne 0 + $(Q)printf " WRAP $(subst $(shell pwd)/,,$(@)) (PIC->non-PIC)\n" $(Q)$(NM) --undefined-only $(obj)/coreboot.initram_partiallylinked.o |\ grep -v _GLOBAL_OFFSET_TABLE_ | grep " U " | sed "s/^ *U //" |\ -- http://www.hailfinger.org/

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r794 - in coreboot-v3/util: . sectionchecker
by svn＠coreboot.org 21 Aug '08

21 Aug '08

Author: hailfinger Date: 2008-08-21 19:43:04 +0200 (Thu, 21 Aug 2008) New Revision: 794 Added: coreboot-v3/util/sectionchecker/ coreboot-v3/util/sectionchecker/sectionchecker Log: v3 does not handle .data* and .bss sections in stage1 and initram. We simply hope they are unused/empty and will get runtime crashes/ corruption/malfunction if they are not empty. Same applies to any sections with relocation entries which can not be resolved during link time. Check for the emptiness of these sections and abort the build on error. This triggers on all stage1/initram global variables which are not declared the right way. It also triggers on local static variables. Features of this checker: - It doesn't only check for non-empty .data and .bss, but also for unknown sections which would be a problem. - It gives you the offending filename, the section and the variable name. - It won't stop after the first error and will tell you about all errors for a given file list. This found a long-standing bug introduced in r729 and fixed in r786. It also broke the build of every Geode target in the v3 tree because they had multiple bugs. And it broke the build of the K8 code because of a bug there. Other fixes resulting from this checker are in r790 and r791. Ron already fixed some of the bugs uncovered by this checker. Tested for all possible variations of .data and .bss usage. Sample output follows: CC build/coreboot.initram (XIP) CHECK initram (non-empty writable/allocatable sections) build/coreboot.initram_partiallylinked.o: section .data: foo1 build/coreboot.initram_partiallylinked.o: section .bss: foo2 build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local: msrnames.2746 make: *** [build/coreboot.initram] Error 1 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Segher Boessenkool <segher(a)kernel.crashing.org> Added: coreboot-v3/util/sectionchecker/sectionchecker =================================================================== --- coreboot-v3/util/sectionchecker/sectionchecker (rev 0) +++ coreboot-v3/util/sectionchecker/sectionchecker 2008-08-21 17:43:04 UTC (rev 794) @@ -0,0 +1,58 @@ +#!/bin/bash +# +# This file is part of the coreboot project. +# +# Copyright (C) 2008 Carl-Daniel Hailfinger +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# +# This program checks whether a given list of files ($3+) has any writable +# and allocatable non-empty sections. If so, the name of the file, the name of +# the section and the symbols in that section are printed and an error is +# returned. +# +# This is extremely useful for stage1 and initram correctness because +# the .data* and .bss sections are silently dropped. All accesses there +# would wreak havoc (silent discard of writes or silent corruption of +# unspecified memory or cache). +# +# The string parsing used here heavily depends on the textual form of +# GNU objdump output and on the instruction architecture of the files. + +LANG=C +OBJDUMP=$1 +READELF=$2 +shift 2 +for a in $*; do + # Look for sections which have WRITE and ALLOC flags set. + $READELF -St $a| + grep -B2 "WRITE.*ALLOC"| + grep -B1 "^ \+[[:alnum:]]\+ \+[0-9a-f]\+ \+[0-9a-f]\+ \+0*[1-9a-f]"| + grep "^ \+\[ *[0-9]\+"| + cut -f 2 -d"]"| + sed "s/^[[:blank:]]*//"| + while read b; do + echo -n "$a: section $b: " + $OBJDUMP -t --section=$b $a| + grep -i "^[0-9a-f]\{8\}"| + grep -v "00000000 [^ ]\+$"| + sed "s/.* //"| + xargs echo + done +done| + grep "" + +# Invert the result +test $? -ne 0

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r793 - coreboot-v3/northbridge/amd/geodelx
by svn＠coreboot.org 21 Aug '08

21 Aug '08

Author: hailfinger Date: 2008-08-21 19:34:06 +0200 (Thu, 21 Aug 2008) New Revision: 793 Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c Log: Move GeodeLX register name array to .rodata and make my checker happy. This one is far from obvious, so let me explain: Basically, *msrnames[] is an array of pointers (strings) and pointers need relocation. That's why they end up in .data.rel.ro.local and make lots of trouble. This should fix the crash Ron was seeing when register name printing was enabled. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-08-21 16:04:41 UTC (rev 792) +++ coreboot-v3/northbridge/amd/geodelx/raminit.c 2008-08-21 17:34:06 UTC (rev 793) @@ -35,7 +35,29 @@ u8 spd_read_byte(u16 device, u8 address); +const static unsigned long msrs[] = { + MC_CF07_DATA, + MC_CF8F_DATA, + MC_CF1017_DATA, + GLCP_DELAY_CONTROLS, + MC_CFCLK_DBUG, + MC_CF_PMCTR, + GLCP_SYS_RSTPLL +}; +/* If you ever change any of the strings below, make sure the char array size + * is the length of the longest string +1 + */ +const static char msrnames[][20] = { + "MC_CF07_DATA", + "MC_CF8F_DATA", + "MC_CF1017_DATA", + "GLCP_DELAY_CONTROLS", + "MC_CFCLK_DBUG", + "MC_CF_PMCTR", + "PLL reg" +}; + /** * Dump key MSR values for RAM init. You can call this function and then use it to * compare to a factory BIOS setting. @@ -43,24 +65,6 @@ */ void dumplxmsrs(void) { - const static unsigned long msrs[] = { - MC_CF07_DATA, - MC_CF8F_DATA, - MC_CF1017_DATA, - GLCP_DELAY_CONTROLS, - MC_CFCLK_DBUG, - MC_CF_PMCTR, - GLCP_SYS_RSTPLL - }; - const static const char *msrnames[] = { - "MC_CF07_DATA", - "MC_CF8F_DATA", - "MC_CF1017_DATA", - "GLCP_DELAY_CONTROLS", - "MC_CFCLK_DBUG", - "MC_CF_PMCTR", - "PLL reg" - }; int i; for (i = 0; i < ARRAY_SIZE(msrs); i++) {

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ERROR: payload (111864) + coreboot (65536)
by mohammed ag 21 Aug '08

21 Aug '08

coreboot-v2-3532 payload memtest or filo ERROR: payload (111864) + coreboot (65536) - Size is 46328 bytes larger than ROM size (131072). make[1]: *** [coreboot.rom] Error 1 make[1]: Leaving directory `/root/coreboot-v2-3532/targets/a-trend/atc-6240/atc-6240/normal' make: *** [normal/coreboot.rom] Error 1 what i can do ? thanks. = Drop Ship from Hong Kong Over 1,000 ebay members joined, average net profits are $950 monthly. http://a8-asy.a8ww.net/a8-ads/adftrclick?redirectid=b456880680c072bcd26d675… -- Powered by Outblaze

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coreboot August 2008