coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

r3533 - trunk/payloads/libpayload/include
by svn＠coreboot.org 23 Aug '08

23 Aug '08

Author: stepan Date: 2008-08-23 14:17:46 +0200 (Sat, 23 Aug 2008) New Revision: 3533 Modified: trunk/payloads/libpayload/include/libpayload.h Log: A missing semicolon prevents libpayload to compile, this patch fixes that. Signed-off-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-08-20 20:31:41 UTC (rev 3532) +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-23 12:17:46 UTC (rev 3533) @@ -303,6 +303,6 @@ /* libc/readline.c */ char * readline(const char * prompt); -int getline(char *buffer, int len) +int getline(char *buffer, int len); #endif

1 0

coreboot contributors
by Carl-Daniel Hailfinger 23 Aug '08

23 Aug '08

Hi, the wiki page about contributors is woefully out of date: http://www.coreboot.org/Contributors I'm trying to clarify the status of various people on-list before I edit the wiki. How do we handle non-code contributions (hardware donations, booth help etc.)? Developers * Ron Minnich <http://public.lanl.gov/rminnich/index.html>, PI at LANL * Eric Biederman (inactive) * James Hendricks (inactive) * Ollie Lho (inactive) * Jason Potnick (inactive) * Tyson Sawyer (inactive) * Eric Seppanen (inactive) * Dale Webster (inactive) * David Woodhouse (inactive) * Denis Dowling (inactive) * Ronnie Liu (inactive) * Yinghai Lu (?) * Stefan Reinauer <http://www.coresystems.de/> * Greg Watson (?) * Richard Smith (inactive) * Mathieu Deschamps (inactive) * Uwe Hermann And special thanks to .. * OpenBIOS <http://www.openbios.org/>, Stefan Reinauer, et al. * FreeBIOS, Johan Rydberg, Jeff Garzik * Acer: Ronnie Liu, Robert CL Lin, Johnson Hsieh, Emily Jiang * Debian Commercial Japan <http://debian.co.jp/> * Electronics for Imaging <http://www.efi.com/>: Manpreet Singh * SiS <http://www.sis.com.tw>: Ollie Lho, K.M. Liu, et al. (developers of the SiS966 port missing) * VIA: Charlie Chen, Cindy Lee, Mike Fen, Jack Liaw, et al. (who else?) * cwlinux <http://www.cwlinux.com>: Andrew Ip et. al. * Adam Agnew * Bari Ari (maybe list as developer?) * Sung-Eun Choi * Niklas Ekstrom * David Hendricks * Erik Hendriks * Andrey Mirtchovski * Levi Khatskevitch * Dean Risinger * Suravee Suthikulpanit * Konstantin Zhidkov Missing from the list are: - AMD (Marc Jones, Jordan Crouse) - Arne Georg Gleditsch (for LXR and Tyan Fam10h) - Artec Group (Mart Raudsepp, Martin-Eric Racine) - Carl-Daniel Hailfinger - Corey Osgood - Ed Swierk (list him under Arastra?) - Harald Gutmann(?) - Jonathan A. Kollasch - Joseph Smith - Jürgen Beisert - Kevin O'Connor (or does he get his own credit section for SeaBIOS?) - Myles Watson - Patrick Georgi (or does he belong to the OpenBIOS section?) - Peter Stuge - /Reinder/ E.N. de Haan (did I get the name right?) - Ronald Hoogenboom - Rudolf Marek - Segher Boessenkool(?) - Tom Sylla (still active?) - Torsten Duwe - Ward Vandewege I'm sure I missed a few people and maybe some people on the list are not really developers. Comments welcome! Regards, Carl-Daniel

5 14

Via EPIA-MII and linuxbios
by bari 23 Aug '08

23 Aug '08

I'll pass this along to the list. Maybe someone will help you. > Greg Chandler wrote: >> I was working on this board to get the Linuxbios going so I can use the >> PCMCIA bridge/CF working for boot, but have run into some snags with the >> document you wrote: >> http://www.coreboot.org/VIA_Epia-M%2C_MII_Build_Tutorial >> >> Here's a list of what I have found, and I'm wondering if you can help >> set me straight? >> >> {Note I am a fairly advanced hardware guy, have EEPROM programer in case >> I mess up, etc...} >> >> 1) {not a big deal} >> The doc claims that there are 2 firmware chips, yet on inspection of the >> board there is only one. It is 256k and the flashrom util {once built} >> does read and verify it. >> >> What the other chip is, I have no idea, since neither the util nor I can >> actually find it. >> >> 2) {also not a big deal} >> Filo config section doesn't have a list of the options, or caveats >> upfront about the cs_ide stuff. There is a section later, but having to >> go back and rebuild is annoying. Also listing USB_DISK=1 as an option >> would be helpfull since that is a supported method, and some of the >> users may be doing that to jumpstart the first board of many ;) >> >> 3) {big problem} >> The build when downloading the latest corev2 snapshot doesn't work. >> The Makefile is also no longer the same. >> >> The example listed, no longer exists for pre-pending the video bios, >> I've figured out what it should be now, but the tutorial is out of date. >> The code also has hard paths coded to ~/svn/payload.elf >> in both the "fallbackMakefile" and "normal/Makefile" files. >> >> I'm not the expert I used to be, but that's pretty retarded for an >> assumption of where the files are going to be at build time... >> >> >

2 1

[PATCH] RFC: autocreate Kconfig from DTS
by Carl-Daniel Hailfinger 23 Aug '08

23 Aug '08

This is a RFC only to show what we could do. Basically, the DTS is now the only source of hardware description and a converter creates Kconfig variables from each mainboard DTS. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-Kconfig_from_dts/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/Kconfig (Arbeitskopie) @@ -62,39 +62,16 @@ endmenu +# Source all northbridge/southbridge/superio Kconfig files: + source mainboard/Kconfig source arch/x86/Kconfig source lib/Kconfig source device/Kconfig # These are used for internal purposes only: +source build/Kconfig -# Northbridges: -config NORTHBRIDGE_AMD_GEODELX - boolean -config NORTHBRIDGE_AMD_K8 - boolean -config NORTHBRIDGE_INTEL_I440BXEMULATION - boolean - -# Southbridges: -config SOUTHBRIDGE_AMD_CS5536 - boolean -config SOUTHBRIDGE_INTEL_I82371EB - boolean -config SOUTHBRIDGE_NVIDIA_MCP55 - boolean - -# Super I/Os: -config SUPERIO_WINBOND_W83627HF - boolean -config SUPERIO_FINTEK_F71805F - boolean -config SUPERIO_ITE_IT8716F - boolean - -# Source all northbridge/southbridge/superio Kconfig files: - menu "Payload" config PAYLOAD_ELF_LOADER Index: corebootv3-Kconfig_from_dts/mainboard/adl/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/mainboard/adl/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/mainboard/adl/Kconfig (Arbeitskopie) @@ -28,9 +28,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 - select SUPERIO_WINBOND_W83627HF help Advanced Digital Logic MSM800SEV mainboard. Index: corebootv3-Kconfig_from_dts/mainboard/amd/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/mainboard/amd/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/mainboard/amd/Kconfig (Arbeitskopie) @@ -28,9 +28,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 - select SUPERIO_WINBOND_W83627HF select PIRQ_TABLE help AMD DB800 Geode LX development board. @@ -40,8 +37,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 select PIRQ_TABLE help AMD Norwich Geode LX development board. @@ -51,7 +46,6 @@ select ARCH_X86 select OPTION_TABLE select CPU_AMD_K8 - select NORTHBRIDGE_AMD_K8 select IOAPIC help AMD Serengeti Index: corebootv3-Kconfig_from_dts/mainboard/artecgroup/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/mainboard/artecgroup/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/mainboard/artecgroup/Kconfig (Arbeitskopie) @@ -28,8 +28,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 select PIRQ_TABLE help Artec Group DBE61 ThinCan, also known as Linutop 1. @@ -39,8 +37,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 select PIRQ_TABLE help Artec Group DBE62 ThinCan. Index: corebootv3-Kconfig_from_dts/mainboard/pcengines/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/mainboard/pcengines/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/mainboard/pcengines/Kconfig (Arbeitskopie) @@ -28,9 +28,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 - select SUPERIO_WINBOND_W83627HF select PIRQ_TABLE help PC Engines ALIX1.C. @@ -40,8 +37,6 @@ select ARCH_X86 select CPU_AMD_GEODELX select OPTION_TABLE - select NORTHBRIDGE_AMD_GEODELX - select SOUTHBRIDGE_AMD_CS5536 select PIRQ_TABLE help PC Engines ALIX.2C3. Index: corebootv3-Kconfig_from_dts/mainboard/gigabyte/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/mainboard/gigabyte/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/mainboard/gigabyte/Kconfig (Arbeitskopie) @@ -28,9 +28,6 @@ select ARCH_X86 select OPTION_TABLE select CPU_AMD_K8 - select NORTHBRIDGE_AMD_K8 - select SOUTHBRIDGE_NVIDIA_MCP55 - select SUPERIO_ITE_IT8716F select IOAPIC help Gigabyte M57SLI Index: corebootv3-Kconfig_from_dts/mainboard/emulation/Kconfig =================================================================== --- corebootv3-Kconfig_from_dts/mainboard/emulation/Kconfig (Revision 794) +++ corebootv3-Kconfig_from_dts/mainboard/emulation/Kconfig (Arbeitskopie) @@ -29,9 +29,6 @@ select ARCH_X86 select CPU_I586 select OPTION_TABLE - select NORTHBRIDGE_INTEL_I440BXEMULATION - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83627HF help x86 QEMU variant. Index: corebootv3-Kconfig_from_dts/create_Kconfig_from_dts =================================================================== --- corebootv3-Kconfig_from_dts/create_Kconfig_from_dts (Revision 0) +++ corebootv3-Kconfig_from_dts/create_Kconfig_from_dts (Revision 0) @@ -0,0 +1,28 @@ +#!/bin/bash +for a in mainboard/*/*/; do + c=`echo $a|tr [[:lower:]]/- [[:upper:]]__|sed "s/^MAIN//;s/_$//"` + grep /config/ $a/dts| + cut -f 2 -d'"'| + sed 's_/[^/]*$__'| + tr [[:lower:]]/ [[:upper:]]_| + sort -u| + while read b; do + echo $b $c + done + done| + sort| + while read d e; do + if [[ x$d != x$oldd ]]; then + echo -n " + +config $d + bool + default y + depends " + else + echo -n " || " + fi + echo -n $e + oldd=$d + done >$* +echo >>$* Property changes: corebootv3-Kconfig_from_dts/create_Kconfig_from_dts ___________________________________________________________________ Name: svn:executable + * Index: corebootv3-Kconfig_from_dts/Makefile =================================================================== --- corebootv3-Kconfig_from_dts/Makefile (Revision 794) +++ corebootv3-Kconfig_from_dts/Makefile (Arbeitskopie) @@ -130,6 +130,8 @@ prepare: $(Q)mkdir -p $(obj) + $(Q)printf "waaah\n" + $(Q)./create_Kconfig_from_dts $(obj)/Kconfig # FIXME: If .config changed, a rebuild is required. -- http://www.hailfinger.org/

3 10

r806 - coreboot-v3/arch/x86/amd
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: hailfinger Date: 2008-08-22 21:42:45 +0200 (Fri, 22 Aug 2008) New Revision: 806 Modified: coreboot-v3/arch/x86/amd/stage0.S Log: Improve comments in Fam10h CAR. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/amd/stage0.S =================================================================== --- coreboot-v3/arch/x86/amd/stage0.S 2008-08-22 18:24:53 UTC (rev 805) +++ coreboot-v3/arch/x86/amd/stage0.S 2008-08-22 19:42:45 UTC (rev 806) @@ -180,10 +180,10 @@ /* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */ /* Only BSP needed, for other nodes set during HT/memory init. */ - /* So we need to check if it is BSP */ - movl $0x1b, %ecx + /* So we need to check if it is BSP/BSC */ + movl $0x1b, %ecx /* APIC Base Address Register */ rdmsr - bt $8, %eax /*BSC */ + bt $8, %eax /* BSC Boot Strap CPU Core */ jnc CAR_FAM10_out /* Enable RT tables on BSP */ @@ -341,10 +341,10 @@ #ifdef CONFIG_CPU_AMD_K10 - /* So we need to check if it is BSP */ - movl $0x1b, %ecx + /* So we need to check if it is BSP/BSC */ + movl $0x1b, %ecx /* APIC BAR */ rdmsr - bt $8, %eax /*BSC */ + bt $8, %eax /* BSC */ jnc CAR_FAM10_ap #endif

1 0

[PATCH] v3: use ARRAY_SIZE everywhere
by Carl-Daniel Hailfinger 22 Aug '08

22 Aug '08

The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-array_size/southbridge/amd/cs5536/cs5536.c =================================================================== --- corebootv3-array_size/southbridge/amd/cs5536/cs5536.c (Revision 803) +++ corebootv3-array_size/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -417,7 +417,6 @@ } } -/* the /sizeof(u32) is to convert byte offsets into u32 offsets */ #define HCCPARAMS 0x08 #define IPREG04 0xA0 #define USB_HCCPW_SET (1 << 1) Index: corebootv3-array_size/southbridge/amd/amd8111/lpc.c =================================================================== --- corebootv3-array_size/southbridge/amd/amd8111/lpc.c (Revision 803) +++ corebootv3-array_size/southbridge/amd/amd8111/lpc.c (Arbeitskopie) @@ -94,7 +94,7 @@ ioapicregvalues[0].value_high = bsp_apicid<<(56-32); printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: corebootv3-array_size/southbridge/nvidia/mcp55/lpc.c =================================================================== --- corebootv3-array_size/southbridge/nvidia/mcp55/lpc.c (Revision 803) +++ corebootv3-array_size/southbridge/nvidia/mcp55/lpc.c (Arbeitskopie) @@ -109,7 +109,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Index: corebootv3-array_size/southbridge/nvidia/mcp55/stage1.c =================================================================== --- corebootv3-array_size/southbridge/nvidia/mcp55/stage1.c (Revision 803) +++ corebootv3-array_size/southbridge/nvidia/mcp55/stage1.c (Arbeitskopie) @@ -117,7 +117,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_x_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0); } } @@ -133,7 +133,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_x_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0); } @@ -326,23 +326,23 @@ for(j=0; j<mcp55_num; j++) { mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); - setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), + setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); for(i=0; i<3; i++) { // three SATA - setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), + setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1), PCI_BDF(busn[j], devn[j], i), io_base[j], 0); } if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]), + setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); } if( (busn[j] == 0) && (mcp55_num>1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), + setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); } - setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), + setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); } Index: corebootv3-array_size/northbridge/amd/k8/coherent_ht.c =================================================================== --- corebootv3-array_size/northbridge/amd/k8/coherent_ht.c (Revision 803) +++ corebootv3-array_size/northbridge/amd/k8/coherent_ht.c (Arbeitskopie) @@ -511,7 +511,7 @@ printk(BIOS_SPEW, "setup_remote_node: "); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u8 reg; reg = pci_reg[i]; @@ -803,7 +803,7 @@ }; #endif - setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0])); + setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1)); setup_temp_row(0,2); verify_connection(7); @@ -894,7 +894,7 @@ 3,0,1,1, }; #endif - setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0])); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); /* ready to enable RT for Node 3 */ rename_temp_node(3); @@ -910,7 +910,7 @@ 2,1,0,1, }; #endif - setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0])); + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); #if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -975,7 +975,7 @@ #endif }; - setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0])); + setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); @@ -999,7 +999,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0])); + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); rename_temp_node(4); enable_routing(4); @@ -1085,7 +1085,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0])); + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3)); /* ready to enable RT for 5 */ rename_temp_node(5); @@ -1111,7 +1111,7 @@ #endif }; - setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0])); + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); #if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) @@ -1203,7 +1203,7 @@ #endif }; - setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0])); + setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); for(byte=0; byte<6; byte+=2) { setup_temp_row(byte,byte+2); @@ -1226,7 +1226,7 @@ #endif }; - setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0])); + setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2)); #if CONFIG_CROSS_BAR_47_56 //init 5, 6 here @@ -1415,7 +1415,7 @@ #endif }; - setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0])); + setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3)); #if CONFIG_CROSS_BAR_47_56 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to @@ -1456,7 +1456,7 @@ 7, 3, 6, }; - opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0])); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); static const u8 conn8_5[] = { 2, 7, 0, @@ -1464,7 +1464,7 @@ 3, 6, 1, }; - opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0])); + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif @@ -1717,7 +1717,7 @@ 1,3, 2,3, }; - needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0])); + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); } #endif @@ -1730,7 +1730,7 @@ 4, 5, #endif }; - needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0])); + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); } #endif @@ -1745,7 +1745,7 @@ 5, 7, 6, 7, }; - needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0])); + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); } #endif Index: corebootv3-array_size/northbridge/amd/k8/raminit.c =================================================================== --- corebootv3-array_size/northbridge/amd/k8/raminit.c (Revision 803) +++ corebootv3-array_size/northbridge/amd/k8/raminit.c (Arbeitskopie) @@ -1399,7 +1399,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for(j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); -- http://www.hailfinger.org/

2 2

r805 - in coreboot-v3: northbridge/amd/k8 southbridge/amd/amd8111 southbridge/amd/cs5536 southbridge/nvidia/mcp55
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: hailfinger Date: 2008-08-22 20:24:53 +0200 (Fri, 22 Aug 2008) New Revision: 805 Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/raminit.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/nvidia/mcp55/lpc.c coreboot-v3/southbridge/nvidia/mcp55/stage1.c Log: The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-22 18:24:53 UTC (rev 805) @@ -511,7 +511,7 @@ printk(BIOS_SPEW, "setup_remote_node: "); /* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u8 reg; reg = pci_reg[i]; @@ -803,7 +803,7 @@ }; #endif - setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0])); + setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1)); setup_temp_row(0,2); verify_connection(7); @@ -894,7 +894,7 @@ 3,0,1,1, }; #endif - setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0])); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3)); /* ready to enable RT for Node 3 */ rename_temp_node(3); @@ -910,7 +910,7 @@ 2,1,0,1, }; #endif - setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0])); + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2)); #if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -975,7 +975,7 @@ #endif }; - setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0])); + setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); @@ -999,7 +999,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0])); + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); rename_temp_node(4); enable_routing(4); @@ -1085,7 +1085,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0])); + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3)); /* ready to enable RT for 5 */ rename_temp_node(5); @@ -1111,7 +1111,7 @@ #endif }; - setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0])); + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4)); #if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) @@ -1203,7 +1203,7 @@ #endif }; - setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0])); + setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1)); for(byte=0; byte<6; byte+=2) { setup_temp_row(byte,byte+2); @@ -1226,7 +1226,7 @@ #endif }; - setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0])); + setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2)); #if CONFIG_CROSS_BAR_47_56 //init 5, 6 here @@ -1415,7 +1415,7 @@ #endif }; - setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0])); + setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3)); #if CONFIG_CROSS_BAR_47_56 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to @@ -1456,7 +1456,7 @@ 7, 3, 6, }; - opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0])); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4)); static const u8 conn8_5[] = { 2, 7, 0, @@ -1464,7 +1464,7 @@ 3, 6, 1, }; - opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0])); + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif @@ -1717,7 +1717,7 @@ 1,3, 2,3, }; - needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0])); + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); } #endif @@ -1730,7 +1730,7 @@ 4, 5, #endif }; - needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0])); + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); } #endif @@ -1745,7 +1745,7 @@ 5, 7, 6, 7, }; - needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0])); + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); } #endif Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 18:24:53 UTC (rev 805) @@ -1402,7 +1402,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for(j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr); Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-22 18:24:53 UTC (rev 805) @@ -94,7 +94,7 @@ ioapicregvalues[0].value_high = bsp_apicid<<(56-32); printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-22 18:24:53 UTC (rev 805) @@ -417,7 +417,6 @@ } } -/* the /sizeof(u32) is to convert byte offsets into u32 offsets */ #define HCCPARAMS 0x08 #define IPREG04 0xA0 #define USB_HCCPW_SET (1 << 1) Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-22 18:24:53 UTC (rev 805) @@ -109,7 +109,7 @@ l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-22 18:24:53 UTC (rev 805) @@ -117,7 +117,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_x_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0); } } @@ -133,7 +133,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_x_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0); } @@ -326,23 +326,23 @@ for(j=0; j<mcp55_num; j++) { mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); - setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), + setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); for(i=0; i<3; i++) { // three SATA - setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), + setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1), PCI_BDF(busn[j], devn[j], i), io_base[j], 0); } if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]), + setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); } if( (busn[j] == 0) && (mcp55_num>1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), + setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); } - setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), + setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); }

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Re: [coreboot] ERROR: payload (111864) + coreboot (65536)
by mohammed ag 22 Aug '08

22 Aug '08

> ----- Original Message ----- > From: "Myles Watson" <mylesgw(a)gmail.com> > To: "'mohammed ag'" <mohammed_ag(a)linuxmail.org>, coreboot(a)coreboot.org > Subject: RE: [coreboot] ERROR: payload (111864) + coreboot (65536) > Date: Thu, 21 Aug 2008 10:47:14 -0600 > > > > > > -----Original Message----- > > From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] > > On Behalf Of mohammed ag > > Sent: Thursday, August 21, 2008 9:25 AM > > To: coreboot(a)coreboot.org > > Subject: [coreboot] ERROR: payload (111864) + coreboot (65536) > > > > coreboot-v2-3532 > > payload memtest or filo > > a-trend/atc-6240 motherboard > > > > ERROR: payload (111864) + coreboot (65536) - Size is 46328 bytes larger > > than ROM size (131072). > > make[1]: *** [coreboot.rom] Error 1 > > make[1]: Leaving directory `/root/coreboot-v2-3532/targets/a-trend/atc- > > 6240/atc-6240/normal' > > make: *** [normal/coreboot.rom] Error 1 > > > > what i can do ? > > More information (vendor, board, Config.lb) would be helpful to really help, > but here are some options: > > 1. Enable compression with the payload. > 2. Use fallback only - no normal image > 3. Play with the various sizes until they all fit in your ROM > 4. Get a larger ROM. > > If your platform is supported by buildrom, check out how it handles these > options. > > Thanks, > Myles > > > > > thanks. > > > > > > = > > Drop Ship from Hong Kong > > Over 1,000 ebay members joined, average net profits are $950 monthly. > > http://a8-asy.a8ww.net/a8- > > ads/adftrclick?redirectid=b456880680c072bcd26d67576dfa9ee8 > > > > > > -- > > Powered by Outblaze > > > > -- > > coreboot mailing list > > coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > hi, thanks for your reply i used fallback only and it is working and booting now . but qemu show some errors this is my qemu output: qemu -cpu pentium3 -no-kqemu -hda /dev/hda -serial stdio -nographic coreboot-2.0.0.0Fallback Fri Aug 22 02:58:55 EEST 2008 starting... SMBus controller enabled Ram1.00 Northbridge prior to SDRAM init: PCI: 00:00.00 00: 86 80 37 12 00 00 00 00 02 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Set register 0x50 to 0x0c Set register 0x51 to 0x80 Set register 0x52 to 0x00 Set register 0x53 to 0xff Set register 0x57 to 0x08 Set register 0x59 to 0x00 Set register 0x5a to 0x00 Set register 0x5b to 0x00 Set register 0x5c to 0x00 Set register 0x5d to 0x00 Set register 0x5e to 0x00 Set register 0x5f to 0x00 Set register 0x60 to 0x00 Set register 0x61 to 0x00 Set register 0x62 to 0x00 Set register 0x63 to 0x00 Set register 0x64 to 0x00 Set register 0x65 to 0x00 Set register 0x66 to 0x00 Set register 0x67 to 0x00 Set register 0x68 to 0x00 Set register 0x74 to 0x00 Set register 0x75 to 0x00 Set register 0x76 to 0x00 Set register 0x76 to 0x00 Set register 0x78 to 0x00 Set register 0x79 to 0xff Set register 0x7a to 0x00 Ram2.00 Ram3 RAM Enable 1: Apply NOP Sending RAM command 0x0023 to 0x00000000 RAM Enable 2: Precharge all Sending RAM command 0x0043 to 0x00000000 RAM Enable 3: CBR Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 Sending RAM command 0x0083 to 0x00000000 RAM Enable 4: Mode register set Sending RAM command 0x0063 to 0x000001d0 RAM Enable 5: Normal operation Sending RAM command 0x0003 to 0x00000000 RAM Enable 6: Enable refresh Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 37 12 00 00 00 00 02 00 00 06 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 0c 80 00 ff 00 00 00 08 03 30 33 33 33 33 33 33 60: 08 08 08 08 08 08 08 08 00 03 00 00 00 00 00 00 70: 00 00 02 00 01 00 03 00 23 01 10 38 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Ram4 Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0.0Fallback Fri Aug 22 05:44:47 EEST 2008 booting... end 96521a41, start 0 32-bit delta 118 calibrate_tsc 32-bit result is 118 clocks_per_usec: 118 Enumerating buses... scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] enabled malloc Enter, size 1100, free_mem_ptr 00026000 malloc 0x00026000 PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: devfn 0xa, bad id 0xffffffff malloc Enter, size 1100, free_mem_ptr 0002644c malloc 0x0002644c PCI: 00:01.3 [8086/7113] bus ops PCI: 00:01.3 [8086/7113] enabled PCI: devfn 0xc, bad id 0xffffffff PCI: devfn 0xd, bad id 0xffffffff PCI: devfn 0xe, bad id 0xffffffff PCI: devfn 0xf, bad id 0xffffffff malloc Enter, size 1100, free_mem_ptr 00026898 malloc 0x00026898 PCI: 00:02.0 [1013/00b8] enabled malloc Enter, size 1100, free_mem_ptr 00026ce4 malloc 0x00026ce4 PCI: 00:03.0 [10ec/8029] enabled PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Disabling static device: PCI: 00:07.0 Disabling static device: PCI: 00:07.1 Disabling static device: PCI: 00:07.2 Disabling static device: PCI: 00:07.3 PCI: devfn 0x3c, bad id 0xffffffff PCI: devfn 0x3d, bad id 0xffffffff PCI: devfn 0x3e, bad id 0xffffffff PCI: devfn 0x3f, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Disabling static device: PCI: 00:0c.0 PCI: devfn 0x61, bad id 0xffffffff PCI: devfn 0x62, bad id 0xffffffff PCI: devfn 0x63, bad id 0xffffffff PCI: devfn 0x64, bad id 0xffffffff PCI: devfn 0x65, bad id 0xffffffff PCI: devfn 0x66, bad id 0xffffffff PCI: devfn 0x67, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_resource io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:03.0 10 * [0x00000400 - 0x000004ff] io PCI: 00:01.1 20 * [0x00000800 - 0x0000080f] io Root Device compute_allocate_resource io: base: 00000810 size: 00000410 align: 8 gran: 0 done Root Device compute_allocate_resource mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:02.0 10 * [0x00000000 - 0x01ffffff] prefmem PCI: 00:02.0 14 * [0x02000000 - 0x02000fff] mem Root Device compute_allocate_resource mem: base: 02001000 size: 02001000 align: 25 gran: 0 done Done reading resources. Allocating VGA resource PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... Root Device compute_allocate_resource io: base: 00001000 size: 00000410 align: 8 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:03.0 10 * [0x00001000 - 0x000010ff] io PCI: 00:01.1 20 * [0x00001400 - 0x0000140f] io Root Device compute_allocate_resource io: base: 00001410 size: 00000410 align: 8 gran: 0 done Root Device compute_allocate_resource mem: base: fc000000 size: 02001000 align: 25 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem PCI: 00:02.0 14 * [0xfe000000 - 0xfe000fff] mem Root Device compute_allocate_resource mem: base: fe001000 size: 02001000 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 64 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe000000 - 0x00fe000fff] size 0x00001000 gran 0x0c mem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 00/00 PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 subsystem <- 00/00 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 01 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 01 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init malloc Enter, size 1100, free_mem_ptr 00027130 malloc 0x00027130 Initializing CPU #0 CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Disabled Variable MTRRs: Disabled microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000 Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init PCI: 00:01.0 init PCI: 00:01.1 init IDE: Primary IDE interface: off IDE: Secondary IDE interface: off PCI: 00:02.0 init PCI: 00:03.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000724 checksum 3025 elfboot: Attempting to load payload. rom_stream: 0xfffe0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 0002757c malloc 0x0002757c New segment addr 0x100000 size 0x355e0 offset 0xc0 filesize 0xc148 (cleaned up) New segment addr 0x100000 size 0x355e0 offset 0xc0 filesize 0xc148 lb: [0x0000000000004000, 0x000000000002a000) malloc Enter, size 32, free_mem_ptr 0002759c malloc 0x0002759c New segment addr 0x1355e0 size 0x48 offset 0xc220 filesize 0x48 (cleaned up) New segment addr 0x1355e0 size 0x48 offset 0xc220 filesize 0x48 lb: [0x0000000000004000, 0x000000000002a000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000355e0 filesz: 0x000000000000c148 [ 0x0000000000100000, 000000000010c148, 0x00000000001355e0) <- 00000000000000c0 Clearing Segment: addr: 0x000000000010c148 memsz: 0x0000000000029498 Loading Segment: addr: 0x00000000001355e0 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x00000000001355e0, 0000000000135628, 0x0000000000135628) <- 000000000000c220 Loaded segments verified segments closed down stream Jumping to boot code at 0x10007c entry = 0x0010007c lb_start = 0x00004000 lb_size = 0x00026000 adjust = 0x03fd6000 buffer = 0x03fb4000 elf_boot_notes = 0x000204a0 adjusted_boot_notes = 0x03ff64a0 FILO version 0.5.6 (root@shadow) Fri Aug 22 05:29:01 EEST 2008 Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 IDE time out reset failed, but slave maybe exist hda: LBA48 20GB: QEMU HARDDISK Mounted EXT2 filesystem Mounted EXT2 filesystem Found Linux version 2.6.21.5-smp (root@midas) #2 SMP Tue Jun 19 14:58:11 CDT 2007 bzImage. Loading kernel... ok Jumping to entry point... Linux version 2.6.21.5-smp (root@midas) (gcc version 4.1.2) #2 SMP Tue Jun 19 14:58:11 CDT 2007 BIOS-provided physical RAM map: sanitize start sanitize end copy_e820_map() start: 0000000000001000 size: 000000000009f000 end: 00000000000a0000 type: 1 copy_e820_map() type is E820_RAM copy_e820_map() start: 00000000000c0000 size: 0000000000030000 end: 00000000000f0000 type: 1 copy_e820_map() type is E820_RAM copy_e820_map() lies in range... copy_e820_map() end <= 0x100000ULL copy_e820_map() start: 0000000000100000 size: 0000000003f00000 end: 0000000004000000 type: 1 copy_e820_map() type is E820_RAM BIOS-e820: 0000000000001000 - 00000000000a0000 (usable) BIOS-e820: 0000000000100000 - 0000000004000000 (usable) 0MB HIGHMEM available. 64MB LOWMEM available. Zone PFN ranges: DMA 0 -> 4096 Normal 4096 -> 16384 HighMem 16384 -> 16384 early_node_map[1] active PFN ranges 0: 0 -> 16384 DMI not present or invalid. Allocating PCI resources starting at 10000000 (gap: 04000000:fc000000) Built 1 zonelists. Total pages: 16256 Kernel command line: root=/dev/hda2 console=tty0 console=ttyS0,115200 Local APIC disabled by BIOS -- you can enable it with "lapic" Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 PID hash table entries: 256 (order: 8, 1024 bytes) Detected 611.171 MHz processor. Console: colour dummy device 80x25 Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 55260k/65536k available (6215k kernel code, 9868k reserved, 2017k data, 392k init, 0k highmem) virtual kernel memory layout: fixmap : 0xffe17000 - 0xfffff000 (1952 kB) pkmap : 0xff800000 - 0xffc00000 (4096 kB) vmalloc : 0xc4800000 - 0xff7fe000 ( 943 MB) lowmem : 0xc0000000 - 0xc4000000 ( 64 MB) .init : 0xc0915000 - 0xc0977000 ( 392 kB) .data : 0xc0711c79 - 0xc090a38c (2017 kB) .text : 0xc0100000 - 0xc0711c79 (6215 kB) Checking if this processor honours the WP bit even in supervisor mode... Ok. Calibrating delay using timer specific routine.. 1146.70 BogoMIPS (lpj=2293416) Security Framework v1.0.0 initialized Mount-cache hash table entries: 512 CPU: L1 I cache: 32K, L1 D cache: 32K CPU: L2 cache: 2048K Intel machine check architecture supported. Intel machine check reporting enabled on CPU#0. Compat vDSO mapped to ffffe000. Checking 'hlt' instruction... OK. SMP alternatives: switching to UP code Freeing SMP alternatives: 24k freed ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126] ACPI: Unable to load the System Description Tables CPU0: Intel Pentium III (Katmai) stepping 03 SMP motherboard not detected. Local APIC not detected. Using dummy APIC emulation. Brought up 1 CPUs NET: Registered protocol family 16 PCI: Using configuration type 1 Setting up standard PCI resources ACPI: Interpreter disabled. Linux Plug and Play Support v0.97 (c) Adam Belay pnp: PnP ACPI: disabled SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb PCI: Probing PCI hardware * Found PM-Timer Bug on the chipset. Due to workarounds for a bug, * this clock source is slow. Consider trying other clock sources PCI quirk: region 0f00-0f0f claimed by PIIX4 SMB Time: tsc clocksource has been installed. PCI: Ignore bogus resource 6 [0:0] of 0000:00:02.0 NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 2048 (order: 2, 24576 bytes) TCP bind hash table entries: 2048 (order: 2, 16384 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP reno registered apm: BIOS not found. VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) NTFS driver 2.1.28 [Flags: R/W]. JFS: nTxBlock = 432, nTxLock = 3456 SGI XFS with ACLs, security attributes, large block numbers, no debug enabled SGI XFS Quota Management subsystem OCFS2 1.3.3 OCFS2 Node Manager 1.3.3 OCFS2 DLM 1.3.3 OCFS2 DLMFS 1.3.3 OCFS2 User DLM kernel interface loaded GFS2 (built Jun 19 2007 14:57:33) installed io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) Limiting direct PCI/PCI transfers. PCI: PIIX3: Enabling Passive Release on 0000:00:01.0 Activating ISA DMA hang workarounds. pci_hotplug: PCI Hot Plug PCI Core version: 0.5 isapnp: Scanning for PnP cards... isapnp: No Plug & Play device found Clocksource tsc unstable (delta = 207175200 ns) Time: pit clocksource has been installed. Real Time Clock Driver v1.12ac Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled �serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16450 FDC 0 is a S82078B RAMDISK driver initialized: 16 RAM disks of 16384K size 1024 blocksize loop: loaded (max 8 devices) Compaq SMART2 Driver (v 2.6.0) HP CISS Driver (v 3.6.14) input: Macintosh mouse button emulation as /class/input/input0 Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx PIIX3: IDE controller at PCI slot 0000:00:01.1 PIIX3: chipset revision 0 PIIX3: not 100% native mode: will probe irqs later PIIX3: neither IDE port enabled (BIOS) hda: QEMU HARDDISK, ATA DISK drive hdc: QEMU CD-ROM, ATAPI CD/DVD-ROM drive ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 ide1 at 0x170-0x177,0x376 on irq 15 hda: max request size: 512KiB hda: 39102336 sectors (20020 MB) w/256KiB Cache, CHS=16383/255/63 hda: cache flushes supported hda: hda1 hda2 hda3 hda4 hda4: <solaris: [s0] hda5 [s1] hda6 [s2] hda7 > hdc: ATAPI 4X CD-ROM drive, 512kB Cache Uniform CD-ROM driver Revision: 3.20 ide-floppy driver 0.99.newide Loading iSCSI transport class v2.0-724. iscsi: registered transport (tcp) Loading Adaptec I2O RAID: Version 2.4 Build 5go Detecting Adaptec I2O RAID controllers... Adaptec aacraid driver (1.1-5[2423]-mh3) aic94xx: Adaptec aic94xx SAS/SATA driver version 1.0.3 loaded scsi: <fdomain> Detection failed (no card) sym53c416.c: Version 1.0.0-ac qlogicfas: no cards were found, please specify I/O address and IRQ using iobase= and irq= options<6>QLogic Fibre Channel HBA Driver iscsi: registered transport (qla4xxx) QLogic iSCSI HBA Driver Emulex LightPulse Fibre Channel SCSI driver 8.1.11 Copyright(c) 2004-2006 Emulex. All rights reserved. seagate: ST0x/TMC-8xx not detected. Failed initialization of WD-7000 SCSI card! DC390: clustering now enabled by default. If you get problems load with "disable_clustering=1" and report to maintainers megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006) megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006) megasas: 00.00.03.10-rc1 Wed Feb 14 10:14:25 PST 2007 GDT-HA: Storage RAID Controller Driver. Version: 3.05 GDT-HA: Found 0 PCI Storage RAID Controllers 3ware Storage Controller device driver for Linux v1.26.02.002. 3ware 9000 Storage Controller device driver for Linux v2.26.02.008. nsp32: loading... ipr: IBM Power RAID SCSI Device Driver version: 2.3.1 (January 23, 2007) RocketRAID 3xxx SATA Controller driver v1.0 (060426) st: Version 20070203, fixed bufsize 32768, s/g segs 256 I2O subsystem v1.325 i2o: max drivers = 8 I2O Configuration OSM v1.323 I2O Bus Adapter OSM v1.317 I2O Block Device OSM v1.325 I2O SCSI Peripheral OSM v1.316 I2O ProcFS OSM v1.316 Fusion MPT base driver 3.04.04 Copyright (c) 1999-2007 LSI Logic Corporation Fusion MPT SPI Host driver 3.04.04 Fusion MPT FC Host driver 3.04.04 Fusion MPT SAS Host driver 3.04.04 usbmon: debugfs is not available 116x: driver isp116x-hcd, 03 Nov 2005 USB Universal Host Controller Interface driver v3.0 sl811: driver sl811-hcd, 19 May 2005 Initializing USB Mass Storage driver... usbcore: registered new interface driver usb-storage USB Mass Storage support registered. usbcore: registered new interface driver hiddev usbcore: registered new interface driver usbhid drivers/usb/input/hid-core.c: v2.6:USB HID core driver PNP: No PS/2 controller found. Probing ports directly. serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mice: PS/2 mouse device common for all mice md: linear personality registered for level -1 md: raid0 personality registered for level 0 md: raid1 personality registered for level 1 md: raid10 personality registered for level 10 raid6: int32x1 17 MB/s raid6: int32x2 16 MB/s raid6: int32x4 12 MB/s raid6: int32x8 6 MB/s raid6: mmxx1 21 MB/s raid6: mmxx2 24 MB/s raid6: sse1x1 21 MB/s raid6: sse1x2 26 MB/s raid6: using algorithm sse1x2 (26 MB/s) md: raid6 personality registered for level 6 md: raid5 personality registered for level 5 md: raid4 personality registered for level 4 raid5: automatically using best checksumming function: pIII_sse pIII_sse : 58.000 MB/sec raid5: using function: pIII_sse (58.000 MB/sec) md: multipath personality registered for level -4 device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel(a)redhat.com TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 Using IPI Shortcut mode input: AT Raw Set 2 keyboard as /class/input/input1 md: Autodetecting RAID arrays. md: autorun ... md: ... autorun DONE. kjournald starting. Commit interval 5 seconds EXT3-fs warning: mounting fs with errors, running e2fsck is recommended EXT3 FS on hda2, internal journal EXT3-fs: recovery complete. EXT3-fs: mounted filesystem with ordered data mode. VFS: Mounted root (ext3 filesystem). Freeing unused kernel memory: 392k freed INIT: version 2.86 booting [1;32m ##########[1;34m Going To Boot System...[1;32m ########## [0;39m INIT: Entering runlevel: 3 [1;32m ##########[1;34m We now in multiuser mode[0;31m : default mode[1;32m ########## [0;39m = -- Powered by Outblaze

2 1

r804 - in coreboot-v3: mainboard/amd/serengeti northbridge/amd/k8
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: rminnich Date: 2008-08-22 18:48:44 +0200 (Fri, 22 Aug 2008) New Revision: 804 Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h coreboot-v3/northbridge/amd/k8/common.c coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/raminit.c Log: This is getting to the link phase. Still won't build as we don't have dqs timing file compiled in yet. Per discussion with YingHai Lu, we are only going to support F2 and later CPUs. This will simplify more code. I realize this code needs work, but it is in v2, and cleanup will get easier once we have the baseline. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h =================================================================== --- coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-22 16:48:44 UTC (rev 804) @@ -22,3 +22,4 @@ */ #define CPU_SOCKET_TYPE SOCKET_AM2 +#define MEM_TRAIN_SEQ 1 /* for now */ Modified: coreboot-v3/northbridge/amd/k8/common.c =================================================================== --- coreboot-v3/northbridge/amd/k8/common.c 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/northbridge/amd/k8/common.c 2008-08-22 16:48:44 UTC (rev 804) @@ -121,7 +121,7 @@ int node_id; }; -static struct hw_mem_hole_info get_hw_mem_hole_info(void) +struct hw_mem_hole_info get_hw_mem_hole_info(void) { struct hw_mem_hole_info mem_hole; int i; @@ -172,7 +172,8 @@ return mem_hole; } -static void disable_hoist_memory(unsigned long hole_startk, int i) + +void disable_hoist_memory(unsigned long hole_startk, int i) { int ii; struct device * dev; Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-22 16:48:44 UTC (rev 804) @@ -166,6 +166,8 @@ static void k8_pci_domain_set_resources(struct device * dev) { + struct hw_mem_hole_info get_hw_mem_hole_info(void); + void disable_hoist_memory(unsigned long hole_startk, int i); #if CONFIG_PCI_64BIT_PREF_MEM == 1 struct resource *io, *mem1, *mem2; struct resource *resource, *last; @@ -325,7 +327,7 @@ } - printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08lx, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 11:33:19 UTC (rev 803) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 16:48:44 UTC (rev 804) @@ -27,6 +27,7 @@ */ #include <console.h> +#include <string.h> #include <mtrr.h> #include <macros.h> #include <spd.h> @@ -44,7 +45,9 @@ #warning where to we define supported DIMM types #define DIMM_SUPPORT 0x0104 -#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 1 + +/* we won't support the buggy old chips */ +#undef K8_REV_F_SUPPORT_F0_F1_WORKAROUND inline void print_raminit(const char *strval, u32 val) { printk(BIOS_DEBUG, "%s%08x\n", strval, val); @@ -866,7 +869,7 @@ #if CPU_SOCKET_TYPE == SOCKET_L1 ClkDis0 = DTL_MemClkDis0; #else - #if CPU_SOCKET_TYPE SOCKET_AM2 + #if CPU_SOCKET_TYPE == SOCKET_AM2 ClkDis0 = DTL_MemClkDis0_AM2; #endif #endif @@ -1595,7 +1598,7 @@ value = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; - read_option(&max_mem_clock, "max_mem_clock"); + get_option(&max_mem_clock, "max_mem_clock"); bios_cycle_time = min_cycle_times[max_mem_clock]; if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; @@ -2379,15 +2382,15 @@ #endif /* Program the Output Driver Compensation Control Registers (Function 2:Offset 0x9c, index 0, 0x20) */ - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 0, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, 0, dword); if(meminfo->is_Width128) { - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword); + pci_write_config32_index_wait(ctrl->f2, 0x98, 0x20, dword); } /* Program the Address Timing Control Registers (Function 2:Offset 0x9c, index 4, 0x24) */ - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx); + pci_write_config32_index_wait(ctrl->f2, 0x98, 4, dwordx); if(meminfo->is_Width128) { - pci_conf1_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx); + pci_write_config32_index_wait(ctrl->f2, 0x98, 0x24, dwordx); } } @@ -2519,6 +2522,8 @@ struct mem_param paramx; struct mem_info *meminfo; long dimm_mask; + void activate_spd_rom(const struct mem_controller *ctrl); + void hard_reset(void); #if 1 if (!sysinfo->ctrl_present[ctrl->node_id]) { return; @@ -2526,7 +2531,7 @@ #endif meminfo = &sysinfo->meminfo[ctrl->node_id]; - print_debug_addr("sdram_set_spd_registers: paramx :", &paramx); + printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :0x%x\n", paramx); activate_spd_rom(ctrl); dimm_mask = spd_detect_dimms(ctrl); @@ -2684,9 +2689,9 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; - - -#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + void dqs_timing(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); + void memreset(int controllers, const struct mem_controller *ctrl); +#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND unsigned cpu_f0_f1[8]; /* FIXME: How about 32 node machine later? */ tsc_t tsc, tsc0[8]; @@ -2755,7 +2760,7 @@ pci_conf1_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); } -#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 +#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i); if(cpu_f0_f1[i]) { //Rev F0/F1 workaround @@ -2808,7 +2813,7 @@ dcm = pci_conf1_read_config32(ctrl[i].f2, DRAM_CTRL_MISC); } while(((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ ); -#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 +#ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND if(cpu_f0_f1[i]) { tsc= rdtsc(); @@ -2863,7 +2868,7 @@ #if MEM_TRAIN_SEQ == 0 - #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 + #ifdef dqs_timing(controllers, ctrl, tsc0, sysinfo); #else dqs_timing(controllers, ctrl, sysinfo); @@ -2880,7 +2885,7 @@ if(sysinfo->mem_trained[i]!=0x80) continue; - dqs_timing(i, &ctrl[i], sysinfo, 1); + dqs_timing(i, &ctrl[i], sysinfo); #if MEM_TRAIN_SEQ == 1 break; // only train the first node with ram

1 0

r803 - coreboot-v3/arch/x86/geodelx
by svn＠coreboot.org 22 Aug '08

22 Aug '08

Author: hailfinger Date: 2008-08-22 13:33:19 +0200 (Fri, 22 Aug 2008) New Revision: 803 Modified: coreboot-v3/arch/x86/geodelx/geodelx.c Log: Typo: word duplication. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/geodelx/geodelx.c =================================================================== --- coreboot-v3/arch/x86/geodelx/geodelx.c 2008-08-22 11:29:30 UTC (rev 802) +++ coreboot-v3/arch/x86/geodelx/geodelx.c 2008-08-22 11:33:19 UTC (rev 803) @@ -76,7 +76,7 @@ * Bugtool #465 and #609 PCI cache deadlock. * TODO: URL? * - * There is also fix code in cache and PCI functions. This bug is very is + * There is also fix code in cache and PCI functions. This bug is very * pervasive. */ static void pci_deadlock(void)

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coreboot August 2008