r805 - in coreboot-v3: northbridge/amd/k8 southbridge/amd/amd8111 southbridge/amd/cs5536 southbridge/nvidia/mcp55
Author: hailfinger Date: 2008-08-22 20:24:53 +0200 (Fri, 22 Aug 2008) New Revision: 805
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/raminit.c coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/nvidia/mcp55/lpc.c coreboot-v3/southbridge/nvidia/mcp55/stage1.c Log: The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-22 18:24:53 UTC (rev 805) @@ -511,7 +511,7 @@ printk(BIOS_SPEW, "setup_remote_node: ");
/* copy the default resource map from node 0 */ - for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { + for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u8 reg; reg = pci_reg[i]; @@ -803,7 +803,7 @@ }; #endif
- setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0])); + setup_row_indirect_group(conn4_1, ARRAY_SIZE(conn4_1));
setup_temp_row(0,2); verify_connection(7); @@ -894,7 +894,7 @@ 3,0,1,1, }; #endif - setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0])); + setup_remote_row_indirect_group(conn4_3, ARRAY_SIZE(conn4_3));
/* ready to enable RT for Node 3 */ rename_temp_node(3); @@ -910,7 +910,7 @@ 2,1,0,1, }; #endif - setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0])); + setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
#if 0 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */ @@ -975,7 +975,7 @@ #endif };
- setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0])); + setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1)); for(byte=0; byte<4; byte+=2) { setup_temp_row(byte,byte+2); @@ -999,7 +999,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0])); + setup_remote_row_indirect_group(conn6_2, ARRAY_SIZE(conn6_2)); rename_temp_node(4); enable_routing(4); @@ -1085,7 +1085,7 @@ #endif }; - setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0])); + setup_remote_row_indirect_group(conn6_3, ARRAY_SIZE(conn6_3));
/* ready to enable RT for 5 */ rename_temp_node(5); @@ -1111,7 +1111,7 @@ #endif }; - setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0])); + setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
#if 0 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5) @@ -1203,7 +1203,7 @@ #endif };
- setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0])); + setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
for(byte=0; byte<6; byte+=2) { setup_temp_row(byte,byte+2); @@ -1226,7 +1226,7 @@ #endif };
- setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0])); + setup_remote_row_indirect_group(conn8_2, ARRAY_SIZE(conn8_2));
#if CONFIG_CROSS_BAR_47_56 //init 5, 6 here @@ -1415,7 +1415,7 @@ #endif };
- setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0])); + setup_row_indirect_group(conn8_3, ARRAY_SIZE(conn8_3));
#if CONFIG_CROSS_BAR_47_56 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to @@ -1456,7 +1456,7 @@ 7, 3, 6, };
- opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0])); + opt_broadcast_rt_group(conn8_4, ARRAY_SIZE(conn8_4));
static const u8 conn8_5[] = { 2, 7, 0, @@ -1464,7 +1464,7 @@ 3, 6, 1, };
- opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0])); + opt_broadcast_rt_plus_group(conn8_5, ARRAY_SIZE(conn8_5)); #endif
@@ -1717,7 +1717,7 @@ 1,3, 2,3, }; - needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0])); + needs_reset |= optimize_connection_group(opt_conn4, ARRAY_SIZE(opt_conn4)); } #endif
@@ -1730,7 +1730,7 @@ 4, 5, #endif }; - needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0])); + needs_reset |= optimize_connection_group(opt_conn6, ARRAY_SIZE(opt_conn6)); } #endif
@@ -1745,7 +1745,7 @@ 5, 7, 6, 7, }; - needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0])); + needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); } #endif
Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 18:24:53 UTC (rev 805) @@ -1402,7 +1402,7 @@ } device0 = ctrl->channel0[i]; device1 = ctrl->channel1[i]; - for(j = 0; j < sizeof(addresses)/sizeof(addresses[0]); j++) { + for(j = 0; j < ARRAY_SIZE(addresses); j++) { unsigned addr; addr = addresses[j]; value0 = spd_read_byte(device0, addr);
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-22 18:24:53 UTC (rev 805) @@ -94,7 +94,7 @@ ioapicregvalues[0].value_high = bsp_apicid<<(56-32); printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low;
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-22 18:24:53 UTC (rev 805) @@ -417,7 +417,6 @@ } }
-/* the /sizeof(u32) is to convert byte offsets into u32 offsets */ #define HCCPARAMS 0x08 #define IPREG04 0xA0 #define USB_HCCPW_SET (1 << 1)
Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-22 18:24:53 UTC (rev 805) @@ -109,7 +109,7 @@
l = (unsigned long *) ioapic_base;
- for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low;
Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-22 16:48:44 UTC (rev 804) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-22 18:24:53 UTC (rev 805) @@ -117,7 +117,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_x_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0); } } @@ -133,7 +133,7 @@ int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_x_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_BDF(busn[j], devn[j], 0) , io_base[j], 0); }
@@ -326,23 +326,23 @@ for(j=0; j<mcp55_num; j++) { mcp55_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
- setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), + setup_resource_map_x_offset(ctrl_conf_1, ARRAY_SIZE(ctrl_conf_1), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); for(i=0; i<3; i++) { // three SATA - setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), + setup_resource_map_x_offset(ctrl_conf_1_1, ARRAY_SIZE(ctrl_conf_1_1), PCI_BDF(busn[j], devn[j], i), io_base[j], 0); } if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_mcp55_only, sizeof(ctrl_conf_mcp55_only)/sizeof(ctrl_conf_mcp55_only[0]), + setup_resource_map_x_offset(ctrl_conf_mcp55_only, ARRAY_SIZE(ctrl_conf_mcp55_only), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); }
if( (busn[j] == 0) && (mcp55_num>1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), + setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0); }
- setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), + setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), PCI_BDF(busn[j], devn[j], 0), io_base[j], 0);
}
-
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