coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

k8 status
by ron minnich 26 Aug '08

26 Aug '08

coreboot-3.0.811 Sun Aug 24 00:05:58 PDT 2008 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member bootblock LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member bootblock LAR: File not found! LAR: Run file normal/initram/segment0 failed: No such file. Failed RAM init code from simnow. Hey, it's a start. ron

4 19

r3536 build service
by coreboot information 25 Aug '08

25 Aug '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "eswierk" checked in revision 3536 to the coreboot source repository and caused the following changes: Change Log: This patch adds PCI device IDs for the Intel EP80579 Integrated Processor, and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of intel:mtarvon has been fixed If something broke during this checkin please be a pain in eswierk's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3536 - in trunk/coreboot-v2/src: include/device northbridge/intel/i3100 southbridge/intel/i3100
by svn＠coreboot.org 25 Aug '08

25 Aug '08

Author: eswierk Date: 2008-08-25 19:02:09 +0200 (Mon, 25 Aug 2008) New Revision: 3536 Modified: trunk/coreboot-v2/src/include/device/pci_ids.h trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c Log: This patch adds PCI device IDs for the Intel EP80579 Integrated Processor, and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/include/device/pci_ids.h =================================================================== --- trunk/coreboot-v2/src/include/device/pci_ids.h 2008-08-25 14:45:00 UTC (rev 3535) +++ trunk/coreboot-v2/src/include/device/pci_ids.h 2008-08-25 17:02:09 UTC (rev 3536) @@ -2345,15 +2345,26 @@ #define PCI_DEVICE_ID_INTEL_3100_LPC 0x2670 #define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c #define PCI_DEVICE_ID_INTEL_3100_PCI 0x244e -#define PCI_DEVICE_ID_INTEL_3100_SATA 0x2680 -#define PCI_DEVICE_ID_INTEL_3100_SATA_R 0x2681 -#define PCI_DEVICE_ID_INTEL_3100_USB 0x2688 -#define PCI_DEVICE_ID_INTEL_3100_USB2 0x2689 +#define PCI_DEVICE_ID_INTEL_3100_IDE 0x2680 +#define PCI_DEVICE_ID_INTEL_3100_AHCI 0x2681 +#define PCI_DEVICE_ID_INTEL_3100_UHCI 0x2688 +#define PCI_DEVICE_ID_INTEL_3100_UHCI2 0x2689 #define PCI_DEVICE_ID_INTEL_3100_SMB 0x269b #define PCI_DEVICE_ID_INTEL_3100_MC 0x35b0 -#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA 0x35b6 +#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA0 0x35b6 #define PCI_DEVICE_ID_INTEL_3100_PCIE_PA1 0x35b7 +/* Intel EP80579 */ +#define PCI_DEVICE_ID_INTEL_EP80579_LPC 0x5031 +#define PCI_DEVICE_ID_INTEL_EP80579_EHCI 0x5035 +#define PCI_DEVICE_ID_INTEL_EP80579_IDE 0x5028 +#define PCI_DEVICE_ID_INTEL_EP80579_AHCI 0x5029 +#define PCI_DEVICE_ID_INTEL_EP80579_UHCI 0x5033 +#define PCI_DEVICE_ID_INTEL_EP80579_SMB 0x5032 +#define PCI_DEVICE_ID_INTEL_EP80579_MC 0x5020 +#define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0 0x5024 +#define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1 0x5025 + #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 #define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta.c 2008-08-25 14:45:00 UTC (rev 3535) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta.c 2008-08-25 17:02:09 UTC (rev 3536) @@ -78,7 +78,7 @@ static struct pci_driver pci_driver_0 __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA, + .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA0, }; static struct pci_driver pci_driver_1 __pci_driver = { Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-08-25 14:45:00 UTC (rev 3535) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-08-25 17:02:09 UTC (rev 3536) @@ -79,23 +79,23 @@ static struct pci_driver sata_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SATA, + .device = PCI_DEVICE_ID_INTEL_3100_IDE, }; static struct pci_driver sata_driver_nr __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SATA_R, + .device = PCI_DEVICE_ID_INTEL_3100_AHCI, }; static struct pci_driver sata_driver_ep80579 __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_SATA, + .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, }; static struct pci_driver sata_driver_nr_ep80579 __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_SATA_R, + .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, }; Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c 2008-08-25 14:45:00 UTC (rev 3535) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c 2008-08-25 17:02:09 UTC (rev 3536) @@ -52,17 +52,17 @@ static struct pci_driver uhci_driver __pci_driver = { .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_USB, + .device = PCI_DEVICE_ID_INTEL_3100_UHCI, }; static struct pci_driver usb2_driver __pci_driver = { .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_USB2, + .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, }; static struct pci_driver uhci_driver_ep80579 __pci_driver = { .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_USB, + .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, };

1 0

r3535 build service
by coreboot information 25 Aug '08

25 Aug '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "eswierk" checked in revision 3535 to the coreboot source repository and caused the following changes: Change Log: This patch modifies the Intel 3100 southbridge code to recognize the integrated LPC, SMBus, USB and SATA devices of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3535&device=mtarvon&vendor… If something broke during this checkin please be a pain in eswierk's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[PATCH 1/6] Intel EP80579 PCI device IDs
by Ed Swierk 25 Aug '08

25 Aug '08

This patch adds PCI device IDs for the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

2 3

[PATCH 4/6] Intel EP80579 southbridge
by Ed Swierk 25 Aug '08

25 Aug '08

This patch modifies the Intel 3100 southbridge code to recognize the integrated LPC, SMBus, USB and SATA devices of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

2 2

r3535 - trunk/coreboot-v2/src/southbridge/intel/i3100
by svn＠coreboot.org 25 Aug '08

25 Aug '08

Author: eswierk Date: 2008-08-25 16:45:00 +0200 (Mon, 25 Aug 2008) New Revision: 3535 Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_ehci.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_smbus.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c Log: This patch modifies the Intel 3100 southbridge code to recognize the integrated LPC, SMBus, USB and SATA devices of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_ehci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_ehci.c 2008-08-25 14:41:11 UTC (rev 3534) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_ehci.c 2008-08-25 14:45:00 UTC (rev 3535) @@ -60,3 +60,9 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_EHCI, }; + +static struct pci_driver ehci_driver_ep80579 __pci_driver = { + .ops = &ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI, +}; Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2008-08-25 14:41:11 UTC (rev 3534) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2008-08-25 14:45:00 UTC (rev 3535) @@ -399,3 +399,9 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_LPC, }; + +static struct pci_driver lpc_driver_ep80579 __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_LPC, +}; Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-08-25 14:41:11 UTC (rev 3534) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-08-25 14:45:00 UTC (rev 3535) @@ -88,3 +88,14 @@ .device = PCI_DEVICE_ID_INTEL_3100_SATA_R, }; +static struct pci_driver sata_driver_ep80579 __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_SATA, +}; + +static struct pci_driver sata_driver_nr_ep80579 __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_SATA_R, +}; Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_smbus.c 2008-08-25 14:41:11 UTC (rev 3534) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_smbus.c 2008-08-25 14:45:00 UTC (rev 3535) @@ -72,3 +72,8 @@ .device = PCI_DEVICE_ID_INTEL_3100_SMB, }; +static struct pci_driver smbus_driver_ep80579 __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_SMB, +}; Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c 2008-08-25 14:41:11 UTC (rev 3534) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c 2008-08-25 14:45:00 UTC (rev 3535) @@ -60,3 +60,9 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_USB2, }; + +static struct pci_driver uhci_driver_ep80579 __pci_driver = { + .ops = &uhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_USB, +};

1 0

[PATCH 2/6] Intel EP80579 CPU core
by Ed Swierk 25 Aug '08

25 Aug '08

This patch implements support for the CPU core of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

2 2

r3534 - in trunk/coreboot-v2/src/cpu/intel: . ep80579
by svn＠coreboot.org 25 Aug '08

25 Aug '08

Author: eswierk Date: 2008-08-25 16:41:11 +0200 (Mon, 25 Aug 2008) New Revision: 3534 Added: trunk/coreboot-v2/src/cpu/intel/ep80579/ trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c Log: This patch implements support for the CPU core of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Arastra, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 as +## published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object ep80579.o +dir /cpu/x86/tsc +dir /cpu/x86/mtrr +dir /cpu/x86/fpu +dir /cpu/x86/mmx +dir /cpu/x86/sse +dir /cpu/x86/lapic +dir /cpu/x86/cache +dir /cpu/intel/microcode +driver ep80579_init.o Added: trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_ep80579_ops; + +struct cpu_intel_ep80579_config { +}; Added: trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_ep80579_ops = { + CHIP_NAME("EP80579 CPU") +}; Added: trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> + +static u32 microcode_updates[] = { + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static void ep80579_init(device_t dev) +{ + /* Turn on caching if we haven't already */ + x86_enable_cache(); + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Enable the local cpu apics */ + setup_lapic(); +}; + +static struct device_operations cpu_dev_ops = { + .init = ep80579_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */ + { 0, 0 }, +}; + +static struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +};

1 0

r821 - coreboot-v3/arch/x86
by svn＠coreboot.org 25 Aug '08

25 Aug '08

Author: rminnich Date: 2008-08-25 07:11:59 +0200 (Mon, 25 Aug 2008) New Revision: 821 Modified: coreboot-v3/arch/x86/pci_ops_conf1.c Log: Fix a simply bug in the find device function. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/pci_ops_conf1.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_conf1.c 2008-08-24 19:55:45 UTC (rev 820) +++ coreboot-v3/arch/x86/pci_ops_conf1.c 2008-08-25 05:11:59 UTC (rev 821) @@ -119,7 +119,8 @@ u8 hdr; int bdf = bus << 16; - /* skip over all the function sin a device -- multifunction devices always have one vendor */ + /* skip over all the functions in a device -- + * multifunction devices always have one vendor */ for (devfn = 0; devfn < 0x100; devfn += 8) { u32 confaddr = bdf | (devfn << 8); val = pci_conf1_read_config32(confaddr, PCI_VENDOR_ID); @@ -127,7 +128,6 @@ if (val == 0xffffffff || val == 0x00000000 || val == 0x0000ffff || val == 0xffff0000) continue; - if (val == ((did << 16) | vid)) { *busdevfn = confaddr; return 1; @@ -135,10 +135,16 @@ hdr = pci_conf1_read_config8(confaddr, PCI_HEADER_TYPE); hdr &= 0x7F; - if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int busses; busses = pci_conf1_read_config32(confaddr, PCI_PRIMARY_BUS); + /* We should never see a value of 0. + * this can happen if we run this before + * things are set up (which we have to be able to do + * in stage 0 + */ + if (! busses) + continue; if (pci_conf1_find_on_bus((busses >> 8) & 0xFF, vid, did, busdevfn)) return 1; }

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coreboot August 2008