coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

r3538 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 26 Aug '08

26 Aug '08

Author: uwe Date: 2008-08-26 21:37:37 +0200 (Tue, 26 Aug 2008) New Revision: 3538 Modified: trunk/payloads/libpayload/libc/exec.c trunk/payloads/libpayload/libc/lib.c trunk/payloads/libpayload/libc/printf.c Log: Fix some Doxygen warnings and/or typos (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/libc/exec.c =================================================================== --- trunk/payloads/libpayload/libc/exec.c 2008-08-26 11:18:38 UTC (rev 3537) +++ trunk/payloads/libpayload/libc/exec.c 2008-08-26 19:37:37 UTC (rev 3538) @@ -35,10 +35,12 @@ #endif /** - * Execute code in memory + * Execute code in memory. * - * @param ptr The entry point to jump to - * @return Return the return value from the entry point + * @param addr TODO + * @param argc TODO + * @param argv TODO + * @return Return the return value from the entry point. */ int exec(long addr, int argc, char **argv) { Modified: trunk/payloads/libpayload/libc/lib.c =================================================================== --- trunk/payloads/libpayload/libc/lib.c 2008-08-26 11:18:38 UTC (rev 3537) +++ trunk/payloads/libpayload/libc/lib.c 2008-08-26 19:37:37 UTC (rev 3538) @@ -54,7 +54,7 @@ /** * Return the absolute value of the specified integer. * - * @param val The integer of which we want to know the absolute value. + * @param j The integer of which we want to know the absolute value. * @return The absolute value of the specified integer. */ int abs(int j) Modified: trunk/payloads/libpayload/libc/printf.c =================================================================== --- trunk/payloads/libpayload/libc/printf.c 2008-08-26 11:18:38 UTC (rev 3537) +++ trunk/payloads/libpayload/libc/printf.c 2008-08-26 19:37:37 UTC (rev 3538) @@ -135,6 +135,7 @@ * @param c Character to print. * @param width Width modifier. * @param flags Flags that change the way the character is printed. + * @param ps Output methods spec for different printf clones. * @return Number of characters printed, negative value on failure. */ static int print_char(char c, int width, uint64_t flags, struct printf_spec *ps) @@ -166,8 +167,10 @@ * @param width Width modifier. * @param precision Precision modifier. * @param flags Flags that modify the way the string is printed. + * @param ps Output methods spec for different printf clones. * @return Number of characters printed, negative value on failure. */ +/** Structure for specifying output methods for different printf clones. */ static int print_string(char *s, int width, unsigned int precision, uint64_t flags, struct printf_spec *ps) { @@ -207,10 +210,11 @@ * Print significant digits of a number in given base. * * @param num Number to print. - * @param widt Width modifier.h + * @param width Width modifier.h * @param precision Precision modifier. * @param base Base to print the number in (must be between 2 and 16). * @param flags Flags that modify the way the number is printed. + * @param ps Output methods spec for different printf clones. * @return Number of characters printed. */ static int print_number(uint64_t num, int width, int precision, int base, @@ -359,7 +363,8 @@ return counter; } -/** Print formatted string. +/** + * Print formatted string. * * Print string formatted according to the fmt parameter and variadic arguments. * Each formatting directive must have the following form:

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Re: [coreboot] r3536 - in trunk/coreboot-v2/src: include/device northbridge/intel/i3100 southbridge/intel/i3100
by Uwe Hermann 26 Aug '08

26 Aug '08

On Mon, Aug 25, 2008 at 07:02:10PM +0200, svn(a)coreboot.org wrote: > Author: eswierk > Date: 2008-08-25 19:02:09 +0200 (Mon, 25 Aug 2008) > New Revision: 3536 > > Modified: > trunk/coreboot-v2/src/include/device/pci_ids.h > trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta.c > trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c > trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c > Log: > This patch adds PCI device IDs for the Intel EP80579 Integrated Processor, > and renames some existing macros for clarity. > > Signed-off-by: Ed Swierk <eswierk(a)arastra.com> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-08-25 14:45:00 UTC (rev 3535) > +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-08-25 17:02:09 UTC (rev 3536) > @@ -79,23 +79,23 @@ > static struct pci_driver sata_driver __pci_driver = { ^^^^ maybe make this ide_driver then? > .ops = &sata_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_3100_SATA, > + .device = PCI_DEVICE_ID_INTEL_3100_IDE, > }; > > static struct pci_driver sata_driver_nr __pci_driver = { ^^^^ sata or ahci? I guess sata is fine though. > .ops = &sata_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_3100_SATA_R, > + .device = PCI_DEVICE_ID_INTEL_3100_AHCI, > }; > > static struct pci_driver sata_driver_ep80579 __pci_driver = { ^^^^ ide? > .ops = &sata_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_EP80579_SATA, > + .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, > }; > > static struct pci_driver sata_driver_nr_ep80579 __pci_driver = { > .ops = &sata_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_EP80579_SATA_R, > + .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, > }; > > Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c 2008-08-25 14:45:00 UTC (rev 3535) > +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_uhci.c 2008-08-25 17:02:09 UTC (rev 3536) > @@ -52,17 +52,17 @@ > static struct pci_driver uhci_driver __pci_driver = { > .ops = &uhci_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_3100_USB, > + .device = PCI_DEVICE_ID_INTEL_3100_UHCI, > }; > > static struct pci_driver usb2_driver __pci_driver = { ^^^^ uhci2 for consistency? > .ops = &uhci_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_3100_USB2, > + .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, > }; > > static struct pci_driver uhci_driver_ep80579 __pci_driver = { > .ops = &uhci_ops, > .vendor = PCI_VENDOR_ID_INTEL, > - .device = PCI_DEVICE_ID_INTEL_EP80579_USB, > + .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, > }; Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r823 - coreboot-v3/mainboard/amd/serengeti
by svn＠coreboot.org 26 Aug '08

26 Aug '08

Author: rminnich Date: 2008-08-26 20:01:19 +0200 (Tue, 26 Aug 2008) New Revision: 823 Modified: coreboot-v3/mainboard/amd/serengeti/stage1.c Log: Set up resources for the mainboard. but the 8111 ISA device is still not visible in SimNOW Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/amd/serengeti/stage1.c =================================================================== --- coreboot-v3/mainboard/amd/serengeti/stage1.c 2008-08-25 23:54:50 UTC (rev 822) +++ coreboot-v3/mainboard/amd/serengeti/stage1.c 2008-08-26 18:01:19 UTC (rev 823) @@ -32,11 +32,268 @@ #include <io.h> #include <arch/x86/msr.h> + +static const struct rmap register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCM(0, 0x18, 1, 0x44, 0x0000f8f8, 0x00000000), + PCM(0, 0x18, 1, 0x4C, 0x0000f8f8, 0x00000001), + PCM(0, 0x18, 1, 0x54, 0x0000f8f8, 0x00000002), + PCM(0, 0x18, 1, 0x5C, 0x0000f8f8, 0x00000003), + PCM(0, 0x18, 1, 0x64, 0x0000f8f8, 0x00000004), + PCM(0, 0x18, 1, 0x6C, 0x0000f8f8, 0x00000005), + PCM(0, 0x18, 1, 0x74, 0x0000f8f8, 0x00000006), + PCM(0, 0x18, 1, 0x7C, 0x0000f8f8, 0x00000007), + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCM(0, 0x18, 1, 0x40, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x48, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x50, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x58, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x60, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x68, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x70, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x78, 0x0000f8fc, 0x00000000), + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCM(0, 0x18, 1, 0x84, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x8C, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x94, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x9C, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xA4, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xAC, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xB4, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xBC, 0x00000048, 0x00ffff00), + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCM(0, 0x18, 1, 0x80, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x88, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x90, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x98, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA0, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA8, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB0, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB8, 0x000000f0, 0x00fc0003), + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCM(0, 0x18, 1, 0xC4, 0xFE000FC8, 0x01fff000), + PCM(0, 0x18, 1, 0xCC, 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xD4, 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xDC, 0xFE000FC8, 0x00000000), + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCM(0, 0x18, 1, 0xC0, 0xFE000FCC, 0x00000003), + PCM(0, 0x18, 1, 0xC8, 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD0, 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD8, 0xFE000FCC, 0x00000000), + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCM(0, 0x18, 1, 0xE0, 0x0000FC88, 0x06000003), // AMD 8111 on link0 of CPU 0 + PCM(0, 0x18, 1, 0xE4, 0x0000FC88, 0x08070013), // AMD 8151 on link0 of CPU 1 + PCM(0, 0x18, 1, 0xE8, 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xEC, 0x0000FC88, 0x00000000), +}; + void amd8111_enable_rom(void); void hardware_stage1(void) { + int max; printk(BIOS_ERR, "Stage1: enable rom ...\n"); + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); amd8111_enable_rom(); printk(BIOS_ERR, "Done.\n"); post_code(POST_START_OF_MAIN);

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what could cause this?
by ron minnich 26 Aug '08

26 Aug '08

rminnich@lb:~/src/bios/coreboot-v3$ lar l build/bios.bin normal/option_table (1776 bytes @0x50);loadaddress 0x0 entry 0x0 normal/initram/segment0 (24404 bytes @0x790);loadaddress 0x0 entry 0x0x4 normal/stage2/segment0 (195156 bytes, zeroes compressed to 1 bytes @0x6740);loadaddress 0x0xd360 entry 0x0x2000 normal/stage2/segment1 (33781 bytes, lzma compressed to 18404 bytes @0x67a0);loadaddress 0x0x2000 entry 0x0x2000 normal/stage2/segment2 (9036 bytes, lzma compressed to 559 bytes @0xafe0);loadaddress 0x0xb000 entry 0x0x2000 normal/payload/segment0 (30944 bytes, lzma compressed to 18142 bytes @0xb260);loadaddress 0x0x10000 entry 0x0x100b0 bootblock (263635550 bytes @0x6e192) Total size = 263699172 bytes (0xfb7bae4) Note the size of the bootbock ... is this related to global variables in any way? ron

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Re: [coreboot] r820 - in coreboot-v3: mainboard/amd/serengeti southbridge/amd/amd8111
by Carl-Daniel Hailfinger 26 Aug '08

26 Aug '08

On 24.08.2008 21:55, svn(a)coreboot.org wrote: > Author: rminnich > New Revision: 820 > > Grow rom space. This now gets a triple fault but I am hoping some smart > person can fix it. > Could you post a boot log? Depending on when the triple fault happens, I might know the solution. - Directly at AP startup: Easy. The global variables are overwritten by every AP and can lead to NULL pointer derefs. (Does not apply in single-core single-processor environments.) - Same for any point after AP startup. - Before AP startup or on uniprocessor: Either a stack overrun (bad) or CAR corruption (worse). - In theory, jumping to the wrong place could be as damaging. Regards, Carl-Daniel -- http://www.hailfinger.org/

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r3537 - trunk/payloads/libpayload
by svn＠coreboot.org 26 Aug '08

26 Aug '08

Author: stepan Date: 2008-08-26 13:18:38 +0200 (Tue, 26 Aug 2008) New Revision: 3537 Modified: trunk/payloads/libpayload/Makefile Log: How could -ffreestanding slip through here. Required because libpayload is not going to run under an OS. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/Makefile =================================================================== --- trunk/payloads/libpayload/Makefile 2008-08-25 17:02:09 UTC (rev 3536) +++ trunk/payloads/libpayload/Makefile 2008-08-26 11:18:38 UTC (rev 3537) @@ -91,7 +91,7 @@ STACKPROTECT += $(call cc-option, -fno-stack-protector,) # TODO: Re-add -Os as soon as we find out why it caused problems. -CFLAGS := -Wall -Werror $(STACKPROTECT) -nostdinc $(INCLUDES) +CFLAGS := -Wall -Werror $(STACKPROTECT) -nostdinc $(INCLUDES) -ffreestanding all: lib

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Test installation of the review board webapplication
by Patrick Georgi 26 Aug '08

26 Aug '08

Hi there, On IRC, there was a request for a web based patch system. I installed review board (http://www.review-board.org), which is "a powerful web-based code review tool that offers developers an easy way to handle code reviews" (to quote its website), to give it a spin. It's not integrated properly yet, as I want to see if it's usable for us first. However, if we agree to use it, I can migrate the database and keep its data, if it's clean enough after our testing. I didn't enable the full text search, or (more importantly) mail notification yet - these would come at later stages, if review board looks good enough for us. Our installation can be found (for now) at http://www.coreboot.org:9119/, but will be moved to some subdomain once it's official. The work flow in review board is like this: 1. The submitter creates a review request, consisting of a patch with meta data (subject, description) for a project. 2. Other users can see the request, and comment on it (in general, or to parts of the patch) 3. Updated patches can be attached to the review request (and you can see the diff between patches) These two steps repeat until the patch is in a suitable state 4. Someone (not the submitter) hits the "Ship it" button/link, which is the equivalent to our "Acked-By" (though I'll have to look if that keeps the ACKer) 5. The submitter (or someone else) hits the "Set Submitted" button/link to mark the review as done (so it disappears from plain sight) - ideally, after the patch is committed For submitting requests, there's a shell utility, too (http://code.google.com/p/reviewboard/wiki/Using_PostReview) The server is configured so you can create review requests for the following subprojects: coreboot-v2, coreboot-v3, libpayload. Of course, I can add more of our subprojects (right now, I'm the only admin, though this will change). Each of them have access to the respective svn repository, so you can post diffs against svn and it's able to fetch the necessary context. For each of the subprojects, there's a review group that you can subscribe to. This has the effect that you see related review requests in your dashboard (frontpage of the app) and (in later stages) get mail notifications for the projects you're interested in. Comments welcome! Regards, Patrick Georgi

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[RFC][PATCH] v3: kill duplicated function
by Carl-Daniel Hailfinger 26 Aug '08

26 Aug '08

Every GeodeLX target already has spd_read_byte in mainboard/$VENDOR/$BOARD/initram.c. It's pointless to have it in the southbridge code as well. Options: - Kill it in the southbridge code and use mainboard code only. - Make the southbridge one a weak symbol. - Rename the southbridge one and call it from mainboard code. Comments? Regards, Carl-Daniel Index: southbridge/amd/cs5536/smbus_initram.c =================================================================== --- southbridge/amd/cs5536/smbus_initram.c (Revision 821) +++ southbridge/amd/cs5536/smbus_initram.c (Arbeitskopie) @@ -330,20 +330,3 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } - -/** - * Read a byte from the SPD. - * - * For this chip, that is really just saying 'read a byte from SMBus'. - * So we use smbus_read_byte(). Nota Bene: leave this here as a function - * rather than a #define in an obscure location. This function is called - * only a few dozen times, and it's not performance critical. - * - * @param device The device. - * @param address The address. - * @return The data from the SMBus packet area or an error of 0xff (i.e. -1). - */ -u8 spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} -- http://www.hailfinger.org/

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My motherboard is not suported
by Osiris 26 Aug '08

26 Aug '08

Hi, I'm not very good speaking english, I'm mexican, but I like Linux and the Free Software Philosofy. So I want a page in spanish, I don't know how you work, maybe mexican or latins like me, can create a page in spanish,and I send you my motherboard model for if you want to add on the list of motherboard in progress. And I don't know how i can flash and install in my original bios, the coreboot. My motherboard is: PCCHIPS M925 v7.3 Thanks for read, and i want news for you amazing develoment in this BIOS, and hate the price for the upgrate of my bios, $30 dollars i think, and i don't know how flash because i don't understand all the english words and i'm not have $30 for a bios upgrate. Osiris _________________________________________________________________ P.D. Checa las nuevas fotos de mi Space http://home.services.spaces.live.com/

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r822 - coreboot-v3/arch/x86
by svn＠coreboot.org 26 Aug '08

26 Aug '08

Author: hailfinger Date: 2008-08-26 01:54:50 +0200 (Tue, 26 Aug 2008) New Revision: 822 Modified: coreboot-v3/arch/x86/coreboot_table.c Log: mainboard_vendor and mainboard_name are constant. Follow that convention everywhere. This fixes a bug triggered by combined compilation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/coreboot_table.c =================================================================== --- coreboot-v3/arch/x86/coreboot_table.c 2008-08-25 05:11:59 UTC (rev 821) +++ coreboot-v3/arch/x86/coreboot_table.c 2008-08-25 23:54:50 UTC (rev 822) @@ -142,7 +142,7 @@ { struct lb_record *rec; struct lb_mainboard *mainboard; - extern char *mainboard_vendor, *mainboard_name; + extern const char *mainboard_vendor, *mainboard_name; rec = lb_new_record(header); mainboard = (struct lb_mainboard *)rec; mainboard->tag = LB_TAG_MAINBOARD;

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coreboot August 2008