coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

r3516 - trunk/payloads/libpayload/curses
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: jcrouse Date: 2008-08-18 21:28:42 +0200 (Mon, 18 Aug 2008) New Revision: 3516 Modified: trunk/payloads/libpayload/curses/tinycurses.c Log: Fix tinycurses color output on the VGA console. The CGA compatible 16 color VGA text mode expects Intensity RGB color specifications, in the order IRGB from most to least significant bit. Curses COLOR_ macros follows ANSI X3.64/ISO 6429/ECMA-48, specifying RGB color in the order BGR from most to least significant bit. Consequently, it is necessary to swap the red and blue bits. Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/curses/tinycurses.c =================================================================== --- trunk/payloads/libpayload/curses/tinycurses.c 2008-08-18 18:55:33 UTC (rev 3515) +++ trunk/payloads/libpayload/curses/tinycurses.c 2008-08-18 19:28:42 UTC (rev 3516) @@ -658,6 +658,8 @@ return OK; } +#define SWAP_RED_BLUE(c) \ + (((c) & 0x4400) >> 2) | ((c) & 0xAA00) | (((c) & 0x1100) << 2) int wnoutrefresh(WINDOW *win) { // FIXME. @@ -720,6 +722,8 @@ serial_putchar(ch); } + c = SWAP_RED_BLUE(c); + if (curses_flags & F_ENABLE_CONSOLE) { ch = win->_line[y].text[x].chars[0];

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r3515 - trunk/payloads/libpayload
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: uwe Date: 2008-08-18 20:55:33 +0200 (Mon, 18 Aug 2008) New Revision: 3515 Modified: trunk/payloads/libpayload/README Log: Add more information to the libpayload README (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/README =================================================================== --- trunk/payloads/libpayload/README 2008-08-18 10:58:09 UTC (rev 3514) +++ trunk/payloads/libpayload/README 2008-08-18 18:55:33 UTC (rev 3515) @@ -1,7 +1,66 @@ -This is libpayload, a minimal library to support standalone payloads -that can be booted with firmware like coreboot. It handles the setup -code, and provides common C library symbols such as malloc() and -printf(). +------------------------------------------------------------------------------- +libpayload README +------------------------------------------------------------------------------- -Please see the sample/ directory for an example of the payload in -action. +libpayload is a minimal library to support standalone payloads +that can be booted with firmware like coreboot. It handles the setup +code, and provides common C library symbols such as malloc() and printf(). + +Note: This is _not_ a standard library for use with an operating system, +rather it's only useful for coreboot payload development! +See http://coreboot.org for details on coreboot. + + +Installation +------------ + + $ svn co svn://coreboot.org/repos/trunk/payloads/libpayload + + $ cd libpayload + + $ make menuconfig + + $ make + + $ sudo make install (optional, will install into /opt per default) + +As libpayload is for 32bit x86 systems only, you might have to install the +32bit libgcc version, otherwise your payloads will fail to compile. +On Debian systems you'd do 'apt-get install gcc-multilib' for example. + + +Usage +----- + +Here's an example of a very simple payload (hello.c) and how to build it: + + #include <libpayload.h> + + int main(void) + { + printf("Hello, world!\n"); + return 0; + } + +Building the payload using the 'lpgcc' compiler wrapper: + + $ lpgcc -o hello.elf hello.c + +Please see the sample/ directory for details. + + +Website and Mailing List +------------------------ + +The main website is http://www.coreboot.org/Libpayload. + +For additional information, patches, and discussions, please join the +coreboot mailing list at http://coreboot.org/Mailinglist, where most +libpayload developers are subscribed. + + +Copyright and License +--------------------- + +See LICENSES. +

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Re: [coreboot] r785 - in coreboot-v3: arch/x86 arch/x86/amd arch/x86/geodelx include
by ron minnich 18 Aug '08

18 Aug '08

On Mon, Aug 18, 2008 at 9:54 AM, <svn(a)coreboot.org> wrote: > Author: hailfinger > Date: 2008-08-18 18:54:12 +0200 (Mon, 18 Aug 2008) > New Revision: 785 boots to linux on dbe62. nice work! ron

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Re: [coreboot] r784 - in coreboot-v3: arch/x86 device mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3
by Stefan Reinauer 18 Aug '08

18 Aug '08

This patch is bad. Please back it out. svn(a)coreboot.org wrote: > Modified: coreboot-v3/arch/x86/Kconfig > =================================================================== > --- coreboot-v3/arch/x86/Kconfig 2008-08-18 13:03:43 UTC (rev 783) > +++ coreboot-v3/arch/x86/Kconfig 2008-08-18 16:48:27 UTC (rev 784) > @@ -93,12 +93,14 @@ > > config LOGICAL_CPUS > hex > + depends CPU_AMD_K8 > This is a wrong dependency. It does not reflect any physical dependency, nor a real dependency in the code. The opposite. It is the purpose that these variables are used throughout the code to verify the availability of certain features. The correct way of describing this would be to set the above variable to a certain value in CPU_AMD_K8, or any related option. > default 1 > help > How many logical CPUs there are. Fix me. > > config MAX_PHYSICAL_CPUS > hex > + depends CPU_AMD_K8 > dito > default 1 > help > Max number of physical CPUs (sockets) > @@ -138,6 +140,7 @@ > > config SMP > boolean > + depends CPU_I586 || CPU_AMD_K8 > dito > default 0 > help > This option is used to enable certain functions to make > @@ -147,7 +150,7 @@ > > config IOAPIC > boolean > - depends ARCH_X86 > + depends ARCH_X86 && CPU_AMD_K8 > dito > default 0 > help > If you want to configure an IOAPIC, set this. > @@ -216,6 +219,7 @@ > > config USBDEBUG_DIRECT > boolean > + depends SOUTHBRIDGE_NVIDIA_MCP55 > dito > default 0 > help > Determines if we enable USB Direct debugging. If you don't have a dongle, > > Modified: coreboot-v3/device/Kconfig > =================================================================== > --- coreboot-v3/device/Kconfig 2008-08-18 13:03:43 UTC (rev 783) > +++ coreboot-v3/device/Kconfig 2008-08-18 16:48:27 UTC (rev 784) > @@ -97,11 +97,13 @@ > > config PCI_64BIT_PREF_MEM > bool "64 bit prefetchable memory addresses" > + depends CPU_AMD_K8 > dito -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[PATCH] v3: fix Kconfig dependencies, update defconfigs
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

Fix Kconfig dependencies and update defconfigs. A few questions remain: - Should CONFIG_SMP be selectable on GeodeLX and Qemu? Might make sense for debugging. - Should CONFIG_IOAPIC be selectable on GeodeLX and Qemu? Maybe for Qemu. - Should CONFIG_USBDEBUG_DIRECT be selectable on GeodeLX and Qemu? I don't think so. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-Kconfig_dependencies/mainboard/pcengines/alix1c/defconfig =================================================================== --- corebootv3-Kconfig_dependencies/mainboard/pcengines/alix1c/defconfig (Revision 782) +++ corebootv3-Kconfig_dependencies/mainboard/pcengines/alix1c/defconfig (Arbeitskopie) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# coreboot version: 3.0.0 -# Sun Feb 24 11:45:09 2008 +# coreboot version: 3.0.782 +# Mon Aug 18 13:55:17 2008 # # @@ -18,10 +18,12 @@ # CONFIG_VENDOR_ADL is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_EMULATION is not set CONFIG_VENDOR_PCENGINES=y CONFIG_MAINBOARD_DIR="pcengines/alix1c" CONFIG_BOARD_PCENGINES_ALIX1C=y +# CONFIG_BOARD_PCENGINES_ALIX2C3 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set CONFIG_COREBOOT_ROMSIZE_KB_512=y @@ -33,8 +35,11 @@ CONFIG_CPU_AMD_GEODELX=y CONFIG_OPTION_TABLE=y CONFIG_PIRQ_TABLE=y +# CONFIG_SMP is not set +# CONFIG_IOAPIC is not set CONFIG_CARBASE=0x80000 CONFIG_CARSIZE=0x8000 +# CONFIG_USBDEBUG_DIRECT is not set # # Compression Index: corebootv3-Kconfig_dependencies/mainboard/pcengines/alix2c3/defconfig =================================================================== --- corebootv3-Kconfig_dependencies/mainboard/pcengines/alix2c3/defconfig (Revision 782) +++ corebootv3-Kconfig_dependencies/mainboard/pcengines/alix2c3/defconfig (Arbeitskopie) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# coreboot version: 3.0."656"' -# Wed Apr 9 20:59:03 2008 +# coreboot version: 3.0.782 +# Mon Aug 18 13:55:18 2008 # # @@ -17,6 +17,7 @@ # CONFIG_VENDOR_ADL is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_EMULATION is not set CONFIG_VENDOR_PCENGINES=y CONFIG_MAINBOARD_DIR="pcengines/alix2c3" @@ -33,8 +34,11 @@ CONFIG_CPU_AMD_GEODELX=y CONFIG_OPTION_TABLE=y CONFIG_PIRQ_TABLE=y +# CONFIG_SMP is not set +# CONFIG_IOAPIC is not set CONFIG_CARBASE=0x80000 CONFIG_CARSIZE=0x8000 +# CONFIG_USBDEBUG_DIRECT is not set # # Compression Index: corebootv3-Kconfig_dependencies/mainboard/emulation/qemu-x86/defconfig =================================================================== --- corebootv3-Kconfig_dependencies/mainboard/emulation/qemu-x86/defconfig (Revision 782) +++ corebootv3-Kconfig_dependencies/mainboard/emulation/qemu-x86/defconfig (Arbeitskopie) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# coreboot version: 3.0.0 -# Thu Mar 13 07:13:17 2008 +# coreboot version: 3.0.782 +# Mon Aug 18 13:55:12 2008 # # @@ -17,6 +17,7 @@ # CONFIG_VENDOR_ADL is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_GIGABYTE is not set CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_PCENGINES is not set CONFIG_MAINBOARD_DIR="emulation/qemu-x86" @@ -31,8 +32,11 @@ CONFIG_ARCH="x86" CONFIG_CPU_I586=y CONFIG_OPTION_TABLE=y +# CONFIG_SMP is not set +# CONFIG_IOAPIC is not set CONFIG_CARBASE=0x8f000 CONFIG_CARSIZE=0x1000 +# CONFIG_USBDEBUG_DIRECT is not set # # Compression Index: corebootv3-Kconfig_dependencies/device/Kconfig =================================================================== --- corebootv3-Kconfig_dependencies/device/Kconfig (Revision 782) +++ corebootv3-Kconfig_dependencies/device/Kconfig (Arbeitskopie) @@ -97,11 +97,13 @@ config PCI_64BIT_PREF_MEM bool "64 bit prefetchable memory addresses" + depends CPU_AMD_K8 help Enable support for 64-bit prefetchable memory addresses in PCI. config HW_MEM_HOLE_SIZEK hex "HW memory hole size in KB" + depends CPU_AMD_K8 default 0x1000 help Some chipsets support setting up a "hole" at the top of memory. It is essentially Index: corebootv3-Kconfig_dependencies/arch/x86/Kconfig =================================================================== --- corebootv3-Kconfig_dependencies/arch/x86/Kconfig (Revision 782) +++ corebootv3-Kconfig_dependencies/arch/x86/Kconfig (Arbeitskopie) @@ -93,12 +93,14 @@ config LOGICAL_CPUS hex + depends CPU_AMD_K8 default 1 help How many logical CPUs there are. Fix me. config MAX_PHYSICAL_CPUS hex + depends CPU_AMD_K8 default 1 help Max number of physical CPUs (sockets) -- http://www.hailfinger.org/

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r785 - in coreboot-v3: arch/x86 arch/x86/amd arch/x86/geodelx include
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: hailfinger Date: 2008-08-18 18:54:12 +0200 (Mon, 18 Aug 2008) New Revision: 785 Modified: coreboot-v3/arch/x86/amd/stage0.S coreboot-v3/arch/x86/geodelx/stage0.S coreboot-v3/arch/x86/stage0_i586.S coreboot-v3/arch/x86/stage1.c coreboot-v3/include/console.h Log: Move stage1 global variable management from asm to C. The stage0 asm code now unconditionally pushes an empty pointer to the stack which is a placeholder for the pointer to global variable storage. That pointer and the global variable storage are initialized in global_vars_init(). Creating global variables is now a piece of cake. You don't even have to touch any asm code, just add them to struct global_vars. Build tested on all targets, boot tested on Qemu. NOTES: - The code is not yet MP safe, but that's due to v3 not being MP safe in general (and the comments contradict the code regarding MP features). - K8 code now works by accident. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Segher Boessenkool <segher(a)kernel.crashing.org> Modified: coreboot-v3/arch/x86/amd/stage0.S =================================================================== --- coreboot-v3/arch/x86/amd/stage0.S 2008-08-18 16:48:27 UTC (rev 784) +++ coreboot-v3/arch/x86/amd/stage0.S 2008-08-18 16:54:12 UTC (rev 785) @@ -23,7 +23,9 @@ #define CacheBase CONFIG_CARBASE #define MEM_TOPK 2048 -/* leave some space for global variable to pass to RAM stage */ +/* Leave some space for a pointer to the global variables. + * This should most likely be 4. + */ #define GlobalVarSize 32 #ifdef CONFIG_CPU_AMD_K10 Modified: coreboot-v3/arch/x86/geodelx/stage0.S =================================================================== --- coreboot-v3/arch/x86/geodelx/stage0.S 2008-08-18 16:48:27 UTC (rev 784) +++ coreboot-v3/arch/x86/geodelx/stage0.S 2008-08-18 16:54:12 UTC (rev 785) @@ -361,13 +361,10 @@ movw %ax, %ss lout: -#ifdef CONFIG_CONSOLE_BUFFER - /* Store pointer to start of printk buffer, should really use - * PRINTK_BUF_ADDR_CAR instead. - */ - movl $CONFIG_CARBASE, %eax - pushl %eax /* printk buffer */ -#endif + /* Store zero for the pointer to the global variables. */ + movl $0, %eax + pushl %eax + /* Restore the BIST result. */ movl %ebp, %eax Modified: coreboot-v3/arch/x86/stage0_i586.S =================================================================== --- coreboot-v3/arch/x86/stage0_i586.S 2008-08-18 16:48:27 UTC (rev 784) +++ coreboot-v3/arch/x86/stage0_i586.S 2008-08-18 16:54:12 UTC (rev 785) @@ -435,13 +435,10 @@ movw %ax, %ss lout: -#ifdef CONFIG_CONSOLE_BUFFER - /* Store pointer to start of printk buffer, should really use - * PRINTK_BUF_ADDR_CAR instead. - */ - movl $CONFIG_CARBASE, %eax - pushl %eax /* printk buffer */ -#endif + /* Store zero for the pointer to the global variables. */ + movl $0, %eax + pushl %eax + /* Restore the BIST result */ movl %ebp, %eax /* We need to set ebp ? No need */ Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-08-18 16:48:27 UTC (rev 784) +++ coreboot-v3/arch/x86/stage1.c 2008-08-18 16:54:12 UTC (rev 785) @@ -82,9 +82,15 @@ struct global_vars *global_vars(void) { - return (struct global_vars *)(bottom_of_stack() - sizeof(struct global_vars)); + return *(struct global_vars **)(bottom_of_stack() - sizeof(struct global_vars *)); } +void global_vars_init(struct global_vars *globvars) +{ + memset(globvars, 0, sizeof(struct global_vars)); + *(struct global_vars **)(bottom_of_stack() - sizeof(struct global_vars *)) = globvars; +} + void dump_mem_range(int msg_level, unsigned char *buf, int size) { int i; @@ -119,9 +125,11 @@ /* * This function is called from assembler code with its argument on the * stack. Force the compiler to generate always correct code for this case. + * We have cache as ram running and can start executing code in C. */ void __attribute__((stdcall)) stage1_main(u32 bist) { + struct global_vars globvars; int ret; struct mem_file archive; void *entry; @@ -150,10 +158,13 @@ stop_ap(); } - // We have cache as ram running and can start executing code in C. + /* Initialize global variables before we can think of using them. + * NEVER run this on an AP! + */ + global_vars_init(&globvars); #ifdef CONFIG_CONSOLE_BUFFER - /* Initialize the printk buffer. */ + /* Initialize the printk buffer. NEVER run this on an AP! */ printk_buffer_init(); #endif Modified: coreboot-v3/include/console.h =================================================================== --- coreboot-v3/include/console.h 2008-08-18 16:48:27 UTC (rev 784) +++ coreboot-v3/include/console.h 2008-08-18 16:54:12 UTC (rev 785) @@ -60,10 +60,10 @@ #endif /* - * If you change struct global_vars in any way, you have to fix all stage0 asm - * code. The stage0 asm code modification is nontrivial (size of the struct, - * alignment, initialization, order of struct members, initialization). - * Depending on your compiler, real breakage may happen. + * struct global_vars is managed entirely from C code. Keep in mind that there + * is NO buffer at the end of the struct, so having zero-sized arrays at the + * end or similar stuff for which the compiler can't determine the final size + * will corrupt memory. If you don't try to be clever, everything will be fine. */ struct global_vars { #ifdef CONFIG_CONSOLE_BUFFER

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r784 - in coreboot-v3: arch/x86 device mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3
by svn＠coreboot.org 18 Aug '08

18 Aug '08

Author: hailfinger Date: 2008-08-18 18:48:27 +0200 (Mon, 18 Aug 2008) New Revision: 784 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/device/Kconfig coreboot-v3/mainboard/emulation/qemu-x86/defconfig coreboot-v3/mainboard/pcengines/alix1c/defconfig coreboot-v3/mainboard/pcengines/alix2c3/defconfig Log: Fix Kconfig dependencies and update defconfigs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-08-18 13:03:43 UTC (rev 783) +++ coreboot-v3/arch/x86/Kconfig 2008-08-18 16:48:27 UTC (rev 784) @@ -93,12 +93,14 @@ config LOGICAL_CPUS hex + depends CPU_AMD_K8 default 1 help How many logical CPUs there are. Fix me. config MAX_PHYSICAL_CPUS hex + depends CPU_AMD_K8 default 1 help Max number of physical CPUs (sockets) @@ -138,6 +140,7 @@ config SMP boolean + depends CPU_I586 || CPU_AMD_K8 default 0 help This option is used to enable certain functions to make @@ -147,7 +150,7 @@ config IOAPIC boolean - depends ARCH_X86 + depends ARCH_X86 && CPU_AMD_K8 default 0 help If you want to configure an IOAPIC, set this. @@ -216,6 +219,7 @@ config USBDEBUG_DIRECT boolean + depends SOUTHBRIDGE_NVIDIA_MCP55 default 0 help Determines if we enable USB Direct debugging. If you don't have a dongle, Modified: coreboot-v3/device/Kconfig =================================================================== --- coreboot-v3/device/Kconfig 2008-08-18 13:03:43 UTC (rev 783) +++ coreboot-v3/device/Kconfig 2008-08-18 16:48:27 UTC (rev 784) @@ -97,11 +97,13 @@ config PCI_64BIT_PREF_MEM bool "64 bit prefetchable memory addresses" + depends CPU_AMD_K8 help Enable support for 64-bit prefetchable memory addresses in PCI. config HW_MEM_HOLE_SIZEK hex "HW memory hole size in KB" + depends CPU_AMD_K8 default 0x1000 help Some chipsets support setting up a "hole" at the top of memory. It is essentially Modified: coreboot-v3/mainboard/emulation/qemu-x86/defconfig =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-08-18 13:03:43 UTC (rev 783) +++ coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-08-18 16:48:27 UTC (rev 784) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# coreboot version: 3.0.0 -# Thu Mar 13 07:13:17 2008 +# coreboot version: 3.0."782" +# Mon Aug 18 18:45:49 2008 # # @@ -17,6 +17,7 @@ # CONFIG_VENDOR_ADL is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_GIGABYTE is not set CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_PCENGINES is not set CONFIG_MAINBOARD_DIR="emulation/qemu-x86" @@ -31,6 +32,7 @@ CONFIG_ARCH="x86" CONFIG_CPU_I586=y CONFIG_OPTION_TABLE=y +# CONFIG_SMP is not set CONFIG_CARBASE=0x8f000 CONFIG_CARSIZE=0x1000 Modified: coreboot-v3/mainboard/pcengines/alix1c/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/defconfig 2008-08-18 13:03:43 UTC (rev 783) +++ coreboot-v3/mainboard/pcengines/alix1c/defconfig 2008-08-18 16:48:27 UTC (rev 784) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# coreboot version: 3.0.0 -# Sun Feb 24 11:45:09 2008 +# coreboot version: 3.0."782" +# Mon Aug 18 18:45:50 2008 # # @@ -18,10 +18,12 @@ # CONFIG_VENDOR_ADL is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_EMULATION is not set CONFIG_VENDOR_PCENGINES=y CONFIG_MAINBOARD_DIR="pcengines/alix1c" CONFIG_BOARD_PCENGINES_ALIX1C=y +# CONFIG_BOARD_PCENGINES_ALIX2C3 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set CONFIG_COREBOOT_ROMSIZE_KB_512=y Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-08-18 13:03:43 UTC (rev 783) +++ coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-08-18 16:48:27 UTC (rev 784) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# coreboot version: 3.0."656"' -# Wed Apr 9 20:59:03 2008 +# coreboot version: 3.0."782" +# Mon Aug 18 18:45:50 2008 # # @@ -17,6 +17,7 @@ # CONFIG_VENDOR_ADL is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_EMULATION is not set CONFIG_VENDOR_PCENGINES=y CONFIG_MAINBOARD_DIR="pcengines/alix2c3"

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Re: [coreboot] r783 - coreboot-v3/arch/x86
by ron minnich 18 Aug '08

18 Aug '08

On Mon, Aug 18, 2008 at 6:03 AM, <svn(a)coreboot.org> wrote: > Author: hailfinger > Date: 2008-08-18 15:03:43 +0200 (Mon, 18 Aug 2008) > New Revision: 783 > > Modified: > coreboot-v3/arch/x86/stage1.c > Log: > Move otherwise unused stuff inside CONFIG_PAYLOAD_ELF_LOADER. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > > > Modified: coreboot-v3/arch/x86/stage1.c > =================================================================== > --- coreboot-v3/arch/x86/stage1.c 2008-08-18 11:15:43 UTC (rev 782) > +++ coreboot-v3/arch/x86/stage1.c 2008-08-18 13:03:43 UTC (rev 783) > @@ -124,13 +124,12 @@ > { > int ret; > struct mem_file archive; > + void *entry; > #ifdef CONFIG_PAYLOAD_ELF_LOADER > struct mem_file result; > int elfboot_mem(struct lb_memory *mem, void *where, int size); > -#endif /* CONFIG_PAYLOAD_ELF_LOADER */ > - void *entry; > > - /* we can't statically init this hack. */ > + /* Why can't we statically init this hack? */ If you do this: struct lb_memory faker = {whatever}; gcc will put the init. data in the elf data segment. This won't play well with CARI learned this the hard way. What you are doing below is putting the init data in the code segment by making it part of the code sequence. The fix in the following emails with the [0] change to [1] is not only unnecessary it is actually wrong. The [0] means 'array of length undefined at compile time'. You just borked that :-) I will comment on in it the following email :-) ron

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Re: [coreboot] r783 - coreboot-v3/arch/x86
by ron minnich 18 Aug '08

18 Aug '08

as of this rev (783) dbe62 boots linux. ron

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[RFC] v3: cpu.c and cpu.h
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

One thing that's quite a bit confusing in v3 is the mess of cpu.c and cpu.h. include/arch/x86/cpu.h defines lots of functions which should be in a .c file instead. They are: struct cpuid_result cpuid(u32 op); u32 cpuid_eax(u32 op); u32 cpuid_ebx(u32 op); u32 cpuid_ecx(u32 op); u32 cpuid_edx(u32 op); void get_fms(struct cpuinfo_x86 *c, u32 tfms); unsigned long read_cr0(void); void write_cr0(unsigned long cr0); void invd(void); void wbinvd(void); void enable_cache(void); void disable_cache(void); void cpu_relax(void); void hlt(void); arch/x86/geodelx/cpu.c is completely unused, but the contents look important. Why don't we call them? northbridge/amd/k8/cpu.c is used. Can someone please illustrate the underlying architecture? (Background: I'm trying to add timestamping to printk, but I'm totally at a loss where I should place get_timestamp().) Regards, Carl-Daniel -- http://www.hailfinger.org/

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coreboot August 2008