coreboot May 2008

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r3344 build service
by coreboot information 22 May '08

22 May '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3344 to the coreboot source repository and caused the following changes: Change Log: Changes to make flashrom compile (and work) on FreeBSD. This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg(a)icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3344&device=epia-cn&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Re: [coreboot] r3344 - trunk/util/flashrom
by Idwer Vollering 22 May '08

22 May '08

2008/5/22, svn(a)coreboot.org <svn(a)coreboot.org>: > > Author: hailfinger > Date: 2008-05-22 15:22:45 +0200 (Thu, 22 May 2008) > New Revision: 3344 > > Modified: > trunk/util/flashrom/Makefile > trunk/util/flashrom/board_enable.c > trunk/util/flashrom/chipset_enable.c > trunk/util/flashrom/flash.h > trunk/util/flashrom/flashrom.c > trunk/util/flashrom/it87spi.c > Log: > Changes to make flashrom compile (and work) on FreeBSD. > This patch addresses different argument order of outX() calls, > FreeBSD-specific headers, difference in certain type names and system > interface names, and also FreeBSD-specific way of gaining IO port > access. > > Signed-off-by: Andriy Gapon <avg(a)icyb.net.ua> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > > > Modified: trunk/util/flashrom/Makefile > =================================================================== > --- trunk/util/flashrom/Makefile 2008-05-21 22:10:38 UTC (rev 3343) > +++ trunk/util/flashrom/Makefile 2008-05-22 13:22:45 UTC (rev 3344) > @@ -19,6 +19,10 @@ > LDFLAGS = -lpci -lz > STRIP_ARGS = -s > endif > +ifeq ($(OS_ARCH), FreeBSD) > +CFLAGS += -I/usr/local/include > +LDFLAGS += -L/usr/local/lib > +endif > > OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.c \ > sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ > > Modified: trunk/util/flashrom/board_enable.c > =================================================================== > --- trunk/util/flashrom/board_enable.c 2008-05-21 22:10:38 UTC (rev 3343) > +++ trunk/util/flashrom/board_enable.c 2008-05-22 13:22:45 UTC (rev 3344) > @@ -37,36 +37,36 @@ > /* Enter extended functions */ > static void w836xx_ext_enter(uint16_t port) > { > - outb(0x87, port); > - outb(0x87, port); > + OUTB(0x87, port); > + OUTB(0x87, port); > } > > /* Leave extended functions */ > static void w836xx_ext_leave(uint16_t port) > { > - outb(0xAA, port); > + OUTB(0xAA, port); > } > > /* General functions for reading/writing Winbond Super I/Os. */ > static unsigned char wbsio_read(uint16_t index, uint8_t reg) > { > - outb(reg, index); > - return inb(index + 1); > + OUTB(reg, index); > + return INB(index + 1); > } > > static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) > { > - outb(reg, index); > - outb(data, index + 1); > + OUTB(reg, index); > + OUTB(data, index + 1); > } > > static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t > mask) > { > uint8_t tmp; > > - outb(reg, index); > - tmp = inb(index + 1) & ~mask; > - outb(tmp | (data & mask), index + 1); > + OUTB(reg, index); > + tmp = INB(index + 1) & ~mask; > + OUTB(tmp | (data & mask), index + 1); > } > > /** > @@ -172,9 +172,9 @@ > base = pci_read_word(dev, 0x88) & 0xFF80; > > /* Enable GPIO15 which is connected to write protect. */ > - val = inb(base + 0x4D); > + val = INB(base + 0x4D); > val |= 0x80; > - outb(val, base + 0x4D); > + OUTB(val, base + 0x4D); > > return 0; > } > @@ -249,14 +249,14 @@ > > #define ASUSP5A_LOOP 5000 > > - outb(0x00, 0xE807); > - outb(0xEF, 0xE803); > + OUTB(0x00, 0xE807); > + OUTB(0xEF, 0xE803); > > - outb(0xFF, 0xE800); > + OUTB(0xFF, 0xE800); > > for (i = 0; i < ASUSP5A_LOOP; i++) { > - outb(0xE1, 0xFF); > - if (inb(0xE800) & 0x04) > + OUTB(0xE1, 0xFF); > + if (INB(0xE800) & 0x04) > break; > } > > @@ -265,13 +265,13 @@ > return -1; > } > > - outb(0x20, 0xE801); > - outb(0x20, 0xE1); > + OUTB(0x20, 0xE801); > + OUTB(0x20, 0xE1); > > - outb(0xFF, 0xE802); > + OUTB(0xFF, 0xE802); > > for (i = 0; i < ASUSP5A_LOOP; i++) { > - tmp = inb(0xE800); > + tmp = INB(0xE800); > if (tmp & 0x70) > break; > } > @@ -281,24 +281,24 @@ > return -1; > } > > - tmp = inb(0xE804); > + tmp = INB(0xE804); > tmp &= ~0x02; > > - outb(0x00, 0xE807); > - outb(0xEE, 0xE803); > + OUTB(0x00, 0xE807); > + OUTB(0xEE, 0xE803); > > - outb(tmp, 0xE804); > + OUTB(tmp, 0xE804); > > - outb(0xFF, 0xE800); > - outb(0xE1, 0xFF); > + OUTB(0xFF, 0xE800); > + OUTB(0xE1, 0xFF); > > - outb(0x20, 0xE801); > - outb(0x20, 0xE1); > + OUTB(0x20, 0xE801); > + OUTB(0x20, 0xE1); > > - outb(0xFF, 0xE802); > + OUTB(0xFF, 0xE802); > > for (i = 0; i < ASUSP5A_LOOP; i++) { > - tmp = inb(0xE800); > + tmp = INB(0xE800); > if (tmp & 0x70) > break; > } > @@ -316,9 +316,9 @@ > uint8_t byte; > > /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ > - outb(0x45, 0xcd6); > - byte = inb(0xcd7); > - outb(byte | 0x20, 0xcd7); > + OUTB(0x45, 0xcd6); > + byte = INB(0xcd7); > + OUTB(byte | 0x20, 0xcd7); > > return 0; > } > @@ -331,13 +331,13 @@ > uint8_t tmp; > > /* Raise GPIO22. */ > - tmp = inb(0x4036); > - outb(tmp, 0xEB); > + tmp = INB(0x4036); > + OUTB(tmp, 0xEB); > > tmp |= 0x40; > > - outb(tmp, 0x4036); > - outb(tmp, 0xEB); > + OUTB(tmp, 0x4036); > + OUTB(tmp, 0xEB); > > return 0; > } > @@ -360,10 +360,10 @@ > /* Use GPIOBASE register to find where the GPIO is mapped. */ > port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; > > - val = inb(port); > + val = INB(port); > val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ > val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ > - outb(val, port); > + OUTB(val, port); > > return 0; > } > @@ -449,7 +449,7 @@ > /* Use GPIOBASE register to find where the GPIO is mapped. */ > gpiobar = pci_read_word(dev, 0x48) & 0xfffc; > > - val = inl(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ > + val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ > printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); > > /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 > @@ -462,7 +462,7 @@ > */ > val |= (1 << 2) | (1 << 3); > > - outl(val, gpiobar + ICH7_GPIO_LVL2); > + OUTL(val, gpiobar + ICH7_GPIO_LVL2); > > return 0; > } > > Modified: trunk/util/flashrom/chipset_enable.c > =================================================================== > --- trunk/util/flashrom/chipset_enable.c 2008-05-21 22:10:38 UTC > (rev 3343) > +++ trunk/util/flashrom/chipset_enable.c 2008-05-22 13:22:45 UTC > (rev 3344) > @@ -65,37 +65,37 @@ > /* The same thing on SiS 950 Super I/O side... */ > > /* First probe for Super I/O on config port 0x2e. */ > - outb(0x87, 0x2e); > - outb(0x01, 0x2e); > - outb(0x55, 0x2e); > - outb(0x55, 0x2e); > + OUTB(0x87, 0x2e); > + OUTB(0x01, 0x2e); > + OUTB(0x55, 0x2e); > + OUTB(0x55, 0x2e); > > - if (inb(0x2f) != 0x87) { > + if (INB(0x2f) != 0x87) { > /* If that failed, try config port 0x4e. */ > - outb(0x87, 0x4e); > - outb(0x01, 0x4e); > - outb(0x55, 0x4e); > - outb(0xaa, 0x4e); > - if (inb(0x4f) != 0x87) { > + OUTB(0x87, 0x4e); > + OUTB(0x01, 0x4e); > + OUTB(0x55, 0x4e); > + OUTB(0xaa, 0x4e); > + if (INB(0x4f) != 0x87) { > printf("Can not access SiS 950\n"); > return -1; > } > - outb(0x24, 0x4e); > - b = inb(0x4f) | 0xfc; > - outb(0x24, 0x4e); > - outb(b, 0x4f); > - outb(0x02, 0x4e); > - outb(0x02, 0x4f); > + OUTB(0x24, 0x4e); > + b = INB(0x4f) | 0xfc; > + OUTB(0x24, 0x4e); > + OUTB(b, 0x4f); > + OUTB(0x02, 0x4e); > + OUTB(0x02, 0x4f); > } > > - outb(0x24, 0x2e); > - printf("2f is %#x\n", inb(0x2f)); > - b = inb(0x2f) | 0xfc; > - outb(0x24, 0x2e); > - outb(b, 0x2f); > + OUTB(0x24, 0x2e); > + printf("2f is %#x\n", INB(0x2f)); > + b = INB(0x2f) | 0xfc; > + OUTB(0x24, 0x2e); > + OUTB(b, 0x2f); > > - outb(0x02, 0x2e); > - outb(0x02, 0x2f); > + OUTB(0x02, 0x2e); > + OUTB(0x02, 0x2f); > > return 0; > } > @@ -522,13 +522,13 @@ > pci_write_byte(dev, 0x48, tmp); > > /* Now become a bit silly. */ > - tmp = inb(0xc6f); > - outb(tmp, 0xeb); > - outb(tmp, 0xeb); > + tmp = INB(0xc6f); > + OUTB(tmp, 0xeb); > + OUTB(tmp, 0xeb); > tmp |= 0x40; > - outb(tmp, 0xc6f); > - outb(tmp, 0xeb); > - outb(tmp, 0xeb); > + OUTB(tmp, 0xc6f); > + OUTB(tmp, 0xeb); > + OUTB(tmp, 0xeb); > > return 0; > } > > Modified: trunk/util/flashrom/flash.h > =================================================================== > --- trunk/util/flashrom/flash.h 2008-05-21 22:10:38 UTC (rev 3343) > +++ trunk/util/flashrom/flash.h 2008-05-22 13:22:45 UTC (rev 3344) > @@ -30,6 +30,25 @@ > #include <stdint.h> > #include <stdio.h> > > +#ifdef __FreeBSD__ > + #include <machine/cpufunc.h> > + #define off64_t off_t > + #define lseek64 lseek > + #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) > + #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) > + #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) > + #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) > + #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) > + #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) > +#else > + #define OUTB outb > + #define OUTW outw > + #define OUTL outl > + #define INB inb > + #define INW inw > + #define INL inl > +#endif > + > #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) > > struct flashchip { > > Modified: trunk/util/flashrom/flashrom.c > =================================================================== > --- trunk/util/flashrom/flashrom.c 2008-05-21 22:10:38 UTC (rev 3343) > +++ trunk/util/flashrom/flashrom.c 2008-05-22 13:22:45 UTC (rev 3344) > @@ -252,6 +252,9 @@ > int option_index = 0; > int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; > int ret = 0, i; > +#ifdef __FreeBSD__ > + int io_fd; > +#endif > > static struct option long_options[] = { > {"read", 0, 0, 'r'}, > @@ -367,6 +370,8 @@ > /* First get full io access */ > #if defined (__sun) && (defined(__i386) || defined(__amd64)) > if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { > +#elif defined(__FreeBSD__) > + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { > #else > if (iopl(3) != 0) { > #endif > @@ -559,5 +564,8 @@ > if (verify_it) > ret |= verify_flash(flash, buf); > > +#ifdef __FreeBSD__ > + close(io_fd); > +#endif > return ret; > } > > Modified: trunk/util/flashrom/it87spi.c > =================================================================== > --- trunk/util/flashrom/it87spi.c 2008-05-21 22:10:38 UTC (rev 3343) > +++ trunk/util/flashrom/it87spi.c 2008-05-22 13:22:45 UTC (rev 3344) > @@ -40,14 +40,14 @@ > /* Generic Super I/O helper functions */ > uint8_t regval(uint16_t port, uint8_t reg) > { > - outb(reg, port); > - return inb(port + 1); > + OUTB(reg, port); > + return INB(port + 1); > } > > void regwrite(uint16_t port, uint8_t reg, uint8_t val) > { > - outb(reg, port); > - outb(val, port + 1); > + OUTB(reg, port); > + OUTB(val, port + 1); > } > > /* Helper functions for most recent ITE IT87xx Super I/O chips */ > @@ -55,13 +55,13 @@ > #define CHIP_ID_BYTE2_REG 0x21 > static void enter_conf_mode_ite(uint16_t port) > { > - outb(0x87, port); > - outb(0x01, port); > - outb(0x55, port); > + OUTB(0x87, port); > + OUTB(0x01, port); > + OUTB(0x55, port); > if (port == ITE_SUPERIO_PORT1) > - outb(0x55, port); > + OUTB(0x55, port); > else > - outb(0xaa, port); > + OUTB(0xaa, port); > } > > static void exit_conf_mode_ite(uint16_t port) > @@ -129,7 +129,7 @@ > int i; > > do { > - busy = inb(it8716f_flashport) & 0x80; > + busy = INB(it8716f_flashport) & 0x80; > } while (busy); > if (readcnt > 3) { > printf("%s called with unsupported readcnt %i.\n", > @@ -138,27 +138,27 @@ > } > switch (writecnt) { > case 1: > - outb(writearr[0], it8716f_flashport + 1); > + OUTB(writearr[0], it8716f_flashport + 1); > writeenc = 0x0; > break; > case 2: > - outb(writearr[0], it8716f_flashport + 1); > - outb(writearr[1], it8716f_flashport + 7); > + OUTB(writearr[0], it8716f_flashport + 1); > + OUTB(writearr[1], it8716f_flashport + 7); > writeenc = 0x1; > break; > case 4: > - outb(writearr[0], it8716f_flashport + 1); > - outb(writearr[1], it8716f_flashport + 4); > - outb(writearr[2], it8716f_flashport + 3); > - outb(writearr[3], it8716f_flashport + 2); > + OUTB(writearr[0], it8716f_flashport + 1); > + OUTB(writearr[1], it8716f_flashport + 4); > + OUTB(writearr[2], it8716f_flashport + 3); > + OUTB(writearr[3], it8716f_flashport + 2); > writeenc = 0x2; > break; > case 5: > - outb(writearr[0], it8716f_flashport + 1); > - outb(writearr[1], it8716f_flashport + 4); > - outb(writearr[2], it8716f_flashport + 3); > - outb(writearr[3], it8716f_flashport + 2); > - outb(writearr[4], it8716f_flashport + 7); > + OUTB(writearr[0], it8716f_flashport + 1); > + OUTB(writearr[1], it8716f_flashport + 4); > + OUTB(writearr[2], it8716f_flashport + 3); > + OUTB(writearr[3], it8716f_flashport + 2); > + OUTB(writearr[4], it8716f_flashport + 7); > writeenc = 0x3; > break; > default: > @@ -170,15 +170,15 @@ > * Note: > * We can't use writecnt directly, but have to use a strange > encoding. > */ > - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | > (writeenc), it8716f_flashport); > + OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | > (writeenc), it8716f_flashport); > > if (readcnt > 0) { > do { > - busy = inb(it8716f_flashport) & 0x80; > + busy = INB(it8716f_flashport) & 0x80; > } while (busy); > > for (i = 0; i < readcnt; i++) { > - readarr[i] = inb(it8716f_flashport + 5 + i); > + readarr[i] = INB(it8716f_flashport + 5 + i); > } > } > > @@ -190,12 +190,12 @@ > int i; > > spi_write_enable(); > - outb(0x06 , it8716f_flashport + 1); > - outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); > + OUTB(0x06 , it8716f_flashport + 1); > + OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); > for (i = 0; i < 256; i++) { > bios[256 * block + i] = buf[256 * block + i]; > } > - outb(0, it8716f_flashport); > + OUTB(0, it8716f_flashport); > /* Wait until the Write-In-Progress bit is cleared. > * This usually takes 1-10 ms, so wait in 1 ms steps. > */ > @@ -221,7 +221,7 @@ > myusec_delay(10); > } > /* resume normal ops... */ > - outb(0x20, it8716f_flashport); > + OUTB(0x20, it8716f_flashport); > return 0; > } > > > > > -- > coreboot mailing list > coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > The dependencies from ports are: devel/libpci and devel/gmake (as tested on FreeBSD7).

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[PATCH] flashrom for ICH7 VT8237S
by Rudolf Marek 22 May '08

22 May '08

Hi all, Here is preliminary patch for VT8237S SPI interface. Thanks to Dominik and Claus great work only two hours of time were needed to port the code. I was very surprised because it worked on first try (except the 3 byte RDID check below) Some routines are even same but copied, maybe it could be merged. Diff for yourself. The ICH7 should work too once correct MMIO base is selected (this part is missing). VIA and ICH7 are very very similar here, I commented the differences in the source. What works? Now it works with VT8237S + SPI flash MX25L4005 (512 KB) (read tested, rdid tested) and with Amic A25L40P 512KB - tested write,erase?, verify (I just ran -wv) The AMIC flash continuation code is 1 byte so manuf ID is 2 BYTES. And flash ID is two bytes too. So I had to extend the RDID command to 4 bytes. Three byte flash like MX will repeat the first byte as seen on the attached dump. Obviously the ... found at physical address 0xfff80000 is wrong too. Should not be printed when SPI controller. In case someone wants to check the AMIC datasheet http://www.amictechnology.com/pdf/A25L40P.pdf I bought this flash for like 1.30 EUR in http://gme.cz I will have no time for this for nearly two weeks, so if someone wants to work on this here is the chance ;) Well I can just Signed-of-by: Rudolf Marek <r.marek(a)assembler.cz> but the code needs cleanups etc - no time now. Rudolf Calibrating delay loop... 496M loops per second. OK. No coreboot table found. Found chipset "VIA VT8237S", enabling flash write... MMIO base at = 0xfed02000 OK. Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x37 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x7f, id2 0x37 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Amic Technology A25L40P, 512 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Chip status register is 00 A25L40P found at physical address 0xfff80000. Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0x0, id2 0x37, id1 parity violation Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0x0, id2 0x37, id1 parity violation Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0x0, id2 0x37, id1 parity violation Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L4005, 512 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Macronix MX25L8005, 1024 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Macronix MX25L1605, 2048 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Macronix MX25L3205, 4096 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0xdd, id2 0x5c Probing for PMC Pm25LV010, 128 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC Pm25LV020, 256 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC Pm25LV040, 512 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC Pm25LV512, 64 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0x7f7a, id2 0x37 Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for SST SST25VF016B, 2048 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for SST SST25VF040B, 512 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x71, id2 0xf4, id1 parity violation Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xda, id2 0x0 Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P10-A, 128 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P20, 256 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P40, 512 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P40-old, 512 KB: RDID returned 7f 37 20 13. Probing for ST M25P80, 1024 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P16, 2048 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P32, 4096 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P64, 8192 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M25P128, 16384 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W25x10, 128 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Winbond W25x20, 256 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Winbond W25x40, 512 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Winbond W25x80, 1024 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0x50, id2 0x0 Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for EON unknown EON SPI chip, 0 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for PMC unknown PMC SPI chip, 0 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for SST unknown SST SPI chip, 0 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Probing for ST unknown ST SPI chip, 0 KB: RDID returned 7f 37 20 13. probe_spi_rdid: id1 0x7f37, id2 0x2013 Flash part is A25L40P (512 KB). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === No operations were specified. Calibrating delay loop... 470M loops per second. OK. No coreboot table found. Found chipset "VIA VT8237S", enabling flash write... MMIO base at = 0xfed02000 OK. Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xc2, id2 0x20 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xc2, id2 0x20 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Amic Technology A25L40P, 512 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xc2, id2 0x20 Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xc2, id2 0x20 Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xc2, id2 0x20 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L4005, 512 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set MX25L4005 found at physical address 0xfff80000. Probing for Macronix MX25L8005, 1024 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Macronix MX25L1605, 2048 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Macronix MX25L3205, 4096 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0xdd, id2 0x5c Probing for PMC Pm25LV010, 128 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV016B, 2048 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV020, 256 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV040, 512 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV080B, 1024 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC Pm25LV512, 64 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xc2, id2 0x20 Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for SST SST25VF016B, 2048 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for SST SST25VF040B, 512 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0x71, id2 0xf4, id1 parity violation Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xda, id2 0x0 Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P10-A, 128 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P20, 256 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P40, 512 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P40-old, 512 KB: RDID returned c2 20 13 c2. Probing for ST M25P80, 1024 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P16, 2048 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P32, 4096 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P64, 8192 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M25P128, 16384 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W25x10, 128 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Winbond W25x20, 256 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Winbond W25x40, 512 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Winbond W25x80, 1024 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x50, id2 0x0, id1 parity violation Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0x50, id2 0x0 Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xdd, id2 0x5c, id1 parity violation Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for EON unknown EON SPI chip, 0 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for PMC unknown PMC SPI chip, 0 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for SST unknown SST SPI chip, 0 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Probing for ST unknown ST SPI chip, 0 KB: RDID returned c2 20 13 c2. probe_spi_rdid: id1 0xc2, id2 0x2013 Flash part is MX25L4005 (512 KB). === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === No operations were specified.

2 1

r3345 - trunk/util/flashrom
by svn＠coreboot.org 22 May '08

22 May '08

Author: hailfinger Date: 2008-05-22 15:42:23 +0200 (Thu, 22 May 2008) New Revision: 3345 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: Add support for Amic A25L40P SPI flash. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-22 13:22:45 UTC (rev 3344) +++ trunk/util/flashrom/flash.h 2008-05-22 13:42:23 UTC (rev 3345) @@ -117,6 +117,7 @@ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ +#define AMIC_A25L40P 0x2013 #define ASD_ID 0x25 /* ASD, not listed in JEP106W */ #define ASD_AE49F2008 0x52 Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-05-22 13:22:45 UTC (rev 3344) +++ trunk/util/flashrom/flashchips.c 2008-05-22 13:42:23 UTC (rev 3345) @@ -44,6 +44,7 @@ {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Amic Technology","A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},

1 0

flashrom FreeBSD port
by Andriy Gapon 22 May '08

22 May '08

Changes to make flashrom compile (and work) on FreeBSD. This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg(a)icyb.net.ua> This is a better version of the previous patch. It addresses Makefile changes and also enables compilation -Werror. For this I also had to wrap inX() under INX(). -- Andriy Gapon Index: flash.h =================================================================== --- flash.h (revision 3322) +++ flash.h (working copy) @@ -30,6 +30,25 @@ #include <stdint.h> #include <stdio.h> +#ifdef __FreeBSD__ + #include <machine/cpufunc.h> + #define off64_t off_t + #define lseek64 lseek + #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) + #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) + #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) + #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) + #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) + #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) +#else + #define OUTB outb + #define OUTW outw + #define OUTL outl + #define INB inb + #define INW inw + #define INL inl +#endif + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Index: it87spi.c =================================================================== --- it87spi.c (revision 3322) +++ it87spi.c (working copy) @@ -40,14 +40,14 @@ /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) { - outb(reg, port); - return inb(port + 1); + OUTB(reg, port); + return INB(port + 1); } void regwrite(uint16_t port, uint8_t reg, uint8_t val) { - outb(reg, port); - outb(val, port + 1); + OUTB(reg, port); + OUTB(val, port + 1); } /* Helper functions for most recent ITE IT87xx Super I/O chips */ @@ -55,13 +55,13 @@ #define CHIP_ID_BYTE2_REG 0x21 static void enter_conf_mode_ite(uint16_t port) { - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); + OUTB(0x87, port); + OUTB(0x01, port); + OUTB(0x55, port); if (port == ITE_SUPERIO_PORT1) - outb(0x55, port); + OUTB(0x55, port); else - outb(0xaa, port); + OUTB(0xaa, port); } static void exit_conf_mode_ite(uint16_t port) @@ -123,7 +123,7 @@ int i; do { - busy = inb(it8716f_flashport) & 0x80; + busy = INB(it8716f_flashport) & 0x80; } while (busy); if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", @@ -132,27 +132,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], it8716f_flashport + 1); + OUTB(writearr[0], it8716f_flashport + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); - outb(writearr[4], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); + OUTB(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -164,15 +164,15 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); + OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { do { - busy = inb(it8716f_flashport) & 0x80; + busy = INB(it8716f_flashport) & 0x80; } while (busy); for (i = 0; i < readcnt; i++) { - readarr[i] = inb(it8716f_flashport + 5 + i); + readarr[i] = INB(it8716f_flashport + 5 + i); } } @@ -184,12 +184,12 @@ int i; spi_write_enable(); - outb(0x06 , it8716f_flashport + 1); - outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + OUTB(0x06 , it8716f_flashport + 1); + OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } - outb(0, it8716f_flashport); + OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -215,7 +215,7 @@ myusec_delay(10); } /* resume normal ops... */ - outb(0x20, it8716f_flashport); + OUTB(0x20, it8716f_flashport); return 0; } Index: Makefile =================================================================== --- Makefile (revision 3322) +++ Makefile (working copy) @@ -19,6 +19,10 @@ LDFLAGS = -lpci -lz STRIP_ARGS = -s endif +ifeq ($(OS_ARCH), FreeBSD) +CFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.c \ sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3322) +++ chipset_enable.c (working copy) @@ -65,37 +65,37 @@ /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - outb(0x87, 0x2e); - outb(0x01, 0x2e); - outb(0x55, 0x2e); - outb(0x55, 0x2e); + OUTB(0x87, 0x2e); + OUTB(0x01, 0x2e); + OUTB(0x55, 0x2e); + OUTB(0x55, 0x2e); - if (inb(0x2f) != 0x87) { + if (INB(0x2f) != 0x87) { /* If that failed, try config port 0x4e. */ - outb(0x87, 0x4e); - outb(0x01, 0x4e); - outb(0x55, 0x4e); - outb(0xaa, 0x4e); - if (inb(0x4f) != 0x87) { + OUTB(0x87, 0x4e); + OUTB(0x01, 0x4e); + OUTB(0x55, 0x4e); + OUTB(0xaa, 0x4e); + if (INB(0x4f) != 0x87) { printf("Can not access SiS 950\n"); return -1; } - outb(0x24, 0x4e); - b = inb(0x4f) | 0xfc; - outb(0x24, 0x4e); - outb(b, 0x4f); - outb(0x02, 0x4e); - outb(0x02, 0x4f); + OUTB(0x24, 0x4e); + b = INB(0x4f) | 0xfc; + OUTB(0x24, 0x4e); + OUTB(b, 0x4f); + OUTB(0x02, 0x4e); + OUTB(0x02, 0x4f); } - outb(0x24, 0x2e); - printf("2f is %#x\n", inb(0x2f)); - b = inb(0x2f) | 0xfc; - outb(0x24, 0x2e); - outb(b, 0x2f); + OUTB(0x24, 0x2e); + printf("2f is %#x\n", INB(0x2f)); + b = INB(0x2f) | 0xfc; + OUTB(0x24, 0x2e); + OUTB(b, 0x2f); - outb(0x02, 0x2e); - outb(0x02, 0x2f); + OUTB(0x02, 0x2e); + OUTB(0x02, 0x2f); return 0; } @@ -516,13 +516,13 @@ pci_write_byte(dev, 0x48, tmp); /* Now become a bit silly. */ - tmp = inb(0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + tmp = INB(0xc6f); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); tmp |= 0x40; - outb(tmp, 0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + OUTB(tmp, 0xc6f); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); return 0; } Index: flashrom.c =================================================================== --- flashrom.c (revision 3322) +++ flashrom.c (working copy) @@ -252,6 +252,9 @@ int option_index = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int ret = 0, i; +#ifdef __FreeBSD__ + int io_fd; +#endif static struct option long_options[] = { {"read", 0, 0, 'r'}, @@ -367,6 +370,8 @@ /* First get full io access */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { +#elif defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #else if (iopl(3) != 0) { #endif @@ -559,5 +564,8 @@ if (verify_it) ret |= verify_flash(flash, buf); +#ifdef __FreeBSD__ + close(io_fd); +#endif return ret; } Index: board_enable.c =================================================================== --- board_enable.c (revision 3322) +++ board_enable.c (working copy) @@ -37,36 +37,36 @@ /* Enter extended functions */ static void w836xx_ext_enter(uint16_t port) { - outb(0x87, port); - outb(0x87, port); + OUTB(0x87, port); + OUTB(0x87, port); } /* Leave extended functions */ static void w836xx_ext_leave(uint16_t port) { - outb(0xAA, port); + OUTB(0xAA, port); } /* General functions for reading/writing Winbond Super I/Os. */ static unsigned char wbsio_read(uint16_t index, uint8_t reg) { - outb(reg, index); - return inb(index + 1); + OUTB(reg, index); + return INB(index + 1); } static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { - outb(reg, index); - outb(data, index + 1); + OUTB(reg, index); + OUTB(data, index + 1); } static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) { uint8_t tmp; - outb(reg, index); - tmp = inb(index + 1) & ~mask; - outb(tmp | (data & mask), index + 1); + OUTB(reg, index); + tmp = INB(index + 1) & ~mask; + OUTB(tmp | (data & mask), index + 1); } /** @@ -172,9 +172,9 @@ base = pci_read_word(dev, 0x88) & 0xFF80; /* Enable GPIO15 which is connected to write protect. */ - val = inb(base + 0x4D); + val = INB(base + 0x4D); val |= 0x80; - outb(val, base + 0x4D); + OUTB(val, base + 0x4D); return 0; } @@ -249,14 +249,14 @@ #define ASUSP5A_LOOP 5000 - outb(0x00, 0xE807); - outb(0xEF, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEF, 0xE803); - outb(0xFF, 0xE800); + OUTB(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { - outb(0xE1, 0xFF); - if (inb(0xE800) & 0x04) + OUTB(0xE1, 0xFF); + if (INB(0xE800) & 0x04) break; } @@ -265,13 +265,13 @@ return -1; } - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { - tmp = inb(0xE800); + tmp = INB(0xE800); if (tmp & 0x70) break; } @@ -281,24 +281,24 @@ return -1; } - tmp = inb(0xE804); + tmp = INB(0xE804); tmp &= ~0x02; - outb(0x00, 0xE807); - outb(0xEE, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEE, 0xE803); - outb(tmp, 0xE804); + OUTB(tmp, 0xE804); - outb(0xFF, 0xE800); - outb(0xE1, 0xFF); + OUTB(0xFF, 0xE800); + OUTB(0xE1, 0xFF); - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { - tmp = inb(0xE800); + tmp = INB(0xE800); if (tmp & 0x70) break; } @@ -316,9 +316,9 @@ uint8_t byte; /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - outb(0x45, 0xcd6); - byte = inb(0xcd7); - outb(byte | 0x20, 0xcd7); + OUTB(0x45, 0xcd6); + byte = INB(0xcd7); + OUTB(byte | 0x20, 0xcd7); return 0; } @@ -331,13 +331,13 @@ uint8_t tmp; /* Raise GPIO22. */ - tmp = inb(0x4036); - outb(tmp, 0xEB); + tmp = INB(0x4036); + OUTB(tmp, 0xEB); tmp |= 0x40; - outb(tmp, 0x4036); - outb(tmp, 0xEB); + OUTB(tmp, 0x4036); + OUTB(tmp, 0xEB); return 0; } @@ -360,10 +360,10 @@ /* Use GPIOBASE register to find where the GPIO is mapped. */ port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - val = inb(port); + val = INB(port); val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - outb(val, port); + OUTB(val, port); return 0; } @@ -449,7 +449,7 @@ /* Use GPIOBASE register to find where the GPIO is mapped. */ gpiobar = pci_read_word(dev, 0x48) & 0xfffc; - val = inl(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ + val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 @@ -462,7 +462,7 @@ */ val |= (1 << 2) | (1 << 3); - outl(val, gpiobar + ICH7_GPIO_LVL2); + OUTL(val, gpiobar + ICH7_GPIO_LVL2); return 0; }

2 1

r3344 - trunk/util/flashrom
by svn＠coreboot.org 22 May '08

22 May '08

Author: hailfinger Date: 2008-05-22 15:22:45 +0200 (Thu, 22 May 2008) New Revision: 3344 Modified: trunk/util/flashrom/Makefile trunk/util/flashrom/board_enable.c trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/flashrom.c trunk/util/flashrom/it87spi.c Log: Changes to make flashrom compile (and work) on FreeBSD. This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg(a)icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/Makefile =================================================================== --- trunk/util/flashrom/Makefile 2008-05-21 22:10:38 UTC (rev 3343) +++ trunk/util/flashrom/Makefile 2008-05-22 13:22:45 UTC (rev 3344) @@ -19,6 +19,10 @@ LDFLAGS = -lpci -lz STRIP_ARGS = -s endif +ifeq ($(OS_ARCH), FreeBSD) +CFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib +endif OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.c \ sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-05-21 22:10:38 UTC (rev 3343) +++ trunk/util/flashrom/board_enable.c 2008-05-22 13:22:45 UTC (rev 3344) @@ -37,36 +37,36 @@ /* Enter extended functions */ static void w836xx_ext_enter(uint16_t port) { - outb(0x87, port); - outb(0x87, port); + OUTB(0x87, port); + OUTB(0x87, port); } /* Leave extended functions */ static void w836xx_ext_leave(uint16_t port) { - outb(0xAA, port); + OUTB(0xAA, port); } /* General functions for reading/writing Winbond Super I/Os. */ static unsigned char wbsio_read(uint16_t index, uint8_t reg) { - outb(reg, index); - return inb(index + 1); + OUTB(reg, index); + return INB(index + 1); } static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { - outb(reg, index); - outb(data, index + 1); + OUTB(reg, index); + OUTB(data, index + 1); } static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) { uint8_t tmp; - outb(reg, index); - tmp = inb(index + 1) & ~mask; - outb(tmp | (data & mask), index + 1); + OUTB(reg, index); + tmp = INB(index + 1) & ~mask; + OUTB(tmp | (data & mask), index + 1); } /** @@ -172,9 +172,9 @@ base = pci_read_word(dev, 0x88) & 0xFF80; /* Enable GPIO15 which is connected to write protect. */ - val = inb(base + 0x4D); + val = INB(base + 0x4D); val |= 0x80; - outb(val, base + 0x4D); + OUTB(val, base + 0x4D); return 0; } @@ -249,14 +249,14 @@ #define ASUSP5A_LOOP 5000 - outb(0x00, 0xE807); - outb(0xEF, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEF, 0xE803); - outb(0xFF, 0xE800); + OUTB(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { - outb(0xE1, 0xFF); - if (inb(0xE800) & 0x04) + OUTB(0xE1, 0xFF); + if (INB(0xE800) & 0x04) break; } @@ -265,13 +265,13 @@ return -1; } - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { - tmp = inb(0xE800); + tmp = INB(0xE800); if (tmp & 0x70) break; } @@ -281,24 +281,24 @@ return -1; } - tmp = inb(0xE804); + tmp = INB(0xE804); tmp &= ~0x02; - outb(0x00, 0xE807); - outb(0xEE, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEE, 0xE803); - outb(tmp, 0xE804); + OUTB(tmp, 0xE804); - outb(0xFF, 0xE800); - outb(0xE1, 0xFF); + OUTB(0xFF, 0xE800); + OUTB(0xE1, 0xFF); - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { - tmp = inb(0xE800); + tmp = INB(0xE800); if (tmp & 0x70) break; } @@ -316,9 +316,9 @@ uint8_t byte; /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - outb(0x45, 0xcd6); - byte = inb(0xcd7); - outb(byte | 0x20, 0xcd7); + OUTB(0x45, 0xcd6); + byte = INB(0xcd7); + OUTB(byte | 0x20, 0xcd7); return 0; } @@ -331,13 +331,13 @@ uint8_t tmp; /* Raise GPIO22. */ - tmp = inb(0x4036); - outb(tmp, 0xEB); + tmp = INB(0x4036); + OUTB(tmp, 0xEB); tmp |= 0x40; - outb(tmp, 0x4036); - outb(tmp, 0xEB); + OUTB(tmp, 0x4036); + OUTB(tmp, 0xEB); return 0; } @@ -360,10 +360,10 @@ /* Use GPIOBASE register to find where the GPIO is mapped. */ port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - val = inb(port); + val = INB(port); val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - outb(val, port); + OUTB(val, port); return 0; } @@ -449,7 +449,7 @@ /* Use GPIOBASE register to find where the GPIO is mapped. */ gpiobar = pci_read_word(dev, 0x48) & 0xfffc; - val = inl(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ + val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 @@ -462,7 +462,7 @@ */ val |= (1 << 2) | (1 << 3); - outl(val, gpiobar + ICH7_GPIO_LVL2); + OUTL(val, gpiobar + ICH7_GPIO_LVL2); return 0; } Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-05-21 22:10:38 UTC (rev 3343) +++ trunk/util/flashrom/chipset_enable.c 2008-05-22 13:22:45 UTC (rev 3344) @@ -65,37 +65,37 @@ /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - outb(0x87, 0x2e); - outb(0x01, 0x2e); - outb(0x55, 0x2e); - outb(0x55, 0x2e); + OUTB(0x87, 0x2e); + OUTB(0x01, 0x2e); + OUTB(0x55, 0x2e); + OUTB(0x55, 0x2e); - if (inb(0x2f) != 0x87) { + if (INB(0x2f) != 0x87) { /* If that failed, try config port 0x4e. */ - outb(0x87, 0x4e); - outb(0x01, 0x4e); - outb(0x55, 0x4e); - outb(0xaa, 0x4e); - if (inb(0x4f) != 0x87) { + OUTB(0x87, 0x4e); + OUTB(0x01, 0x4e); + OUTB(0x55, 0x4e); + OUTB(0xaa, 0x4e); + if (INB(0x4f) != 0x87) { printf("Can not access SiS 950\n"); return -1; } - outb(0x24, 0x4e); - b = inb(0x4f) | 0xfc; - outb(0x24, 0x4e); - outb(b, 0x4f); - outb(0x02, 0x4e); - outb(0x02, 0x4f); + OUTB(0x24, 0x4e); + b = INB(0x4f) | 0xfc; + OUTB(0x24, 0x4e); + OUTB(b, 0x4f); + OUTB(0x02, 0x4e); + OUTB(0x02, 0x4f); } - outb(0x24, 0x2e); - printf("2f is %#x\n", inb(0x2f)); - b = inb(0x2f) | 0xfc; - outb(0x24, 0x2e); - outb(b, 0x2f); + OUTB(0x24, 0x2e); + printf("2f is %#x\n", INB(0x2f)); + b = INB(0x2f) | 0xfc; + OUTB(0x24, 0x2e); + OUTB(b, 0x2f); - outb(0x02, 0x2e); - outb(0x02, 0x2f); + OUTB(0x02, 0x2e); + OUTB(0x02, 0x2f); return 0; } @@ -522,13 +522,13 @@ pci_write_byte(dev, 0x48, tmp); /* Now become a bit silly. */ - tmp = inb(0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + tmp = INB(0xc6f); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); tmp |= 0x40; - outb(tmp, 0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + OUTB(tmp, 0xc6f); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); return 0; } Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-05-21 22:10:38 UTC (rev 3343) +++ trunk/util/flashrom/flash.h 2008-05-22 13:22:45 UTC (rev 3344) @@ -30,6 +30,25 @@ #include <stdint.h> #include <stdio.h> +#ifdef __FreeBSD__ + #include <machine/cpufunc.h> + #define off64_t off_t + #define lseek64 lseek + #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0) + #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0) + #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0) + #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); }) + #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) + #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) +#else + #define OUTB outb + #define OUTW outw + #define OUTL outl + #define INB inb + #define INW inw + #define INL inl +#endif + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-05-21 22:10:38 UTC (rev 3343) +++ trunk/util/flashrom/flashrom.c 2008-05-22 13:22:45 UTC (rev 3344) @@ -252,6 +252,9 @@ int option_index = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int ret = 0, i; +#ifdef __FreeBSD__ + int io_fd; +#endif static struct option long_options[] = { {"read", 0, 0, 'r'}, @@ -367,6 +370,8 @@ /* First get full io access */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { +#elif defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #else if (iopl(3) != 0) { #endif @@ -559,5 +564,8 @@ if (verify_it) ret |= verify_flash(flash, buf); +#ifdef __FreeBSD__ + close(io_fd); +#endif return ret; } Modified: trunk/util/flashrom/it87spi.c =================================================================== --- trunk/util/flashrom/it87spi.c 2008-05-21 22:10:38 UTC (rev 3343) +++ trunk/util/flashrom/it87spi.c 2008-05-22 13:22:45 UTC (rev 3344) @@ -40,14 +40,14 @@ /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) { - outb(reg, port); - return inb(port + 1); + OUTB(reg, port); + return INB(port + 1); } void regwrite(uint16_t port, uint8_t reg, uint8_t val) { - outb(reg, port); - outb(val, port + 1); + OUTB(reg, port); + OUTB(val, port + 1); } /* Helper functions for most recent ITE IT87xx Super I/O chips */ @@ -55,13 +55,13 @@ #define CHIP_ID_BYTE2_REG 0x21 static void enter_conf_mode_ite(uint16_t port) { - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); + OUTB(0x87, port); + OUTB(0x01, port); + OUTB(0x55, port); if (port == ITE_SUPERIO_PORT1) - outb(0x55, port); + OUTB(0x55, port); else - outb(0xaa, port); + OUTB(0xaa, port); } static void exit_conf_mode_ite(uint16_t port) @@ -129,7 +129,7 @@ int i; do { - busy = inb(it8716f_flashport) & 0x80; + busy = INB(it8716f_flashport) & 0x80; } while (busy); if (readcnt > 3) { printf("%s called with unsupported readcnt %i.\n", @@ -138,27 +138,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], it8716f_flashport + 1); + OUTB(writearr[0], it8716f_flashport + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); - outb(writearr[4], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); + OUTB(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -170,15 +170,15 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); + OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { do { - busy = inb(it8716f_flashport) & 0x80; + busy = INB(it8716f_flashport) & 0x80; } while (busy); for (i = 0; i < readcnt; i++) { - readarr[i] = inb(it8716f_flashport + 5 + i); + readarr[i] = INB(it8716f_flashport + 5 + i); } } @@ -190,12 +190,12 @@ int i; spi_write_enable(); - outb(0x06 , it8716f_flashport + 1); - outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + OUTB(0x06 , it8716f_flashport + 1); + OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } - outb(0, it8716f_flashport); + OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -221,7 +221,7 @@ myusec_delay(10); } /* resume normal ops... */ - outb(0x20, it8716f_flashport); + OUTB(0x20, it8716f_flashport); return 0; }

1 0

flashrom FreeBSD port
by Andriy Gapon 22 May '08

22 May '08

Changes to make flashrom compile (and work) on FreeBSD. This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. This patch doesn't address Makefile. Signed-off-by: Andriy Gapon <avg(a)icyb.net.ua> -- Andriy Gapon Index: flash.h =================================================================== --- flash.h (revision 3322) +++ flash.h (working copy) @@ -30,6 +30,19 @@ #include <stdint.h> #include <stdio.h> +#ifdef __FreeBSD__ + #include <machine/cpufunc.h> + #define off64_t off_t + #define lseek64 lseek + #define OUTB(x, y) outb((u_int)(y), (u_char)(x)) + #define OUTW(x, y) outw((u_int)(y), (u_short)(x)) + #define OUTL(x, y) outl((u_int)(y), (u_int)(x)) +#else + #define OUTB outb + #define OUTW outw + #define OUTL outl +#endif + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) struct flashchip { Index: it87spi.c =================================================================== --- it87spi.c (revision 3322) +++ it87spi.c (working copy) @@ -40,14 +40,14 @@ /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) { - outb(reg, port); + OUTB(reg, port); return inb(port + 1); } void regwrite(uint16_t port, uint8_t reg, uint8_t val) { - outb(reg, port); - outb(val, port + 1); + OUTB(reg, port); + OUTB(val, port + 1); } /* Helper functions for most recent ITE IT87xx Super I/O chips */ @@ -55,13 +55,13 @@ #define CHIP_ID_BYTE2_REG 0x21 static void enter_conf_mode_ite(uint16_t port) { - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); + OUTB(0x87, port); + OUTB(0x01, port); + OUTB(0x55, port); if (port == ITE_SUPERIO_PORT1) - outb(0x55, port); + OUTB(0x55, port); else - outb(0xaa, port); + OUTB(0xaa, port); } static void exit_conf_mode_ite(uint16_t port) @@ -132,27 +132,27 @@ } switch (writecnt) { case 1: - outb(writearr[0], it8716f_flashport + 1); + OUTB(writearr[0], it8716f_flashport + 1); writeenc = 0x0; break; case 2: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 7); writeenc = 0x1; break; case 4: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); writeenc = 0x2; break; case 5: - outb(writearr[0], it8716f_flashport + 1); - outb(writearr[1], it8716f_flashport + 4); - outb(writearr[2], it8716f_flashport + 3); - outb(writearr[3], it8716f_flashport + 2); - outb(writearr[4], it8716f_flashport + 7); + OUTB(writearr[0], it8716f_flashport + 1); + OUTB(writearr[1], it8716f_flashport + 4); + OUTB(writearr[2], it8716f_flashport + 3); + OUTB(writearr[3], it8716f_flashport + 2); + OUTB(writearr[4], it8716f_flashport + 7); writeenc = 0x3; break; default: @@ -164,7 +164,7 @@ * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); + OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport); if (readcnt > 0) { do { @@ -184,12 +184,12 @@ int i; spi_write_enable(); - outb(0x06 , it8716f_flashport + 1); - outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); + OUTB(0x06 , it8716f_flashport + 1); + OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } - outb(0, it8716f_flashport); + OUTB(0, it8716f_flashport); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-10 ms, so wait in 1 ms steps. */ @@ -215,7 +215,7 @@ myusec_delay(10); } /* resume normal ops... */ - outb(0x20, it8716f_flashport); + OUTB(0x20, it8716f_flashport); return 0; } Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3322) +++ chipset_enable.c (working copy) @@ -65,37 +65,37 @@ /* The same thing on SiS 950 Super I/O side... */ /* First probe for Super I/O on config port 0x2e. */ - outb(0x87, 0x2e); - outb(0x01, 0x2e); - outb(0x55, 0x2e); - outb(0x55, 0x2e); + OUTB(0x87, 0x2e); + OUTB(0x01, 0x2e); + OUTB(0x55, 0x2e); + OUTB(0x55, 0x2e); if (inb(0x2f) != 0x87) { /* If that failed, try config port 0x4e. */ - outb(0x87, 0x4e); - outb(0x01, 0x4e); - outb(0x55, 0x4e); - outb(0xaa, 0x4e); + OUTB(0x87, 0x4e); + OUTB(0x01, 0x4e); + OUTB(0x55, 0x4e); + OUTB(0xaa, 0x4e); if (inb(0x4f) != 0x87) { printf("Can not access SiS 950\n"); return -1; } - outb(0x24, 0x4e); + OUTB(0x24, 0x4e); b = inb(0x4f) | 0xfc; - outb(0x24, 0x4e); - outb(b, 0x4f); - outb(0x02, 0x4e); - outb(0x02, 0x4f); + OUTB(0x24, 0x4e); + OUTB(b, 0x4f); + OUTB(0x02, 0x4e); + OUTB(0x02, 0x4f); } - outb(0x24, 0x2e); + OUTB(0x24, 0x2e); printf("2f is %#x\n", inb(0x2f)); b = inb(0x2f) | 0xfc; - outb(0x24, 0x2e); - outb(b, 0x2f); + OUTB(0x24, 0x2e); + OUTB(b, 0x2f); - outb(0x02, 0x2e); - outb(0x02, 0x2f); + OUTB(0x02, 0x2e); + OUTB(0x02, 0x2f); return 0; } @@ -517,12 +517,12 @@ /* Now become a bit silly. */ tmp = inb(0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); tmp |= 0x40; - outb(tmp, 0xc6f); - outb(tmp, 0xeb); - outb(tmp, 0xeb); + OUTB(tmp, 0xc6f); + OUTB(tmp, 0xeb); + OUTB(tmp, 0xeb); return 0; } Index: flashrom.c =================================================================== --- flashrom.c (revision 3322) +++ flashrom.c (working copy) @@ -252,6 +252,9 @@ int option_index = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int ret = 0, i; +#ifdef __FreeBSD__ + int io_fd; +#endif static struct option long_options[] = { {"read", 0, 0, 'r'}, @@ -367,6 +370,8 @@ /* First get full io access */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { +#elif defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { #else if (iopl(3) != 0) { #endif @@ -559,5 +564,8 @@ if (verify_it) ret |= verify_flash(flash, buf); +#ifdef __FreeBSD__ + close(io_fd); +#endif return ret; } Index: board_enable.c =================================================================== --- board_enable.c (revision 3322) +++ board_enable.c (working copy) @@ -37,36 +37,36 @@ /* Enter extended functions */ static void w836xx_ext_enter(uint16_t port) { - outb(0x87, port); - outb(0x87, port); + OUTB(0x87, port); + OUTB(0x87, port); } /* Leave extended functions */ static void w836xx_ext_leave(uint16_t port) { - outb(0xAA, port); + OUTB(0xAA, port); } /* General functions for reading/writing Winbond Super I/Os. */ static unsigned char wbsio_read(uint16_t index, uint8_t reg) { - outb(reg, index); + OUTB(reg, index); return inb(index + 1); } static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { - outb(reg, index); - outb(data, index + 1); + OUTB(reg, index); + OUTB(data, index + 1); } static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) { uint8_t tmp; - outb(reg, index); + OUTB(reg, index); tmp = inb(index + 1) & ~mask; - outb(tmp | (data & mask), index + 1); + OUTB(tmp | (data & mask), index + 1); } /** @@ -174,7 +174,7 @@ /* Enable GPIO15 which is connected to write protect. */ val = inb(base + 0x4D); val |= 0x80; - outb(val, base + 0x4D); + OUTB(val, base + 0x4D); return 0; } @@ -249,13 +249,13 @@ #define ASUSP5A_LOOP 5000 - outb(0x00, 0xE807); - outb(0xEF, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEF, 0xE803); - outb(0xFF, 0xE800); + OUTB(0xFF, 0xE800); for (i = 0; i < ASUSP5A_LOOP; i++) { - outb(0xE1, 0xFF); + OUTB(0xE1, 0xFF); if (inb(0xE800) & 0x04) break; } @@ -265,10 +265,10 @@ return -1; } - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = inb(0xE800); @@ -284,18 +284,18 @@ tmp = inb(0xE804); tmp &= ~0x02; - outb(0x00, 0xE807); - outb(0xEE, 0xE803); + OUTB(0x00, 0xE807); + OUTB(0xEE, 0xE803); - outb(tmp, 0xE804); + OUTB(tmp, 0xE804); - outb(0xFF, 0xE800); - outb(0xE1, 0xFF); + OUTB(0xFF, 0xE800); + OUTB(0xE1, 0xFF); - outb(0x20, 0xE801); - outb(0x20, 0xE1); + OUTB(0x20, 0xE801); + OUTB(0x20, 0xE1); - outb(0xFF, 0xE802); + OUTB(0xFF, 0xE802); for (i = 0; i < ASUSP5A_LOOP; i++) { tmp = inb(0xE800); @@ -316,9 +316,9 @@ uint8_t byte; /* Set GPIO lines in the Broadcom HT-1000 southbridge. */ - outb(0x45, 0xcd6); + OUTB(0x45, 0xcd6); byte = inb(0xcd7); - outb(byte | 0x20, 0xcd7); + OUTB(byte | 0x20, 0xcd7); return 0; } @@ -332,12 +332,12 @@ /* Raise GPIO22. */ tmp = inb(0x4036); - outb(tmp, 0xEB); + OUTB(tmp, 0xEB); tmp |= 0x40; - outb(tmp, 0x4036); - outb(tmp, 0xEB); + OUTB(tmp, 0x4036); + OUTB(tmp, 0xEB); return 0; } @@ -363,7 +363,7 @@ val = inb(port); val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - outb(val, port); + OUTB(val, port); return 0; } @@ -462,7 +462,7 @@ */ val |= (1 << 2) | (1 << 3); - outl(val, gpiobar + ICH7_GPIO_LVL2); + OUTL(val, gpiobar + ICH7_GPIO_LVL2); return 0; }

3 2

legacybios update
by Kevin O'Connor 22 May '08

22 May '08

Hi, I've just pushed a new elf payload to: http://linuxtogo.org/~kevin/legacybios/bios.bin.elf-20080518 This version should be free of qemu dependencies. In particular, it no longer relies on parameters passed in nvram. The code will still access CMOS_RESET_CODE (0x0f), CMOS_FLOPPY_DRIVE_TYPE (0x10), and CMOS_CENTURY (0x32). However, I think these nvram locations are pretty standard and basically harmless. The above payload will not populate PIR, MPTABLE, SMBIOS, or ACPI tables. Also, just to facilitate testing, I've hardcoded the memory to 128Megs, and I've hardcoded a standard boot order (floppy, cdrom, then hard drive). I've tested the payload with coreboot-v3 and qemu. The above payload plugs into the standard coreboot-v3 elf payload config. I did not customize the coreboot code at all - however, I did disable "Execute PCI Option ROMs" in the coreboot config. It looks like I'll need to acquire some real hardware to test on. Any suggestions? Anyone willing to try the above on real hardware? :-) -Kevin

5 11

Re: [coreboot] buildrom
by qchwu 22 May '08

22 May '08

dear ward The error message list here. > Unpacking filo... > Patching filo... > Applying patch make.patch > Now at patch make.patch > make[1]: Entering directory `/bios/buildrom/buildrom-devel/work/filo/svn' > rm -f include/arch > ln -s ../i386/include include/arch > test -f Config && mv Config Config.bak || true > cat defconfig i386/defconfig >>Config > *** Default Config file is created *** > *** Now you examine this file and edit it as you like *** > make[1]: Leaving directory `/bios/buildrom/buildrom-devel/work/filo/svn' > Building filo... > make[1]: Entering directory `/bios/buildrom/buildrom-devel/work/filo/svn' > Makefile:63: 3/4-,ae-L--o,^2,C,^1O/OUA:?+-e!DEGclean!+-uA:Au:Ai > makerules:46: 3/4-,ae-L--o-oo:AO^1O/OUA:?+-e!DEGclean!+-uA: 3/4EAu:Ai > echo '#define PROGRAM_NAME "FILO"' > main/version.h > echo '#define PROGRAM_VERSION "0.5 (root@localhost) Wed May 21 03:25:00 > CST 2008"' >> main/version.h > make -C main > make[2]: Entering directory > `/bios/buildrom/buildrom-devel/work/filo/svn/main' > /bin/echo -e '/* GENERATED FILE, DO NOT EDIT */\n' >../config.h > sed -e 's/#.*//' -e '/=/!d' -e > 's/$[^[:space:]]*$[[:space:]]*=[[:space:]]*$.*$.*/#define \1 \2/' -e > 's/^#define $[^ ]*$ 0$/#undef \1/' ../Config > > >>../config.h > gcc -m32 -nostdinc -Os -isystem > /bios/buildrom/buildrom-devel/staging/include > -isystem /include -fno-stack-protector -Wall -Os -fomit-frame-pointer > -fno-common -ffreestanding -fno-strict-aliasing -Wno-pointer-sign > -Wno-unused - > > nostdinc -imacros ../config.h -I../include -IDEG^2 > *DEG-L--o/usr/local/gcc-4.2.2/lib/gcc/i386-redhat-linux/4.2.2/include -MD > -c filo.c -o filo.o > OUDEGu:-oNOT *O filo.c-L--o1 uA:IA: 1/4thO:D-: > ../include/lib.h:4:20: 'iIo-L--ostddef.h-L--oA>>OD-A:C,,o:IA: 1/4th>>oA:?A > 1/4 > In file included from filo.c:1: > ../include/lib.h:36: 'iIo-L--oexpected !(R))!- before !(R)size!- > ../include/lib.h:38: 'iIo-L--oexpected !(R))!- before !(R)nmemb!- > ../include/lib.h:39: 'iIo-L--oexpected declaration specifiers or !(R)...!- > before !(R)size_t!- > ../include/lib.h:42: 'iIo-L--oexpected !(R))!- before !(R)size!- > ../include/lib.h:46: 'iIo-L--oexpected !(R)=!-, !(R),!-, !(R);!-, > !(R)asm!- or !(R)__attribute__!- before !(R)strnlen!- > ../include/lib.h:47: 'iIo-L--oexpected !(R)=!-, !(R),!-, !(R);!-, > !(R)asm!- or !(R)__attribute__!- before !(R)strlen!- > ../include/lib.h:49: 'iIo-L--oexpected declaration specifiers or !(R)...!- > before !(R)size_t!- > ../include/lib.h:50: 'iIo-L--oexpected declaration specifiers or !(R)...!- > before !(R)size_t!- > ../include/lib.h:51: 'iIo-L--oexpected declaration specifiers or !(R)...!- > before !(R)size_t!- > ../include/lib.h:52: 'iIo-L--oexpected declaration specifiers or !(R)...!- > before !(R)size_t!- > make[2]: *** [filo.o] 'iIo 1 > make[2]: Leaving directory > `/bios/buildrom/buildrom-devel/work/filo/svn/main' > make[1]: *** [main/builtin.o] 'iIo 2 > make[1]: Leaving directory `/bios/buildrom/buildrom-devel/work/filo/svn' > make: *** [/bios/buildrom/buildrom-devel/work/filo/svn/filo.elf] 'iIo 2 > [root@localhost buildrom-devel]# My gcc version is 4.2.2.The MAKE version is 3.79.1.linux kernel is 2.4.20. The system base on 32-bit. How can i fix this bug?

1 0

r3343 build service
by coreboot information 21 May '08

21 May '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3343 to the coreboot source repository and caused the following changes: Change Log: This is a simple patch which allows payloads to be placed in memory in the range of 0xf0000-0x100000, where the Coreboot tables live in v2. As long as the payload doesn't need the tables, it seems harmless, so why not just print a warning? This allows v2 to load "legacybios" without having to have a separate loader. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> It'll be fine for testing and doesn't really break anything that did work before... Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3343&device=epia-cn&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

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coreboot May 2008