coreboot April 2008

coreboot@coreboot.org

75 participants
404 discussions

r3210 - in trunk/payloads/libpayload: . include libc
by svn＠coreboot.org 02 Apr '08

02 Apr '08

Author: uwe Date: 2008-04-02 14:35:45 +0200 (Wed, 02 Apr 2008) New Revision: 3210 Modified: trunk/payloads/libpayload/LICENSES trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/libc/printf.c Log: Add missing snprintf() to libc/printf.c (trivial). This is also taken from the HelenOS project. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/LICENSES =================================================================== --- trunk/payloads/libpayload/LICENSES 2008-04-01 17:14:57 UTC (rev 3209) +++ trunk/payloads/libpayload/LICENSES 2008-04-02 12:35:45 UTC (rev 3210) @@ -78,6 +78,7 @@ svn checkout svn://svn.helenos.eu/HelenOS/trunk HelenOS http://svn.helenos.eu/chora/browse.php?f=%2Ftrunk%2F Original files: kernel/generic/src/printf/printf_core.c + kernel/generic/src/printf/snprintf.c kernel/generic/src/printf/sprintf.c kernel/generic/src/printf/vsnprintf.c kernel/generic/src/printf/vsprintf.c Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-04-01 17:14:57 UTC (rev 3209) +++ trunk/payloads/libpayload/include/libpayload.h 2008-04-02 12:35:45 UTC (rev 3210) @@ -110,6 +110,7 @@ int memcmp(const char *s1, const char *s2, size_t len); /* libc/printf.c */ +int snprintf(char *str, size_t size, const char *fmt, ...); int sprintf(char *str, const char *fmt, ...); int vsnprintf(char *str, size_t size, const char *fmt, va_list ap); int vsprintf(char *str, const char *fmt, va_list ap); Modified: trunk/payloads/libpayload/libc/printf.c =================================================================== --- trunk/payloads/libpayload/libc/printf.c 2008-04-01 17:14:57 UTC (rev 3209) +++ trunk/payloads/libpayload/libc/printf.c 2008-04-02 12:35:45 UTC (rev 3210) @@ -694,6 +694,18 @@ return counter; } +int snprintf(char *str, size_t size, const char *fmt, ...) +{ + int ret; + va_list args; + + va_start(args, fmt); + ret = vsnprintf(str, size, fmt, args); + va_end(args); + + return ret; +} + int sprintf(char *str, const char *fmt, ...) { int ret;

1 0

Re: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
by coreboot 02 Apr '08

02 Apr '08

#76: LinuxBIOS messages should be accessible in dmesg ----------------------------+----------------------------------------------- Reporter: stepan | Owner: rminnich Type: enhancement | Status: new Priority: major | Milestone: Setting up LinuxBIOS v3 Component: coreboot | Version: v3 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Comment (by anonymous): No. The code in r590 only creates infrastructure within coreboot. Someone on the uboot mailing list stated that you have to change the linux kernel to know where to look for the buffer (and potentially check the format, not sure). This (at least a pointer to the log) should be passed in the coreboot table. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:3> coreboot <http://www.coreboot.org/>

1 0

PCI irq routing
by Nikolay Petukhov 02 Apr '08

02 Apr '08

Hi, all. Now coreboot perform irq routing for some boards. You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5…] for the right setup irq. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add irq routing for AMD/GX1 boards in coreboot. The pirq.patch for irq routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign irq for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.part depends of type chipset and set PIRQx linies in interrupt router. Now this part supports only CS5530/5536 interrupt routers. Irq routing functionality is include through macro PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020 http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. -- Nikolay

4 6

Re: [coreboot] #7: Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards
by coreboot 01 Apr '08

01 Apr '08

#7: Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards -------------------------+-------------------------------------------------- Reporter: uwe | Owner: uwe Type: defect | Status: new Priority: critical | Milestone: Component: flashrom | Version: Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by uwe): * patchstatus: => there is no patch * version: v2 => * summary: flashrom: Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards => Doesn't seem to be able to write on ICH-2 (maybe other ICH-x) mainboards -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/7#comment:4> coreboot <http://www.coreboot.org/>

2 1

Re: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
by coreboot 01 Apr '08

01 Apr '08

#76: LinuxBIOS messages should be accessible in dmesg ----------------------------+----------------------------------------------- Reporter: stepan | Owner: rminnich Type: enhancement | Status: new Priority: major | Milestone: Setting up LinuxBIOS v3 Component: coreboot | Version: v3 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch ----------------------------+----------------------------------------------- Changes (by hailfinger): * type: defect => enhancement Comment: I implemented the buffer in r590, but the payload has to know a hardcoded buffer address to read the message buffer. There is no explicit mechanism for passing the log buffer address to a payload. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:2> coreboot <http://www.coreboot.org/>

1 0

r3209 - trunk/coreboot-v2/src/southbridge/intel/i3100
by svn＠coreboot.org 01 Apr '08

01 Apr '08

Author: eswierk Date: 2008-04-01 19:14:57 +0200 (Tue, 01 Apr 2008) New Revision: 3209 Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c Log: Setting an integrated southbridge device (like SATA or USB2.0) to "off" in Config.lb should cause the PCI device not to respond to configuration requests. Replace the existing code that I naively copied from esb6300 with something that actually works on the 3100. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c 2008-04-01 17:05:22 UTC (rev 3208) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100.c 2008-04-01 17:14:57 UTC (rev 3209) @@ -18,52 +18,45 @@ * */ -/* This code is based on src/southbridge/intel/esb6300/esb6300.c */ - #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include "i3100.h" void i3100_enable(device_t dev) { device_t lpc_dev; - u32 index = 0; - u16 reg_old, reg; + u8 func; + volatile u32 *disable; - /* See if we are behind the i3100 PCI bridge */ - lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if ((dev->path.u.pci.devfn & 0xf8) == 0xf8) { - index = dev->path.u.pci.devfn & 7; - } - else if ((dev->path.u.pci.devfn & 0xf8) == 0xe8) { - index = (dev->path.u.pci.devfn & 7) + 8; - } - if ((!lpc_dev) || (index >= 16) || ((1 << index) & 0x3091)) { + if (dev->enabled) return; - } - if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || - (lpc_dev->device != PCI_DEVICE_ID_INTEL_3100_LPC)) { - u32 id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | - (PCI_DEVICE_ID_INTEL_3100_LPC << 16))) { - return; - } - } - reg = reg_old = pci_read_config16(lpc_dev, 0xf2); - reg &= ~(1 << index); - if (!dev->enabled) { - reg |= (1 << index); + /* + * To disable an integrated southbridge device, set the corresponding + * flag in the Function Disable register. + */ + + /* Temporarily enable the root complex register block at 0xa0000000. */ + lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0)); + pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0)); + disable = (volatile u32 *) 0xa0003418; + func = PCI_FUNC(dev->path.u.pci.devfn); + switch (PCI_SLOT(dev->path.u.pci.devfn)) { + case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */ + *disable |= (1 << (func == 0x0 ? 14 : func)); + break; + case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */ + *disable |= (1 << (func + 8)); + break; + case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */ + *disable |= (1 << (func + 16)); + break; } - if (reg != reg_old) { - pci_write_config16(lpc_dev, 0xf2, reg); - } + /* Disable the root complex register block. */ + pci_write_config32(lpc_dev, 0xf0, 0); } struct chip_operations southbridge_intel_i3100_ops = { CHIP_NAME("Intel 3100 Southbridge") - .enable_dev = i3100_enable, }; Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-04-01 17:05:22 UTC (rev 3208) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_sata.c 2008-04-01 17:14:57 UTC (rev 3209) @@ -72,18 +72,19 @@ .enable_resources = pci_dev_enable_resources, .init = sata_init, .scan_bus = 0, + .enable = i3100_enable, .ops_pci = &lops_pci, }; static struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SATA, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_SATA, }; static struct pci_driver sata_driver_nr __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SATA_R, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_3100_SATA_R, };

1 0

Re: [coreboot] #76: LinuxBIOS messages should be accessible in dmesg
by coreboot 01 Apr '08

01 Apr '08

#76: LinuxBIOS messages should be accessible in dmesg -------------------------+-------------------------------------------------- Reporter: stepan | Owner: rminnich Type: defect | Status: new Priority: major | Milestone: Setting up LinuxBIOS v3 Component: coreboot | Version: v3 Resolution: | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Comment (by uwe): Untested yet by me, but it looks like this is (partly?) implemented in r590. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/76#comment:1> coreboot <http://www.coreboot.org/>

2 1

r3208 - trunk/coreboot-v2/src/southbridge/intel
by svn＠coreboot.org 01 Apr '08

01 Apr '08

Author: eswierk Date: 2008-04-01 19:05:22 +0200 (Tue, 01 Apr 2008) New Revision: 3208 Removed: trunk/coreboot-v2/src/southbridge/intel/i82801db/ Log: Remove i82801DB files that I meant to delete in r3206. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Ed Swierk <eswierk(a)arastra.com>

1 0

Re: [coreboot] r3206 - trunk/coreboot-v2/src/southbridge/intel/i82801db
by Uwe Hermann 01 Apr '08

01 Apr '08

On Tue, Apr 01, 2008 at 04:42:52AM +0200, svn(a)coreboot.org wrote: > Author: eswierk > Date: 2008-04-01 04:42:52 +0200 (Tue, 01 Apr 2008) > New Revision: 3206 > > Removed: > trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb > trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h > trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c > trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c > trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c > trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c This looks incomplete, there are a lot of files left: i82801db_ehci.c i82801db.h i82801db_ide.c i82801db_lpc.c i82801db_pci.c i82801db_reset.c i82801db_smbus.c i82801db_smbus.h i82801db_uhci.c i82801db_watchdog.c Unless I'm missing something, please do another 'svn rm' on the whole directory, i.e. $ svn rm src/southbridge/intel/i82801db $ svn ci src/southbridge/intel/i82801db with the same Signed-off-by's and Acked-by's. Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

Issue tracker -- list issues by component
by Uwe Hermann 01 Apr '08

01 Apr '08

Hi, I've added a new "report" to trac which allows you to view issues sorted by component: http://tracker.coreboot.org/trac/coreboot/report/10 I've also re-assigned a few issues to their proper component as good as I could, but some may still need to be re-arranged. There are now components for pretty much all relevant parts of the coreboot "family", including filo, grub2, coreinfo, libpayload, coreboot (v2 or v3), mkelfimage, flashrom, superiotool, wiki/website/tracker, toolchain etc. If you think a component is missing, please let me know so I can add it. Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2008