coreboot March 2008

coreboot@coreboot.org

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382 discussions

r3201 - trunk/payloads/libpayload
by svn＠coreboot.org 31 Mar '08

31 Mar '08

Author: uwe Date: 2008-03-31 17:21:24 +0200 (Mon, 31 Mar 2008) New Revision: 3201 Modified: trunk/payloads/libpayload/Config.in Log: Whitespace fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/Config.in =================================================================== --- trunk/payloads/libpayload/Config.in 2008-03-31 15:18:56 UTC (rev 3200) +++ trunk/payloads/libpayload/Config.in 2008-03-31 15:21:24 UTC (rev 3201) @@ -30,25 +30,25 @@ mainmenu "Libpayload Configuration" config HAVE_DOT_CONFIG - bool - default y + bool + default y # When (if) we support multiple architectures, this will become an option. config TARGET_I386 - bool - default y + bool + default y menu "Output Options" - + config SERIAL_CONSOLE - bool "See output on the serial port console" - default y + bool "See output on the serial port console" + default y config SERIAL_IOBASE - hex "I/O base for the serial port (default 0x3f8)" - depends SERIAL_CONSOLE - default 0x3f8 - + hex "I/O base for the serial port (default 0x3f8)" + depends SERIAL_CONSOLE + default 0x3f8 + config SERIAL_SET_SPEED bool "Override the serial console baud rate" default n @@ -59,25 +59,25 @@ depends SERIAL_SET_SPEED default 115200 -config VGA_CONSOLE - bool "See output on a VGA console" - default y +config VGA_CONSOLE + bool "See output on a VGA console" + default y config PC_KEYBOARD - bool "Allow input from a PC keyboard" - depends VGA_CONSOLE - default y + bool "Allow input from a PC keyboard" + depends VGA_CONSOLE + default y config NVRAM - bool "Support for reading/writing NVRAM bytes" - default y + bool "Support for reading/writing NVRAM bytes" + default y endmenu menu "Build Options" config TINYCURSES - bool "Enable tinycurses support" - default y + bool "Enable tinycurses support" + default y endmenu

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r3200 - in trunk/payloads/libpayload: drivers include
by svn＠coreboot.org 31 Mar '08

31 Mar '08

Author: uwe Date: 2008-03-31 17:18:56 +0200 (Mon, 31 Mar 2008) New Revision: 3200 Added: trunk/payloads/libpayload/drivers/nvram.c Removed: trunk/payloads/libpayload/drivers/cmos.c Modified: trunk/payloads/libpayload/drivers/Makefile.inc trunk/payloads/libpayload/include/libpayload.h Log: Rename drivers/cmos.c to drivers/nvram.c (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/drivers/Makefile.inc =================================================================== --- trunk/payloads/libpayload/drivers/Makefile.inc 2008-03-31 15:17:39 UTC (rev 3199) +++ trunk/payloads/libpayload/drivers/Makefile.inc 2008-03-31 15:18:56 UTC (rev 3200) @@ -31,4 +31,4 @@ TARGETS-$(CONFIG_SERIAL_CONSOLE) += drivers/serial.o TARGETS-$(CONFIG_VGA_CONSOLE) += drivers/vga.o TARGETS-$(CONFIG_PC_KEYBOARD) += drivers/keyboard.o -TARGETS-$(CONFIG_NVRAM) += drivers/cmos.o +TARGETS-$(CONFIG_NVRAM) += drivers/nvram.o Deleted: trunk/payloads/libpayload/drivers/cmos.c =================================================================== --- trunk/payloads/libpayload/drivers/cmos.c 2008-03-31 15:17:39 UTC (rev 3199) +++ trunk/payloads/libpayload/drivers/cmos.c 2008-03-31 15:18:56 UTC (rev 3200) @@ -1,69 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Datasheet: - * - Name: MC146818: Real-time Clock Plus RAM (RTC) - * - PDF: http://www.freescale.com/files/microcontrollers/doc/data_sheet/MC146818.pdf - * - Order number: MC146818/D - */ - -/* - * See also: - * http://bochs.sourceforge.net/techspec/CMOS-reference.txt - * http://www.bioscentral.com/misc/cmosmap.htm - */ - -#include <libpayload.h> - -#define RTC_PORT 0x70 - -/** - * Read a byte from the specified NVRAM address. - * - * @param addr The NVRAM address to read a byte from. - * @return The byte at the given NVRAM address. - */ -u8 nvram_read(u8 addr) -{ - outb(addr, RTC_PORT); - return inb(RTC_PORT + 1); -} - -/** - * Write a byte to the specified NVRAM address. - * - * @param val The byte to write to NVRAM. - * @param addr The NVRAM address to write to. - */ -void nvram_write(u8 val, u8 addr) -{ - outb(addr, RTC_PORT); - outb(val, RTC_PORT + 1); -} Copied: trunk/payloads/libpayload/drivers/nvram.c (from rev 3199, trunk/payloads/libpayload/drivers/cmos.c) =================================================================== --- trunk/payloads/libpayload/drivers/nvram.c (rev 0) +++ trunk/payloads/libpayload/drivers/nvram.c 2008-03-31 15:18:56 UTC (rev 3200) @@ -0,0 +1,69 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Datasheet: + * - Name: MC146818: Real-time Clock Plus RAM (RTC) + * - PDF: http://www.freescale.com/files/microcontrollers/doc/data_sheet/MC146818.pdf + * - Order number: MC146818/D + */ + +/* + * See also: + * http://bochs.sourceforge.net/techspec/CMOS-reference.txt + * http://www.bioscentral.com/misc/cmosmap.htm + */ + +#include <libpayload.h> + +#define RTC_PORT 0x70 + +/** + * Read a byte from the specified NVRAM address. + * + * @param addr The NVRAM address to read a byte from. + * @return The byte at the given NVRAM address. + */ +u8 nvram_read(u8 addr) +{ + outb(addr, RTC_PORT); + return inb(RTC_PORT + 1); +} + +/** + * Write a byte to the specified NVRAM address. + * + * @param val The byte to write to NVRAM. + * @param addr The NVRAM address to write to. + */ +void nvram_write(u8 val, u8 addr) +{ + outb(addr, RTC_PORT); + outb(val, RTC_PORT + 1); +} Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-03-31 15:17:39 UTC (rev 3199) +++ trunk/payloads/libpayload/include/libpayload.h 2008-03-31 15:18:56 UTC (rev 3200) @@ -49,7 +49,7 @@ #define NVRAM_RTC_MONTH 8 #define NVRAM_RTC_YEAR 9 -/* drivers/cmos.c */ +/* drivers/nvram.c */ u8 nvram_read(u8 addr); void nvram_write(u8 val, u8 addr);

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r3199 - in trunk/payloads/libpayload: . drivers include
by svn＠coreboot.org 31 Mar '08

31 Mar '08

Author: uwe Date: 2008-03-31 17:17:39 +0200 (Mon, 31 Mar 2008) New Revision: 3199 Modified: trunk/payloads/libpayload/Config.in trunk/payloads/libpayload/drivers/Makefile.inc trunk/payloads/libpayload/drivers/cmos.c trunk/payloads/libpayload/include/libpayload.h Log: Due to popular demand, rename "CMOS" to "NVRAM" (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/Config.in =================================================================== --- trunk/payloads/libpayload/Config.in 2008-03-30 11:31:15 UTC (rev 3198) +++ trunk/payloads/libpayload/Config.in 2008-03-31 15:17:39 UTC (rev 3199) @@ -68,8 +68,8 @@ depends VGA_CONSOLE default y -config CMOS - bool "Support for reading/writing CMOS bytes" +config NVRAM + bool "Support for reading/writing NVRAM bytes" default y endmenu Modified: trunk/payloads/libpayload/drivers/Makefile.inc =================================================================== --- trunk/payloads/libpayload/drivers/Makefile.inc 2008-03-30 11:31:15 UTC (rev 3198) +++ trunk/payloads/libpayload/drivers/Makefile.inc 2008-03-31 15:17:39 UTC (rev 3199) @@ -31,4 +31,4 @@ TARGETS-$(CONFIG_SERIAL_CONSOLE) += drivers/serial.o TARGETS-$(CONFIG_VGA_CONSOLE) += drivers/vga.o TARGETS-$(CONFIG_PC_KEYBOARD) += drivers/keyboard.o -TARGETS-$(CONFIG_CMOS) += drivers/cmos.o +TARGETS-$(CONFIG_NVRAM) += drivers/cmos.o Modified: trunk/payloads/libpayload/drivers/cmos.c =================================================================== --- trunk/payloads/libpayload/drivers/cmos.c 2008-03-30 11:31:15 UTC (rev 3198) +++ trunk/payloads/libpayload/drivers/cmos.c 2008-03-31 15:17:39 UTC (rev 3199) @@ -45,24 +45,24 @@ #define RTC_PORT 0x70 /** - * Read a byte from the specified CMOS address. + * Read a byte from the specified NVRAM address. * - * @param addr The CMOS address to read a byte from. - * @return The byte at the given CMOS address. + * @param addr The NVRAM address to read a byte from. + * @return The byte at the given NVRAM address. */ -u8 cmos_read(u8 addr) +u8 nvram_read(u8 addr) { outb(addr, RTC_PORT); return inb(RTC_PORT + 1); } /** - * Write a byte to the specified CMOS address. + * Write a byte to the specified NVRAM address. * - * @param val The byte to write to CMOS. - * @param addr The CMOS address to write to. + * @param val The byte to write to NVRAM. + * @param addr The NVRAM address to write to. */ -void cmos_write(u8 val, u8 addr) +void nvram_write(u8 val, u8 addr) { outb(addr, RTC_PORT); outb(val, RTC_PORT + 1); Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-03-30 11:31:15 UTC (rev 3198) +++ trunk/payloads/libpayload/include/libpayload.h 2008-03-31 15:17:39 UTC (rev 3199) @@ -41,17 +41,17 @@ #define MAX(a,b) ((a) > (b) ? (a) : (b)) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -/* Some CMOS byte definitions */ -#define CMOS_RTC_SECONDS 0 -#define CMOS_RTC_MINUTES 2 -#define CMOS_RTC_HOURS 4 -#define CMOS_RTC_DAY 7 -#define CMOS_RTC_MONTH 8 -#define CMOS_RTC_YEAR 9 +/* Some NVRAM byte definitions */ +#define NVRAM_RTC_SECONDS 0 +#define NVRAM_RTC_MINUTES 2 +#define NVRAM_RTC_HOURS 4 +#define NVRAM_RTC_DAY 7 +#define NVRAM_RTC_MONTH 8 +#define NVRAM_RTC_YEAR 9 /* drivers/cmos.c */ -u8 cmos_read(u8 addr); -void cmos_write(u8 val, u8 addr); +u8 nvram_read(u8 addr); +void nvram_write(u8 val, u8 addr); /* drivers/keyboard.c */ int keyboard_havechar(void);

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Re: [coreboot] #15: fix abuild for all boards that use the "three images solution
by coreboot 30 Mar '08

30 Mar '08

#15: fix abuild for all boards that use the "three images solution --------------------------+------------------------------------------------- Reporter: anonymous | Owner: yhlu Type: defect | Status: reopened Priority: major | Milestone: Component: code | Version: v2 Resolution: | Keywords: abuild Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- Changes (by uwe): * status: closed => reopened * resolution: fixed => Comment: Reopening. While all boards build fine with abuild currently, not all of those which have a "three-images-solution" (failover+fallback+normal) actually do build all of the sub-images, which means that at least the auto-generated images at qa.coreboot.org are broken. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/15#comment:4> coreboot <http://www.coreboot.org/>

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r3198 - in trunk/coreboot-v2/src: mainboard/intel/mtarvon southbridge/intel/i3100
by svn＠coreboot.org 30 Mar '08

30 Mar '08

Author: uwe Date: 2008-03-30 13:31:15 +0200 (Sun, 30 Mar 2008) New Revision: 3198 Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c Log: Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots the system automatically unless software resets the timer periodically. The extra reboot extends boot time by several seconds. The attached patch adds a function to the Intel 3100 southbridge code that halts the TCO timer, thus preventing this extra reboot, and calls the function early in the boot process on the Mt. Arvon board. It also fixes a bug in the LPC device initialization -- the ACPI BAR enable flag is bit 7, not bit 4. Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c 2008-03-29 17:24:58 UTC (rev 3197) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/auto.c 2008-03-30 11:31:15 UTC (rev 3198) @@ -90,6 +90,9 @@ uart_init(); console_init(); + /* Prevent the TCO timer from rebooting us */ + i3100_halt_tco_timer(); + /* Halt if there was a built in self test failure */ report_bist_failure(bist); Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2008-03-29 17:24:58 UTC (rev 3197) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2008-03-30 11:31:15 UTC (rev 3198) @@ -30,3 +30,23 @@ /* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x82, 0x340f); } + +static void i3100_halt_tco_timer(void) +{ + device_t dev; + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_3100_LPC), 0); + if (dev == PCI_DEV_INVALID) { + die("LPC bridge not found\r\n"); + } + + /* Temporarily enable the ACPI I/O range at 0x4000 */ + pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); + pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); + + /* Halt the TCO timer, preventing SMI and automatic reboot */ + outw(inw(0x4068) | (1 << 11), 0x4068); + + /* Disable the ACPI I/O range */ + pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); +} Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2008-03-29 17:24:58 UTC (rev 3197) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_lpc.c 2008-03-30 11:31:15 UTC (rev 3198) @@ -276,7 +276,7 @@ /* Enable the ACPI bar */ acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 4); + acpi_cntl |= (1 << 7); pci_write_config8(dev, 0x44, acpi_cntl); /* Enable the GPIO bar */

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buildrom: optional delay to kexec fails
by Andreas B. Mundt 30 Mar '08

30 Mar '08

Hi everybody, in revision 125 of buildrom an optional delay before the LAB environment kexecs the on-disk kernel has been introduced. For me this does not work. There is neither a delay nor can I enter the busybox environment by pressing return. After showing the delay-press-key-message, the on-disk kernel is booted immediately. I use a 64 bit kernel in LAB. (The default one with amd64 configuration.) What can go wrong? Regards, Andi

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PCI setup documentation
by Carl-Daniel Hailfinger 30 Mar '08

30 Mar '08

The Linux-MIPS people have a great document explaining PCI initialization which should probably be added to our wiki and/or porting guides. http://www.linux-mips.org/wiki/PCI_Subsystem Any ideas where it would fit best? Regards, Carl-Daniel

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Re: [coreboot] [LinuxBIOS] Televideo TC7020 successfully booted with LinuxBiosV2
by Uwe Hermann 29 Mar '08

29 Mar '08

Hi, On Fri, Mar 28, 2008 at 04:11:22PM -0400, Knechel, Andrew wrote: > My name is Andrew Knechel. We are trying to use Televideo 7020's as > linux thin clients and I saw a posting that you were able to do > something similar. Can you provide me with any details that would be > useful? The code for the TC7020 is committed in svn now, see http://www.coreboot.org/TeleVideo_TC7020_Build_Tutorial for a quick HOWTO for compiling coreboot for this board. You can then use flashrom to flash the image onto an empty ROM chip (I would not recommend overwriting your original chip -- keep it in a safe place as backup). http://www.coreboot.org/Flashrom Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] [PATCH] TeleVideo TC7020 support (2nd try)
by Kenji Noguchi 29 Mar '08

29 Mar '08

Hi Uwe, Thanks for the review. I have updated the patch based on your review. The new patch needs Nikolay's CS5530/CS5536 PIRQ patch. I cannot run superiotool with the factory BIOS because the BIOS is WinCE. WakeOnLan doesn't work out of the box. The original thin-clients manager is able to on/off WOL feature as far as I remember. It's a PC97317 board. Strange, the superiotool r2992 says "No Super I/O found" NIC is soldered on the motherboard, and it resides on pci 15.0. Fixed the config entry. Floppy connector may be available in one of the pin headers but I can't confirm. I leave it off to be conservative. COM2 is a regular DB9 serial. Fixed the comment. irq_tables.c in the previous patch was re-generated by getpir tool, and manually edited. However I had no way of testing it. Linux kernel won't read it unless patched, you know. Anyway I reworked on this file using Nikolay's irq patch. As for MiniPCI slot there are INTA and INTB by definition of the MiniPCI. lspci output had no 14.0 because it's a slot. I installd a WiFi card to the MiniPCI slot(PCI 14.0) for testing. It got IRQ9 and worked great! Regards, Kenji Noguchi

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[PATCH] [buildrom] update to latest filo rev, remove manual sata spinup patch
by Ward Vandewege 29 Mar '08

29 Mar '08

-- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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coreboot March 2008