coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

Re: [coreboot] flashrom and PM49FL004/2
by Nikolay Petukhov 17 May '08

17 May '08

Hi. Patch[] already old. Try this patch. 2008/3/18, malatesh kamatad <malateshkamat(a)gmail.com>: > Hi ..... > > We are working on Coreboot we are trying to flash on the > PM49fl004/SST49lf004B > > but the flashrom has problems with the write and erase operation. > > We have MSI Neo and MSI K9N Ultra mother boards with socketed bios. > > > So we are following the procedure what you have given in the > mailing list (patch) , > > After compiling we are getting the error as bellow > > [malatesh@turtle22 flashrom]$ make > > Checking for pciutils and zlib... found. > gcc -o flashrom chipset_enable.o board_enable.o udelay.o jedec.o > sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o > 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o sst_fwhub.o > layout.o cbtable.o flashchips.o flashrom.o sharplhf00l04.o w29ee011.o spi.o > -lpci -lz -static > sst_fwhub.o: In function `probe_sst_fwhub': > sst_fwhub.c:(.text+0x21a): undefined reference to `probe_49fl00x' > flashchips.o:(.data+0x644): undefined reference to `probe_49fl00x' > flashchips.o:(.data+0x648): undefined reference to `erase_49fl00x' > flashchips.o:(.data+0x64c): undefined reference to `write_49fl00x' > flashchips.o:(.data+0x670): undefined reference to `probe_49fl00x' > flashchips.o:(.data+0x674): undefined reference to `erase_49fl00x' > flashchips.o:(.data+0x678): undefined reference to `write_49fl00x' > collect2: ld returned 1 exit status > make: *** [flashrom] Error 1 > > > I think we have down a mistake in this step , > > we are unable to understand the step i.e > > diff -Nru flashrom/flash.h flashrom-pm49fl00x/flash.h > > --- flashrom/flash.h 2008-02-07 03:07:58.000000000 +0500 > > +++ flashrom-pm49fl00x/flash.h 2008-03-11 13:38:25.000000000 > +0500 > > @@ -373,9 +373,9 @@ > please guide us............. > > with regards , > Malatesh. > > > > > > > > > > > > > -- Nikolay

5 10

[PATCH] flashrom: ST M25P40 bug?
by Fredrik Tolf 17 May '08

17 May '08

I don't know if this is a bug, or if there are somehow two completely different versions of the ST M25P40 SPI chip. I just tried to burn such a chip with flashrom, but it wouldn't detect it at all, so I checked the datasheet for it, and it turned out that the probe was completely different from what one would think, reading flashrom's source. It seems that the M25P40 doesn't use the RDID command to send its ID, but rather a "RES" (Read Electronic Signature) command instead, which returns just one byte. I added support for it, and then it worked perfectly for me. I'm attaching my patch to fix the problem. I would imagine that the other M25Pxx chips would be affected by the same problem, but since I can neither verify nor test what IDs they would have, they are excluded from my patch. Fredrik Tolf

4 17

[LinuxBIOS] flashrom support for AMD Geode CS5536
by Lane Brooks 16 May '08

16 May '08

Attached is a patch that enables AMD Geode CS5536 chipset support. I have tested it successfully on a MSM800 board from digital logic. It does, however, have a few issues that I would like some feedback on. In my discussions with Marc Jones, Geode systems write protect the BIOS via RCONFs (cache settings similar to MTRRs). Unlocking requires changing MSR 0x1808 top byte to 0x22. Reading and writing to the msr, however, requires instrucitons rdmsr/wrmsr, which are ring0 privileged instructions so only the kernel can do the read/write. So my patch uses the msr kernel module to access these instructions from user space using the /dev/cpu/0/msr device. My questions are: - I do not think this is portable beyond linux. Is that an issue? - My code assumes the msr kernel module is already loaded. Is there a way to force a kernel module to load from the C code? My code does die gracefully with a message reminding them to load the kernel module if things fail. - It seems like there should be a way to revert the msr back after flashing is completed to put the bios back in write protect mode. Is there a cleanup mechanism available? Something like disable_flash... Thanks, Lane Brooks

8 17

[LinuxBIOS] flashrom on ga 2761gxdk
by ron minnich 16 May '08

16 May '08

It now finds the part, and gets ready to program it, but exits instantly without doing anything. I think this is the culprit: void generic_spi_page_program(int block, uint8_t *buf, uint8_t *bios) { if (it8716f_flashport) it8716f_spi_page_program(block, buf, bios); } i.e. the flashport is not set. So, before I dig too far into this, is there some simple thing I should look at to get flashrom working on this board? Also, seems to me it's a pretty serious error if this can not be determined, ... anyone mind if I add an error message? right now it exits with no error, having done no work :-) thanks ron

5 28

[PATCH] v3: fix bugs in Geode LX RAMinit
by Carl-Daniel Hailfinger 20 Apr '08

20 Apr '08

Marc? It would be nice if you could read through the code and verify the things I did. northbridge/amd/geodelx/raminit.c:auto_size_dimm() checks for the mathematically impossible condition of a value being above and below the specified range at the same time. Change it to check for out-of-range. arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it will keep going and mess up DRAM timings. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-geodelx_dram_fixes/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3-geodelx_dram_fixes/northbridge/amd/geodelx/raminit.c (Revision 638) +++ LinuxBIOSv3-geodelx_dram_fixes/northbridge/amd/geodelx/raminit.c (Arbeitskopie) @@ -79,7 +79,7 @@ /* EEPROM byte usage: (5) Number of DIMM Banks */ banner(BIOS_DEBUG, "MODBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); - if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { + if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) { printk(BIOS_EMERG, "Number of module banks not compatible\n"); post_code(ERROR_BANK_SET); hlt(); @@ -90,7 +90,7 @@ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ banner(BIOS_DEBUG, "FIELDBANKS"); spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); - if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { + if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) { printk(BIOS_EMERG, "Number of device banks not compatible\n"); post_code(ERROR_BANK_SET); hlt(); Index: LinuxBIOSv3-geodelx_dram_fixes/arch/x86/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3-geodelx_dram_fixes/arch/x86/geodelx/geodelx.c (Revision 638) +++ LinuxBIOSv3-geodelx_dram_fixes/arch/x86/geodelx/geodelx.c (Arbeitskopie) @@ -386,6 +386,7 @@ msr.hi |= delay_control_table[i].fast_hi; msr.lo |= delay_control_table[i].fast_low; } + break; } } wrmsr(GLCP_DELAY_CONTROLS, msr); -- http://www.hailfinger.org/

6 11

[PATCH] Halt TCO timer on Intel 3100 chipset
by Ed Swierk 16 Apr '08

16 Apr '08

Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots the system automatically unless software resets the timer periodically. The extra reboot extends boot time by several seconds. The attached patch adds a function to the Intel 3100 southbridge code that halts the TCO timer, thus preventing this extra reboot, and calls the function early in the boot process on the Mt. Arvon board. It also fixes a bug in the LPC device initialization--the ACPI BAR enable flag is bit 7, not bit 4. Signed-off-by: Ed Swierk <eswierk(a)arastra.com>

6 20

[PATCH] CN10K patch, FILO ide discover patch.
by Urbez Santana Roma 15 Apr '08

15 Apr '08

Note: for install this patch, you must download the last coreboot SVN, and install first the patch posted by Corey Osgood, that includes CN700/C7 and jetway mainboard. The filo patch is for correct a problem with FILO when tries to find the IDE disk, if more that one IDE interface is on, and no all IDE's are in native Mode. The count of compatibility interfaces are wrong, and not finds the interface that is marked as a IDE 0x0101 or SATA 0x0180 and not all are native, the search of the io base and control, are wrong. If this is not correct sorry :))) If in VT8237R have SATA as an 0101 and the IDE too 0101 class, with this patch, works, because counts corectly the unique non native interface IDE, as the first. NOTE1: in the epia-cn/Config.lb the IDE and SATA are enabled. NOTE2: in epia-cn/auto.c the values of PCI_DEV(0,0x11,0) 0x50 and 0x51 are different, for have IDE and SATA enableds at function enable_mainboard_devices NOTE3: Here is a file base.c that haves a udelay with use of rtdsc NOTE4: another function via_cn_fixup, fixes the use of PCI devices access to the memory. Must be improved, and not use a fixed value. NOTE5: have a change in cn700/raminit.c for configure in CN the memory. NOTE6: vt8237r configures the SATA device as an IDE class 0x0101 must be 0x0180????? Urbez Santana.

3 2

recent mainboard with coreboot support and certain requirements
by Paul Menzel 09 Apr '08

09 Apr '08

Dear list readers, sorry for bothering you. I want to buy a new mainboard with the following features. 1. It has to be supported by coreboot. 2. I want to have a board with onboard graphics, since I do not play any games. I hope to save power this way. 3. Probably it should support a processor with at least 2 GHz. 4. Firewire would be nice. (I want to maybe do some video editing once every three months.) Of course I read [1]. It looks like I have to make a decision between onboard graphic and firewire – but 2. has higher priority (or is my assumption regarding power consumption wrong). So this is my result. - GIGABYTE_GA-2761GXDK [2] (the link in the wiki on the board [3] somehow leads to [4]) Unfortunately this board seems not to be available in Germany/Europe(?). Therefore I weakened requirement 1. a little bit to 1‘. 1‘. It has or will have coreboot support. That is why I am planning to buy the ASUS M2V-MX SE [5] having read the announcement from Rudolf Marek [6]. Any thoughts/suggestions from you to my decision/requirements. Thanks a lot for your time. Paul [1] http://www.coreboot.org/Supported_Motherboards [2] http://www.coreboot.org/GIGABYTE_GA-2761GXDK_Build_Tutorial [3] http://www.rssfeedbus.com/index.php?showtopic=1515 [4] http://www.modolog.com/ [5] http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=324&l4=0&model=1807&mod… [6] http://www.coreboot.org/pipermail/coreboot/2008-March/032582.html

5 9

[PATCH] libpayload: CMOS / BCD functions
by Uwe Hermann 04 Apr '08

04 Apr '08

See patch. I'll follow-up with a coreinfo patch to dump the whole CMOS array. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

7 12

lzma v3 fails to compile under gcc-4.3.x
by Devils-Hawk 02 Apr '08

02 Apr '08

compiling with gcc-4.3.0 will result in the following or similar: > error: 'memcpy' is not a member of 'std' because gcc-4.3.0 does not include certain standard C-headers in C++ programs by default anymore. Attached simple stupid patch should fix that. regards, devh

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coreboot March 2008