coreboot March 2008

coreboot@coreboot.org

75 participants
382 discussions

[PATCH] Merge lib/ramtest.c into lib/ram.c
by Uwe Hermann 18 Mar '08

18 Mar '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

6 22

[PATCH] flashrom support for W39V080FA and Kontron 986LCD-M
by Stefan Reinauer 18 Mar '08

18 Mar '08

See patch. This one was particularly tricky as the Kontron board uses all kinds of flash protection methods. Also the Winbond W39V080FA(P)(Z) is very timing critical, so it won't work with our existing jedec functions. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 3

r3166 - trunk/util/flashrom
by svn＠coreboot.org 18 Mar '08

18 Mar '08

Author: stepan Date: 2008-03-18 01:36:18 +0100 (Tue, 18 Mar 2008) New Revision: 3166 Added: trunk/util/flashrom/w39v080fa.c Log: oops. forgot to add the file. Support for the Winbond W39V080FA series of chips. Support for flashing on the Kontron 986LCD-M board. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/util/flashrom/w39v080fa.c =================================================================== --- trunk/util/flashrom/w39v080fa.c (rev 0) +++ trunk/util/flashrom/w39v080fa.c 2008-03-18 00:36:18 UTC (rev 3166) @@ -0,0 +1,206 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include "flash.h" + +int probe_winbond_fwhub(struct flashchip *flash) +{ + volatile uint8_t *bios = flash->virtual_memory; + uint8_t vid, did; + + /* Product Identification Entry */ + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + *(volatile uint8_t *)(bios + 0x5555) = 0x90; + myusec_delay(10); + + /* Read product ID */ + vid = *(volatile uint8_t *)bios; + did = *(volatile uint8_t *)(bios + 0x01); + + /* Product Identifixation Exit */ + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + myusec_delay(10); + + printf_debug("%s: vid 0x%x, did 0x%x\n", __FUNCTION__, vid, did); + + if (vid != flash->manufacture_id || did != flash->model_id) + return 0; + + map_flash_registers(flash); + + return 1; +} + +static int unlock_block_winbond_fwhub(struct flashchip *flash, int offset) +{ + volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2; + uint8_t locking; + + printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, *wrprotect); + + locking = *wrprotect; + switch (locking & 0x7 ) { + case 0: + printf_debug("Full Access.\n"); + return 0; + case 1: + printf_debug("Write Lock (Default State).\n"); + *wrprotect = 0; + return 0; + case 2: + printf_debug("Locked Open (Full Access, Lock Down).\n"); + return 0; + case 3: + fprintf(stderr, "Error: Write Lock, Locked Down.\n"); + return -1; + case 4: + printf_debug("Read Lock.\n"); + *wrprotect = 0; + return 0; + case 5: + printf_debug("Read/Write Lock.\n"); + *wrprotect = 0; + return 0; + case 6: + fprintf(stderr, "Error: Read Lock, Locked Down.\n"); + return -1; + case 7: + fprintf(stderr, "Error: Read/Write Lock, Locked Down.\n"); + return -1; + } + + /* We will never reach this point, but GCC doesn't know */ + return -1; +} + +int unlock_winbond_fwhub(struct flashchip *flash) +{ + int i, total_size = flash->total_size * 1024; + volatile uint8_t *bios = flash->virtual_memory; + uint8_t locking; + + /* Are there any hardware restrictions that we can't overcome? + * If flashrom fail here, someone's got to check all those GPIOs. + */ + + /* Product Identification Entry */ + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + *(volatile uint8_t *)(bios + 0x5555) = 0x90; + myusec_delay(10); + + /* Read Hardware Lock Bits */ + locking = *(volatile uint8_t *)(bios + 0xffff2); + + /* Product Identification Exit */ + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + myusec_delay(10); + + printf_debug("Lockout bits:\n"); + + if (locking & (1<<2)) + fprintf(stderr, "Error: hardware bootblock locking (#TBL).\n"); + else + printf_debug("No hardware bootblock locking (good!)\n"); + + if (locking & (1<<3)) + fprintf(stderr, "Error: hardware block locking (#WP).\n"); + else + printf_debug("No hardware block locking (good!)\n"); + + if (locking & ((1<<2) | (1<<3))) + return -1; + + /* Unlock the complete chip */ + for (i = 0; i < total_size; i += flash->page_size) + if (unlock_block_winbond_fwhub(flash, i)) + return -1; + + return 0; +} + +static int erase_sector_winbond_fwhub(volatile uint8_t *bios, unsigned int sector) +{ + /* Remember: too much sleep can waste your day. */ + + printf("0x%08x\b\b\b\b\b\b\b\b\b\b", sector); + + /* Sector Erase */ + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + *(volatile uint8_t *)(bios + 0x5555) = 0x80; + + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + *(volatile uint8_t *)(bios + sector) = 0x30; + + /* wait for Toggle bit ready */ + toggle_ready_jedec(bios); + + return 0; +} + +int erase_winbond_fwhub(struct flashchip *flash) +{ + int i, total_size = flash->total_size * 1024; + volatile uint8_t *bios = flash->virtual_memory; + + printf("Erasing: "); + + for (i = 0; i < total_size; i += flash->page_size) + erase_sector_winbond_fwhub(bios, i); + + printf("\n"); + + for (i = 0; i < total_size; i++) { + if (bios[i] != 0xff) { + fprintf(stderr, "Error: Flash chip erase failed at 0x%08x(0x%02x)\n", i, bios[i]); + return -1; + } + } + + return 0; +} + +int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf) +{ + int i; + int total_size = flash->total_size * 1024; + volatile uint8_t *bios = flash->virtual_memory; + + if (erase_winbond_fwhub(flash)) + return -1; + + printf("Programming: "); + for (i = 0; i < total_size; i+=flash->page_size) { + printf("0x%08x\b\b\b\b\b\b\b\b\b\b", i); + write_sector_jedec(bios, buf + i, bios + i, flash->page_size); + } + printf("\n"); + + return 0; +} +

1 0

r3165 - trunk/util/flashrom
by svn＠coreboot.org 17 Mar '08

17 Mar '08

Author: stepan Date: 2008-03-17 23:59:40 +0100 (Mon, 17 Mar 2008) New Revision: 3165 Modified: trunk/util/flashrom/Makefile trunk/util/flashrom/board_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/flashrom.c Log: Support for the Winbond W39V080FA series of chips. Support for flashing on the Kontron 986LCD-M board. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/Makefile =================================================================== --- trunk/util/flashrom/Makefile 2008-03-17 17:06:06 UTC (rev 3164) +++ trunk/util/flashrom/Makefile 2008-03-17 22:59:40 UTC (rev 3165) @@ -24,7 +24,7 @@ am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \ 82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \ sst_fwhub.o layout.o cbtable.o flashchips.o flashrom.o \ - sharplhf00l04.o w29ee011.o spi.o + w39v080fa.o sharplhf00l04.o w29ee011.o spi.o all: pciutils dep $(PROGRAM) Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-03-17 17:06:06 UTC (rev 3164) +++ trunk/util/flashrom/board_enable.c 2008-03-17 22:59:40 UTC (rev 3165) @@ -431,6 +431,42 @@ return 0; } +static int board_kontron_986lcd_m(const char *name) +{ + struct pci_dev *dev; + uint16_t gpiobar; + uint32_t val; + +#define ICH7_GPIO_LVL2 0x38 + + dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */ + if (!dev) { + // This will never happen on this board + fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n"); + return -1; + } + + /* Use GPIOBASE register to find where the GPIO is mapped. */ + gpiobar = pci_read_word(dev, 0x48) & 0xfffc; + + val = inl(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ + printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); + + /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 + * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0 + * bit 3 (0x08) = 0 #WP --> block locking = 1 + * bit 3 (0x08) = 1 #WP --> block locking = 0 + * + * To enable full block locking, you would do: + * val &= ~ ((1 << 2) | (1 << 3)); + */ + val |= (1 << 2) | (1 << 3); + + outl(val, gpiobar + ICH7_GPIO_LVL2); + + return 0; +} + /** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on @@ -497,6 +533,8 @@ "artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000, "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x}, + {0x8086, 0x27b8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ }; Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-03-17 17:06:06 UTC (rev 3164) +++ trunk/util/flashrom/flash.h 2008-03-17 22:59:40 UTC (rev 3165) @@ -276,6 +276,8 @@ #define W_39V040A 0x3D #define W_39V040B 0x54 #define W_39V080A 0xD0 +#define W_39V080FA 0xD3 +#define W_39V080FA_DM 0x93 #define W_49F002U 0x0B #define W_49V002A 0xB0 #define W_49V002FA 0x32 @@ -414,6 +416,11 @@ int erase_sst_fwhub(struct flashchip *flash); int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); +/* w39V080fa.c */ +int probe_winbond_fwhub(struct flashchip *flash); +int erase_winbond_fwhub(struct flashchip *flash); +int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf); + /* w29ee011.c */ int probe_w29ee011(struct flashchip *flash); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-03-17 17:06:06 UTC (rev 3164) +++ trunk/util/flashrom/flashchips.c 2008-03-17 22:59:40 UTC (rev 3165) @@ -129,6 +129,8 @@ {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, {"Winbond", "W49V002A", WINBOND_ID, W_49V002A, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, {"Winbond", "W49V002FA", WINBOND_ID, W_49V002FA, 256, 128, probe_jedec, erase_chip_jedec, write_49f002}, + {"Winbond", "W39V080FA", WINBOND_ID, W_39V080FA, 1024, 64*1024, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, + {"Winbond", "W39V080FA (dual mode)",WINBOND_ID, W_39V080FA_DM, 512, 64*1024, probe_winbond_fwhub, erase_winbond_fwhub, write_winbond_fwhub}, {"EON", "unknown SPI chip", EON_ID_NOPREFIX,GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, {"Macronix", "unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0, probe_spi, NULL, NULL}, Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-03-17 17:06:06 UTC (rev 3164) +++ trunk/util/flashrom/flashrom.c 2008-03-17 22:59:40 UTC (rev 3165) @@ -109,8 +109,8 @@ flash++; continue; } - printf_debug("Probing for %s, %d KB\n", - flash->name, flash->total_size); + printf_debug("Probing for %s %s, %d KB: ", + flash->vendor, flash->name, flash->total_size); size = flash->total_size * 1024;

1 0

Re: [coreboot] m57sli FAN control
by Ward Vandewege 17 Mar '08

17 Mar '08

All right, please find a revised patch attached that does not stop the CPU fan. Turns out that the original patch malfunctioned on both v1.1 and v2 of the board if the it87 driver was not loaded. That driver fixed the settings, which added to my confusion. It also explains why it seemed to work for me at first, but then did not when rebooting (I was booting a different filesystem that did not load the it87 module on startup). Anyway, I'd be grateful for some testing of the attached. It does the right thing on v1.1 and v2 of the board based on my testing. It does not set the diode zero adjust temperature right yet for v2 of the board (it should be 0xfe instead of 0xec). That could be done by adding a detection for the revision of the IT8716F chip (v2 seems to have rev3, v1.1 has rev0), but I don't have time to add that right now. It's not that important I think - but if someone wants to contribute that change, please feel free. There are a few other registers that should be slightly different between v1.1 and v2 but nothing very crucial it seems. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

3 6

SMI support in coreboot
by David Edrich 17 Mar '08

17 Mar '08

Is there any SMI support in coreboot? I read there was something called VSA, that sounds like SMI support relevant. Maybe only for Opterons?

2 1

r139 - buildrom-devel/config/platforms
by svn＠coreboot.org 17 Mar '08

17 Mar '08

Author: ward Date: 2008-03-17 18:42:24 +0100 (Mon, 17 Mar 2008) New Revision: 139 Modified: buildrom-devel/config/platforms/tyan-s2891.conf Log: Bump up coreboot revision to get the right image size for filo/etherboot payloads. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/tyan-s2891.conf =================================================================== --- buildrom-devel/config/platforms/tyan-s2891.conf 2008-03-10 19:55:49 UTC (rev 138) +++ buildrom-devel/config/platforms/tyan-s2891.conf 2008-03-17 17:42:24 UTC (rev 139) @@ -41,7 +41,7 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf CBV2_TDIR=s2891 -CBV2_TAG=3092 +CBV2_TAG=3164 # FILO configuration

1 0

Re: [coreboot] r3157 - in trunk/coreboot-v2/src/southbridge/intel: . i3100
by Uwe Hermann 17 Mar '08

17 Mar '08

A few more comments on things I noticed: On Mon, Mar 17, 2008 at 12:34:17AM +0100, svn(a)coreboot.org wrote: > +static void i3100_enable_superio(void) > +{ > + device_t dev; > + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, > + PCI_DEVICE_ID_INTEL_3100_LPC), 0); > + if (dev == PCI_DEV_INVALID) { > + die("LPC bridge not found\r\n"); > + } Do we actually need this kind of check? If the LPC device is not there or is the wrong one, that's clearly a programming bug, no? This function will only be called from i3100 boards, so the LPC device is surely available. Similar example: when you write code for an Intel board and include an AMD CPU init file or something -- clearly a bug, no need for bloating the code to check for that kind of programmer bug. Opinions? I'd say drop this check (here and in many other files/chipsets). Or is there some other valid reason why this has to be checked at run-time in the code? > + > + /* Enable decoding of I/O locations for SuperIO devices */ > + pci_write_config16(dev, 0x82, 0x340f); > +} > > Added: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c > =================================================================== [...] > +#include "i3100_smbus.h" > + > +#define SMBUS_IO_BASE 0x0f00 > + > +static void enable_smbus(void) > +{ > + device_t dev; > + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, > + PCI_DEVICE_ID_INTEL_3100_SMB), 0); > + if (dev == PCI_DEV_INVALID) { > + die("SMBus controller not found\r\n"); > + } Ditto, see above. > +#include <console/console.h> > +#include <device/device.h> > +#include <device/pci.h> > +#include <device/pci_ids.h> Currently needed, but I think we should also have pci.h include this one, as we do in v3 -- pretty much every file needs pci_ids.h. > +#include <device/pci_ops.h> Not needed, already included by pci.h. > Added: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_reset.c > =================================================================== > --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_reset.c (rev 0) > +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_reset.c 2008-03-16 23:34:10 UTC (rev 3157) > @@ -0,0 +1,26 @@ [...] > +#include <arch/io.h> > + > +void hard_reset(void) > +{ > + outb(0x06, 0xcf9); > +} Is this tested? When and where is it used/invoked? coreboot-internally as part of bringup or when you say 'reboot' in Linux? Does it have to be in an extra file? That's a bit of an overkill for one line of code. Can we merge it into some other i3100 file? Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 1

r3164 - trunk/coreboot-v2/targets/tyan/s2891
by svn＠coreboot.org 17 Mar '08

17 Mar '08

Author: ward Date: 2008-03-17 18:06:06 +0100 (Mon, 17 Mar 2008) New Revision: 3164 Modified: trunk/coreboot-v2/targets/tyan/s2891/Config.lb Log: The ATI vga rom is only 36K on the Tyan s2891, not 48K. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/coreboot-v2/targets/tyan/s2891/Config.lb =================================================================== --- trunk/coreboot-v2/targets/tyan/s2891/Config.lb 2008-03-17 13:43:48 UTC (rev 3163) +++ trunk/coreboot-v2/targets/tyan/s2891/Config.lb 2008-03-17 17:06:06 UTC (rev 3164) @@ -7,12 +7,12 @@ # Tyan s2891 romimage "normal" -# 48K for ATI ROM in 1M - option ROM_SIZE = 1024*1024-48*1024 -# 48K for SCSI FW or ATI ROM +# 36K for ATI ROM in 1M + option ROM_SIZE = 1024*1024-36*1024 +# 48K for SCSI FW # option ROM_SIZE = 512*1024-48*1024 -# 48K for SCSI FW and 48K for ATI ROM -# option ROM_SIZE = 512*1024-48*1024-48*1024 +# 48K for SCSI FW and 36K for ATI ROM +# option ROM_SIZE = 512*1024-48*1024-36*1024 # 64K for Etherboot # option ROM_SIZE = 512*1024-64*1024 option USE_FALLBACK_IMAGE=0

1 0

Re: [coreboot] .. Re: Via epia
by jtd 17 Mar '08

17 Mar '08

On Friday 14 March 2008 10:50 pm, Uwe Hermann wrote: > On Fri, Mar 14, 2008 at 07:07:46PM +0530, jtd wrote: > > On Friday 14 March 2008 12:15 pm, Corey Osgood wrote: > > > you need to have a src/via/idot/mainboard.c with > > > mainboard_via_idot_ops declared in it. See the same file for > > > any other target for an example. > > > > Ok. Done. > > It now bombs at > > make[1]: *** No rule to make target `/root/svn/payload.elf', > > needed by `payload'. Stop > > > > What payload is recommended?. Filo or grub2. The payload page > > says grub2 does not work as yet. > > Start with FILO for now. I think GRUB2 doesn't work with corebootv2 > yet and it's less tested and documented so far. > > > and filo-0.5 fails with > > gcc -m32 -Wall -Os -fomit-frame-pointer -fno-common > > -ffreestanding -fno-strict-aliasing -Wno-pointer-sign -Wno-unused > > -nostdinc -imacros ../config.h -I../include > > -I/usr/lib/gcc-lib/i486-linux/3.3.5/include -MD -c filo.c -o > > filo.o cc1: error: unrecognized option `-Wno-pointer-sign' > > Just drop '-Wno-pointer-sign' from the Makefile, your compiler > seems pretty old and doesn't know about that option. shifted the tree to etch. filo-0.5 compiles. But... ./buildrom coreboot.strip coreboot.rom payload 0x10000 0x20000 ERROR: payload (78064) + coreboot (65536) - Size is 12528 bytes larger than ROM size (131072). make[1]: *** [coreboot.rom] Error 1 since vgarom = 61952 payload = 78064 coreboot = 65536 total = 205552 It should fit into the 256KB flash with 56592 bytes to spare. Do i need to disable fallback? What is the purpose of fallback. -- Rgds JTD

4 5

← Newer
1
...
14
15
16
17
18
19
20
...
39
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2008