coreboot September 2007

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367 discussions

Re: [LinuxBIOS] Dummy pci dev for image on a usb flash drive (Peter Stuge)
by Baski 27 Sep '07

27 Sep '07

------------------------------ Message: 4 Date: Thu, 27 Sep 2007 11:04:22 +0200 From: Peter Stuge Subject: Re: [LinuxBIOS] Dummy pci dev for image on a usb flash drive To: linuxbios(a)linuxbios.org Message-ID: <20070927090422.12905.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii On Wed, Sep 26, 2007 at 10:19:08PM -0700, Baski wrote: > I want to place an option ROM image on a raw USB flash drive. Please explain why, otherwise we can't help you much. > It will be an option ROM image of a proper controller with correct > option ROM and PNP headers. How can we make linuxBios to look for > this drive and allocate dummy pci resources like bus 0 dev-xx, fun > yy and irqs? First, LB has no USB drivers. You could move what is in FILO over though. More relevant is the fact that LB can't allocate resources to hardware that does not exist. Unless you have the controller itself it's not possible to set any resources. They are set in registers (RAM) that is mandatory for PCI cards to have (the so called PCI config space) and no card means nowhere to set things. Furthermore, option ROMs are not really "compatible" with LB, the idea is to try to use existing open source drivers with LB instead of binary blobs with broken interfaces. So - what do you want to accomplish with your idea? There may be a better way to do it, or it may be best to forget the whole thing. We can't say without more info. //Peter This is for my MS project. We want to simulate a PCI card and use one of the CPU cores to do our processing. We would also want to reserve that core. We want to create the dummy pci device so that OS driver can communicate with the emulated card. What methods would you suggest? Thanks. --------------------------------- Got a little couch potato? Check out fun summer activities for kids.

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[LinuxBIOS] r2811 build service
by LinuxBIOS information 27 Sep '07

27 Sep '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "ward" checked in revision 2811 to the LinuxBIOS source repository and caused the following changes: Change Log: Add preliminary SPI flash identification support for SPI chips attached to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte M57SLI board. It works only with rev 2.0 of the board, but it will bail out on earlier versions, so no damage can occur. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2811&device=khepri&vendor… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] Mobile Phone ROMs
by Laith Juwaidah 27 Sep '07

27 Sep '07

Hi, I found your website by accident, I was looking for a way to flash the ROM of my Samsung I600 so I can install Linux on it (It's a project I want to do)... I am a programmer but I'm completely new to this... That's why I was wondering if I can use flashrom to flash the ROM of my Samsung... Chears! -- Laith Juwaidah ljuwaidah(a)gmail.com http://www.ljuwaidah.org

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[LinuxBIOS] r2811 - trunk/util/flashrom
by svn＠openbios.org 27 Sep '07

27 Sep '07

Author: ward Date: 2007-09-27 16:29:57 +0200 (Thu, 27 Sep 2007) New Revision: 2811 Modified: trunk/util/flashrom/board_enable.c Log: Add preliminary SPI flash identification support for SPI chips attached to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte M57SLI board. It works only with rev 2.0 of the board, but it will bail out on earlier versions, so no damage can occur. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2007-09-26 16:41:15 UTC (rev 2810) +++ trunk/util/flashrom/board_enable.c 2007-09-27 14:29:57 UTC (rev 2811) @@ -4,6 +4,7 @@ * Copyright (C) 2005-2007 coresystems GmbH <stepan(a)coresystems.de> * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2007 Luc Verhaegen <libv(a)skynet.be> + * Copyright (C) 2007 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,6 +30,104 @@ #include <string.h> #include "flash.h" +/* Generic Super I/O helper functions */ +uint8_t regval(uint16_t port, uint8_t reg) +{ + outb(reg, port); + return inb(port + 1); +} + +void regwrite(uint16_t port, uint8_t reg, uint8_t val) +{ + outb(reg, port); + outb(val, port + 1); +} + +/* Helper functions for most recent ITE IT87xx Super I/O chips */ +#define CHIP_ID_BYTE1_REG 0x20 +#define CHIP_ID_BYTE2_REG 0x21 +static void enter_conf_mode_ite(uint16_t port) +{ + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + if (port == 0x2e) + outb(0x55, port); + else + outb(0xaa, port); +} + +static void exit_conf_mode_ite(uint16_t port) +{ + regwrite(port, 0x02, 0x02); +} + +static uint16_t find_ite_serial_flash_port(uint16_t port) +{ + uint8_t tmp = 0; + uint16_t id, flashport = 0; + + enter_conf_mode_ite(port); + + id = regval(port, CHIP_ID_BYTE1_REG) << 8; + id |= regval(port, CHIP_ID_BYTE2_REG); + + /* TODO: Handle more IT87xx if they support flash translation */ + if (id == 0x8716) { + /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ + tmp = regval(port, 0x24) & 0xFE; + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); + printf("LPC write to serial flash %sabled\n", + (tmp & 1 << 4) ? "en" : "dis"); + printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + /* LDN 0x7, reg 0x64/0x65 */ + regwrite(port, 0x07, 0x7); + flashport = regval(port, 0x64) << 8; + flashport |= regval(port, 0x65); + } + exit_conf_mode_ite(port); + return flashport; +} + +static void it8716_serial_rdid(uint16_t port) +{ + uint8_t busy, data0, data1, data2; + do { + busy = inb(port) & 0x80; + } while (busy); + /* RDID */ + outb(0x9f, port + 1); + /* Start IO, 33MHz, 3 input bytes, 0 output bytes*/ + outb((0x5<<4)|(0x3<<2)|(0x0), port); + do { + busy = inb(port) & 0x80; + } while (busy); + data0 = inb(port + 5); + data1 = inb(port + 6); + data2 = inb(port + 7); + printf("RDID returned %02x %02x %02x\n", data0, data1, data2); + return; +} + +static int it87xx_probe_serial_flash(const char *name) +{ + uint16_t flashport; + flashport = find_ite_serial_flash_port(0x2e); + if (flashport) + it8716_serial_rdid(flashport); + flashport = find_ite_serial_flash_port(0x4e); + if (flashport) + it8716_serial_rdid(flashport); + return 0; +} + /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -314,6 +413,8 @@ }; struct board_pciid_enable board_pciid_enables[] = { + {0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + "gigabyte", "m57sli", "GIGABYTE GA-M57SLI", it87xx_probe_serial_flash}, {0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise}, {0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,

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Re: [LinuxBIOS] LinuxBIOS from Dell
by Robert Vogel 27 Sep '07

27 Sep '07

----- Original Message ----- From: "ron minnich" <rminnich(a)gmail.com> To: "Robert Vogel" <vogel(a)ct.metrocast.net> Cc: "yhlu" <yinghailu(a)gmail.com>; "Corey Osgood" <corey.osgood(a)gmail.com>; <linuxbios(a)linuxbios.org>; "Carl-Daniel Hailfinger" <c-d.hailfinger.devel.2006(a)gmx.net>; "Danny Piccirillo" <danny.piccirillo(a)gmail.com> Sent: Wednesday, September 26, 2007 12:07 PM Subject: Re: [LinuxBIOS] LinuxBIOS from Dell > > >> Are there hiding places in the chipset too ? How closed are the chipsets >> ? > > Depends on the vendor. > > ron > How about AMD ?

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[LinuxBIOS] Dummy pci dev for image on a usb flash drive
by Baski 27 Sep '07

27 Sep '07

Hi LB Gurus, I want to place an option ROM image on a raw USB flash drive. It will be an option ROM image of a proper controller with correct option ROM and PNP headers. How can we make linuxBios to look for this drive and allocate dummy pci resources like bus 0 dev-xx, fun yy and irqs? Thanks a lot for your time. -Baski --------------------------------- Don't let your dream ride pass you by. Make it a reality with Yahoo! Autos.

2 1

[LinuxBIOS] Motherboard exchange?
by Alex Beregszaszi 27 Sep '07

27 Sep '07

Hi, I have a Chaintech Apogee 7NJL1 board, still unboxed. It has an Nvidia nForce2 chipset, an ITE IT8712F superio chip, Socket-A (AMD K7) cpu slot and a socketed flash chip. It has lot of goodies inside, see for example http://www.motherboard.cz/mb/chaintech/7NJL1.htm for detailed listing. As K7 motherboards are not supported (according to the wiki), this would be a good challenge to add code for it, while the chipset has probably already support in LinuxBIOS v2 making the job easier. I am willing to donate this to someone doing the job. Also I am seeking a donation: a board which is already (partly) suppoted by v2 and can accept an Intel CPU with SSE3 (preferably SSE4) support (as a plus it could have a socketed flash chip :). Anyone interested? (I am based in Europe, this is the preferred region to avoid high shipping costs.) -- Alex

1 0

[LinuxBIOS] [PATCH] buildrom: Update AMD LX platforms
by Marc Jones 26 Sep '07

26 Sep '07

Note that other LX platform "owners" should update the buildrom platform linuxbios tags to pick up the PERR#/SERR# fix. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Update AMD GeodeLX platfroms to get latest PCI device fixes. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: buildrom/config/platforms/db800.conf =================================================================== --- buildrom.orig/config/platforms/db800.conf 2007-09-26 05:30:37.000000000 -0600 +++ buildrom/config/platforms/db800.conf 2007-09-26 05:34:12.000000000 -0600 @@ -32,7 +32,7 @@ LINUXBIOS_BOARD=db800 LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=db800 -LINUXBIOS_TAG=2750 +LINUXBIOS_TAG=2810 LINUXBIOS_ROM_NAME=db800.rom # FILO configuration Index: buildrom/config/platforms/norwich.conf =================================================================== --- buildrom.orig/config/platforms/norwich.conf 2007-09-26 05:33:14.000000000 -0600 +++ buildrom/config/platforms/norwich.conf 2007-09-26 05:34:26.000000000 -0600 @@ -30,7 +30,7 @@ LINUXBIOS_BOARD=norwich LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=norwich -LINUXBIOS_TAG=2722 +LINUXBIOS_TAG=2810 LINUXBIOS_ROM_NAME=norwich.rom # FILO configuration

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[LinuxBIOS] r42 - buildrom-devel/config/platforms
by svn＠openbios.org 26 Sep '07

26 Sep '07

Author: jcrouse Date: 2007-09-27 00:15:06 +0200 (Thu, 27 Sep 2007) New Revision: 42 Modified: buildrom-devel/config/platforms/db800.conf buildrom-devel/config/platforms/norwich.conf Log: Update AMD GeodeLX platfroms to get latest PCI device fixes. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: buildrom-devel/config/platforms/db800.conf =================================================================== --- buildrom-devel/config/platforms/db800.conf 2007-09-26 20:09:07 UTC (rev 41) +++ buildrom-devel/config/platforms/db800.conf 2007-09-26 22:15:06 UTC (rev 42) @@ -32,7 +32,7 @@ LINUXBIOS_BOARD=db800 LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=db800 -LINUXBIOS_TAG=2750 +LINUXBIOS_TAG=2810 LINUXBIOS_ROM_NAME=db800.rom # FILO configuration Modified: buildrom-devel/config/platforms/norwich.conf =================================================================== --- buildrom-devel/config/platforms/norwich.conf 2007-09-26 20:09:07 UTC (rev 41) +++ buildrom-devel/config/platforms/norwich.conf 2007-09-26 22:15:06 UTC (rev 42) @@ -30,7 +30,7 @@ LINUXBIOS_BOARD=norwich LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=norwich -LINUXBIOS_TAG=2722 +LINUXBIOS_TAG=2810 LINUXBIOS_ROM_NAME=norwich.rom # FILO configuration

1 0

[LinuxBIOS] buildrom patch for ALIX1.C
by ron minnich 26 Sep '07

26 Sep '07

This patch is for ALIX 1.C support for buildrom. ron

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coreboot September 2007