coreboot September 2007

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367 discussions

[LinuxBIOS] Call for help: superiotool
by Uwe Hermann 08 Oct '07

08 Oct '07

Hi, as you may have noticed, we have a relatively new tool called 'superiotool' (http://linuxbios.org/index.php/Superiotool) in the repository: $ svn co svn://linuxbios.org/repos/trunk/util/superiotool It is able to detect which Super I/O is located on your mainboard, and (if the respective code support was added), it can also dump the contents of all registers on the Super I/O: $ superiotool -d This will hopefully be helpful in debugging Super I/O related problems, e.g. with keyboards, systems sensors and fans, etc. To make the tool more useful we need - As many supported Super I/Os as possible. Supporting new ones is relatively easy, but a bit time-consuming. You have to grab the datasheet, find out the ID/version of the Super I/O and add it in the respective file (ite.c for ITE Super I/Os, for example). For the dump functionality you have to add a (large) table with all registers and their defaults. - One or two outputs of 'superiotool -d' for each supported Super I/O for reference, so we can compare values for different boards. If you have one of the supported Super I/Os (see table in http://linuxbios.org/Superiotool) please run 'superiotool -d' as root, reply to this email and submit the output. We'll then link to your email (in the list archive) in the wiki page. Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] problem on geode
by ron minnich 08 Oct '07

08 Oct '07

with the older version of linuxbios on the msm800sev, I could reflash. I can ID but no longer reflash with the buildrom version of linuxbios. here is the 0x1808 MSR. pbx ~ # /rdmsr 0x1808 MSR register 0x1808 => 25:ff:fc:02:13:f7:df:00 pbx ~ # /wrmsr 0x1808 22:ff:fc:02:10:f3:bf:00 MSR register 0x1808 => 22:ff:fc:02:10:f3:bf:00 pbx ~ # /rdmsr 0x1808 MSR register 0x1808 => 22:ff:fc:02:10:f3:bf:00 this was sufficient before. Marc, what should I look at? flashrom does this: pbx ~ # ./flashrom Calibrating delay loop... ok Found LinuxBIOS table at: 00000530 vendor id: digitallogic part id: msm800sev WARNING: No chipset found. Flash detection will most likely fail. M50FW080 found at physical address: 0xfff00000 Flash part is M50FW080 (1024 KB) OK, only ENABLING flash write, but NOT FLASHING. pbx ~ # ./flashrom -w d.rom Calibrating delay loop... ok Found LinuxBIOS table at: 00000530 vendor id: digitallogic part id: msm800sev WARNING: No chipset found. Flash detection will most likely fail. M50FW080 found at physical address: 0xfff00000 Flash part is M50FW080 (1024 KB) ERASE FAILED Is there some other setting I need to go after? ron

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[LinuxBIOS] Problems with Filo booting - HELP
by joe＠smittys.pointclark.net 07 Oct '07

07 Oct '07

Help me please. I have attached my bootlog. Filo gets this error, what does it mean? Thanks - Joe ------------------------------------------------- Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffd0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 00018000 malloc 0x00018000 New segment addr 0x100000 size 0x3d260 offset 0xc0 filesize 0x13248 (cleaned up) New segment addr 0x100000 size 0x3d260 offset 0xc0 filesize 0x13248 lb: [0x0000000000004000, 0x000000000001c000) malloc Enter, size 32, free_mem_ptr 00018020 malloc 0x00018020 New segment addr 0x13d260 size 0x48 offset 0x13320 filesize 0x48 (cleaned up) New segment addr 0x13d260 size 0x48 offset 0x13320 filesize 0x48 lb: [0x0000000000004000, 0x000000000001c000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000003d260 filesz: 0x0000000000013248 [ 0x0000000000100000, 0000000000113248, 0x000000000013d260) <- 00000000000000c0 Clearing Segment: addr: 0x0000000000113248 memsz: 0x000000000002a018 Loading Segment: addr: 0x000000000013d260 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x000000000013d260, 000000000013d2a8, 0x000000000013d2a8) <- 0000000000013320 Loaded segments verified segments closed down stream Jumping to boot code at 0x10ea14 entry = 0x0010ea14 lb_start = 0x00004000 lb_size = 0x00018000 adjust = 0x07fe4000 buffer = 0x07fd0000 elf_boot_notes = 0x000139a0 adjusted_boot_notes = 0x07ff79a0 Unexpected Exception: -1 @ ffffffff:ffffffff - Halting Code: -1 eflags: ffffffff eax: ffffffff ebx: ffffffff ecx: ffffffff edx: 00018000 edi: ffffffff esi: ffffffff ebp: 0010003c esp: 00100014 --------------------------------------------------------

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[LinuxBIOS] badly initialized (?) pci bridge on the M57SLI (with irq table and mptable)
by Ward Vandewege 05 Oct '07

05 Oct '07

Hi there, We've had a bit of a chat on the IRC channel today about the M57SLI and how the pci bridge does not seem to be initialized properly under LinuxBIOS. The pci-e bridge is initialized ok - pci-e vga cards work fine; pci vga cards do not. Here's an lspci of the pci bridge (device 06.0), booted from the proprietary bios: 0000:00:06.0 0604: 10de:0370 (rev a2) (prog-if 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fb000000-fb0fffff Prefetchable memory behind bridge: fff00000-000fffff BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [b8] #0d [0000] Capabilities: [8c] #08 [a800] 00: de 10 70 03 07 00 b0 00 a2 01 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 f0 00 80 02 20: 00 fb 00 fb f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 00 0a and from linuxbios: 0000:00:06.0 0604: 10de:0370 (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [b8] #0d [0000] Capabilities: [8c] #08 [a800] 00: de 10 70 03 04 01 b0 00 a2 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 80 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 03 0a Uwe thought that perhaps there was an issue with the IRQ or MP table. I've run getpir and mptable while running the proprietary BIOS, and here's the output: http://ward.vandewege.net/m57sli_mptable.output http://ward.vandewege.net/m57sli_irq_tables.c I've also saved a proprietary and linuxbios dmesg output, since there seems to be something funny going on with the PCI bridge detection - under LinuxBIOS no less than 7 devices show up as PCI bridges, rather than the 2 that show up under the proprietary BIOS. http://ward.vandewege.net/m57sli_dmesg_linuxbios.txt http://ward.vandewege.net/m57sli_dmesg_proprietary.txt Suggestions? Things to try? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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Re: [LinuxBIOS] svn tricks [was:r2814 - trunk/util/superiotool]
by Peter Stuge 05 Oct '07

05 Oct '07

On Fri, Sep 28, 2007 at 05:45:43PM +0200, svn(a)openbios.org wrote: > Modified: trunk/util/superiotool/superiotool.h > =================================================================== > --- trunk/util/superiotool/superiotool.h 2007-09-28 15:39:10 UTC (rev 2813) > +++ trunk/util/superiotool/superiotool.h 2007-09-28 15:45:43 UTC (rev 2814) > @@ -1,5 +1,5 @@ > /* > - * This file is part of the LinuxBIOS project. > + * This file is part of the superiotool project. > * > * Copyright (C) 2007 Carl-Daniel Hailfinger > * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> > @@ -29,7 +29,7 @@ > #include <getopt.h> > #include <sys/io.h> > > -#define SUPERIOTOOL_VERSION "0.1" > +#define SUPERIOTOOL_VERSION "r$Rev$" How do I work with this? $Rev$ for superiotool.h won't be increased automatically when I make changes to another file. I don't even think $Rev$ will bump when I export the changed rev, so this will only show the last rev of the particular file? I have this issue in my own svn repos. What am I doing wrong? //Peter

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[LinuxBIOS] [RFC] FILO normal/fallback boot patch
by Corey Osgood 05 Oct '07

05 Oct '07

Dunno if anyone's ever wanted/done this before, but the attached patch adds a fallback boot option to FILO, so that if the first kernel fails, the second one gets booted, if that fails it drops to the usual command line. I'm using it on Magden's system to try to boot from USB before going to the hard drive, but I imagine it could be used for CD-ROM, etc, just as easily. The fallback boot is entirely optional, if not defined it's just ignored. Also, this won't break Peter's filo speedup patch, except the changes to the default config file (which I'll fix and send another patch, if need be). It needs a little more prettying up and some comments if it were to get committed, but if people don't want it I won't bother. -Corey

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[LinuxBIOS] GA-M57SLI SPI support
by Carl-Daniel Hailfinger 03 Oct '07

03 Oct '07

Hi, this new thread is here just to get some early testing and info on the GA-M57SLI SPI flash. The IT8716F is indeed used for LPC-to-SPI translation as I supected. LDN 0x0, reg 0x24: val=0x1a serial flash interface at pin 29 LPC write to serial flash enabled 512kByte of flash are mapped at top of 4GByte 128kByte of flash are mapped at top of 1MByte (1152kByte can be mapped at most) LDN 0x7, reg 0x64/0x65: val=0x08/0x20 serial flash interface base addr 0x0820 (that's an I/O port) What I need: * Byte reads from all ports between 0x0820-0x0827 on the SPI version of the GA-M57SLI under factory BIOS. Should be harmless. * Exact type of SPI flash chip (datasheet link would be nice) * Volunteer who can reflash manually once my writing code is ready. Carl-Daniel

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[LinuxBIOS] linuxbios support for thinkpads?
by Robinson Tryon 02 Oct '07

02 Oct '07

Hiya, I'm in the market for a new laptop on which to run Ubuntu, and Lenovo's Thinkpads look like a good choice. I like the idea of running an open BIOS, but looking at past posts to the mailing list, it appears that certain chipsets (such as those for the T60) are not supported: http://article.gmane.org/gmane.linux.bios/19651 I believe that certain (older) Thinkpad chipsets are supported, but what about the 945 or the 965 (for the T61) ? The "Supported Chipsets" page (below) hasn't had any updates in a couple of months -- is that the best place for me to determine if Linux BIOS is compatible with a particular chipset/system? http://linuxbios.org/index.php/Supported_Chipsets_and_Devices Thanks, -- Robinson

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[LinuxBIOS] Enabling APIC 82801xx
by joe＠smittys.pointclark.net 02 Oct '07

02 Oct '07

OK, I have a new booting problem. LB dies on the i82801xx_enable_ioapic() function in 82801xx_lpc.c: void i82801xx_enable_ioapic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (3 << 7); /* Enable IOAPIC */ reg32 |= (1 << 13); /* Coprocessor error enable */ reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); printk_debug("IOAPIC Southbridge enabled %x\n", reg32); *ioapic_index = 0; *ioapic_data = (1 << 25); *ioapic_index = 0; reg32 = *ioapic_data; printk_debug("Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n"); /* TODO: From i82801ca, needed/useful on other ICH? */ *ioapic_index = 3; // Select Boot Configuration register *ioapic_data = 1; // Use Processor System Bus to deliver interrupts } Initializing devices... Root Device init PCI: 00:00.0 init Northbridge init PCI: 00:1d.0 init PCI: 00:1d.1 init PCI: 00:1d.2 init PCI: 00:1d.7 init EHCI: Setting up controller.. done. PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 0 APIC Error What is going on here? Why is *ioapic_data coming back as 0x0 after it has been set to 0x2000000 (1 << 25)? Help? Thanks - Joe

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[LinuxBIOS] successfully flashed Asus M2A-VM,
by Rodney Crossman 01 Oct '07

01 Oct '07

just an fyi that I successfully flashed the bios on an Asus M2A-VM motherboard which has an amd 690G chipset. System has been power cycled and all is working. Thank you all for providing this extremely useful tool. # ./flashrom -wv m2a1301.bin Calibrating delay loop... ok No LinuxBIOS table found. WARNING: No chipset found. Flash detection will most likely fail. SST49LF080A found at physical address: 0xfff00000 Flash part is SST49LF080A (1024 KB) Flash image seems to be a legacy BIOS. Disabling checks. Programming Page: 0255 at address: 0x000ff000 Verifying flash - VERIFIED Rodney All outgoing messages have been checked for viruses by Etrust Antivirus.

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coreboot September 2007