coreboot September 2007

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367 discussions

[LinuxBIOS] [PATCH] pci_rom.c checksum extension rom
by Alex Beregszaszi 29 Nov '07

29 Nov '07

Hi, the attached patch adds code to checksum the pci extension rom and stop if the stored and calculated checksum differ. -- Alex

6 15

[LinuxBIOS] #87: flashrom issues on m57sli-s4
by LinuxBIOS 14 Nov '07

14 Nov '07

#87: flashrom issues on m57sli-s4 ---------------------------------+------------------------------------------ Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ There is a problem with flashrom; it won't work reliably when the machine is booted under LinuxBIOS on the m57sli-s4. This is what I used to see: It works maybe 1 out of 10 times - it always works when booted with the proprietary BIOS. I can tell while it's flashing if it is good or not good: the speed of the flashing is moderately fast for a good flash. For a bad flash, it is either too fast, too slow, or it varies a lot during the flash. This is what I'm seeing today (with the latest rev of flashrom, 2744): Flashrom jumps from page 15 to page 224 while flashing, and then fails to verify. I've tried with several different chis (all of the same type though). {{{ # ./flashrom -vvvv -w /home/ward/Desktop/buildrom/buildrom-devel/deploy /gigabyte-m57sli.rom -V Calibrating delay loop... 537M loops per second. ok Found canidate at: 00000530-00000e2c Found LinuxBIOS table at: 00000530 lb_table found at address 0xb7e40530 LinuxBIOS header(24) checksum: e2db table(2300) checksum: 826c entries: 14 vendor id: GIGABYTE part id: m57sli Found chipset "NVIDIA MCP55": Enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for At29C040A, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for At29C020, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for Mx29f002, 256 KB probe_29f002: id1 0xbf, id2 0x5b Probing for SST29EE020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Probing for SST39SF010A, 128 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39SF020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39SF040, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST39VF020, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF040B, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF040, 512 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF020A, 256 KB probe_jedec: id1 0xbf, id2 0x5b Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xbf, id2 0x5b SST49LF080A found at physical address: 0xfff00000 Flash part is SST49LF080A (1024 KB) LinuxBIOS last image size (not rom size) is 1048576 bytes. MANUFACTURER: GIGABYTE MAINBOARD ID: m57sli This firmware image matches this motherboard. Programming Page: 0255 at address: 0x000ff000 Verifying flash address: 0x00000000 - FAILED }}} I should note that I'm using a bios savior to swap flash chips, and that the socket has been soldered onto the board manually. But under the proprietary bios there is never a problem, so... -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/87> LinuxBIOS <http://www.linuxbios.org/>

8 38

[LinuxBIOS] [PATCH] LAR checksums
by Alex Beregszaszi 14 Nov '07

14 Nov '07

Hi, checksum-fix.diff fixes a checksum calculation bug in the lar utility, where it would checksum less bytes then desired. lar-check-sum.diff implements checksum checking in the runtime lar code. I implemented the check inside the filename check, thus it wont be executed on unneeded entries. As my assumption was that I cant modify the memory, the code is skipping bytes between 20-24 of the header (checksum field) to generate a correct sum. This is bad, as the numbers shall be updated at every lar structure change. This is good, as we are not writing to memory. -- Alex

4 6

[LinuxBIOS] #80: serial console in grub2 works
by LinuxBIOS 07 Nov '07

07 Nov '07

#80: serial console in grub2 works ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: oxygene Type: enhancement | Status: new Priority: major | Milestone: Port GRUB2 to LinuxBIOS Component: code | Version: v3 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ grub2 should be capable of using the serial console, just like lbv3 is -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/80> LinuxBIOS <http://www.linuxbios.org/>

1 6

[LinuxBIOS] [PATCH] Support other than 0xC000 ROMs in VM86
by Alex Beregszaszi 17 Oct '07

17 Oct '07

Hi, this patch changes the real_mode_switch_call_vga() function to jump to the addr given as an argument instead the hardcoded 0xc000. Also it changes the function to inline assembly and passes the arguments through that. This patch includes the changes from my previous patch "[PATCH] vgabios: use same interface for biosemu.c and vm86.c", but should be committed incrementally. Btw, I think it would be a good idea to export the interrupt handlers to a common file (biosints.c?) and let it be hooked up by both vm86 and x86emu implementations. -- Alex

3 8

[LinuxBIOS] Gigabyte M61P-S3 board
by Michael van der Kolff 17 Oct '07

17 Oct '07

Well, I was just inspecting this beautiful little M61P-S3 board, and it has an SPI flash chip on it, in particular, the MX25L4005A. I don't seem to see anything that would indicate that anything but the IT8716F would be connecting to it. I first tried using the version in Debian (testing): It didn't detect any flash chip. I then tried using the SVN version: It too didn't detect anything. Then I looked through, and found a reference to the M55. I looked the archives, and found a message from May07: I figured I would see if I could get lucky telling it to look like an M55. I first got the connection to the IT8716F working, by telling it that the M61 is just like an M55, except with PCI device id 0x03e0. That seemed to work. However, going from there, it doesn't seem to detect any SPI functionality at all. It looks to me like support for each flash chip is needed (given that the spec sheet gives commands to output the manufacturer ID & device ID), but maybe that isn't true. In any case, the command set is relatively simple. Is the SPI stuff properly supported? I feel like I'm a little out of my depth on this code... Cheers, Michael

4 7

[LinuxBIOS] Supertek ST-3ET
by Markus Boas 16 Oct '07

16 Oct '07

Hi Volks, the ST-3WT boots but it dosn't load the rtl8139.elf oder zelf image for pxe. There is the boot log: Sep 19:08:00 CEST 2007 starting... Setting up default parameters for memory Sizing memory Probing for DIMM0 Found DIMM0 Page Size: 00002000 Component Banks: 4 Module Banks: 1 DIMM size: 08000000 Probing for DIMM1 MC_BANK_CFG = 00701530 Copying LinuxBIOS to RAM. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Normal So 30. Sep 19:08:00 CEST 2007 booting... clocks_per_usec: 360 Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1078/0001] enabled PCI: 00:0f.0 [10ec/8139] enabled PCI: 00:12.0 [1078/0100] enabled PCI: 00:12.1 [1078/0101] enabled PCI: 00:12.2 [1078/0102] enabled PCI: 00:12.3 [1078/0103] enabled PCI: 00:12.4 [1078/0104] enabled PCI: 00:13.0 [0e11/a0f8] enabled PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 enabled PCI: 00:12.1 disabled PCI: 00:12.2 enabled PCI: 00:12.3 disabled PCI: 00:12.4 disabled PCI: pci_scan_bus returning with max=000 done Allocating resources... Reading resources... Done reading resources. Setting resources... BC_DRAM_TOP = 0x07bfffff MC_GBASE_ADD = 0x000000f8 I would set ram size to 124 Mbytes PCI: 00:0f.0 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:0f.0 14 <- [0x00febfd000 - 0x00febfd0ff] mem PCI: 00:12.1 10 <- [0x00febfe000 - 0x00febfe0ff] mem PCI: 00:12.2 20 <- [0x0000001400 - 0x000000147f] io PCI: 00:12.3 10 <- [0x00febff000 - 0x00febff07f] mem PCI: 00:12.4 10 <- [0x00febfb000 - 0x00febfbfff] mem PCI: 00:13.0 10 <- [0x00febfc000 - 0x00febfcfff] mem Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 07 PCI: 00:0f.0 cmd <- 03 PCI: 00:12.0 cmd <- 0f PCI: 00:12.2 missing enable_resources PCI: 00:12.1 cmd <- 02 PCI: 00:12.2 cmd <- 01 PCI: 00:12.3 cmd <- 02 PCI: 00:12.4 cmd <- 02 PCI: 00:13.0 cmd <- 02 done. Initializing devices... Root Device init PCI: 00:00.0 init northbridge: northbridge_init() PCI: 00:12.0 init PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.4 init PNP: 002e.5 init PNP: 002e.6 init PNP: 002e.7 init PNP: 002e.8 init PCI: 00:0f.0 init PCI: 00:12.1 init PCI: 00:12.2 init Primary IDE interface disabled Secondary IDE interface enabled PCI: 00:12.3 init PCI: 00:12.4 init PCI: 00:13.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote linuxbios table at: 00000530 - 0000068c checksum 7000 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffcffff No header at 0 ... ... ... No header at 8096 header_offset is -1 Can not load ELF The Config.lb # Config file for the Eaglelion 5BCM motherboard # This will make a target directory of 5bcm target 5bcm mainboard eaglelion/5bcm option ROM_SIZE=512*1024 romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Normal" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebi # payload /etc/hosts payload /home/ryven/hardware/Linuxbios/payload/rtl8139.elf end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Fallback" # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf # payload ../../../../../lnxieepro100.ebia # payload /etc/hosts payload /home/ryven/hardware/Linuxbios/payload/rtl8139.elf end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" The lspci -vv Geode:~# lspci -vv 0000:00:00.0 Host bridge: Cyrix Corporation PCI Master Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 0000:00:0f.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RT8139 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at e000 [size=256] Region 1: Memory at d0000000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:12.0 ISA bridge: Cyrix Corporation 5530 Legacy [Kahlua] (rev 30) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64, Cache Line Size: 0x04 (16 bytes) 0000:00:12.1 Bridge: Cyrix Corporation 5530 SMI [Kahlua] Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 40012000 (32-bit, non-prefetchable) [size=256] 0000:00:12.2 IDE interface: Cyrix Corporation 5530 IDE [Kahlua] (prog-if 80 [Master]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Region 4: I/O ports at f000 [size=16] 0000:00:12.3 Multimedia audio controller: Cyrix Corporation 5530 Audio [Kahlua] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Region 0: Memory at 40011000 (32-bit, non-prefetchable) [size=128] 0000:00:12.4 VGA compatible controller: Cyrix Corporation 5530 Video [Kahlua] (prog-if 00 [VGA]) Subsystem: Cyrix Corporation: Unknown device 0001 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 40800000 (32-bit, non-prefetchable) [size=8M] 0000:00:13.0 USB Controller: Compaq Computer Corporation ZFMicro Chipset USB (rev 06) (prog-if 10 [OHCI]) Subsystem: Compaq Computer Corporation ZFMicro Chipset USB Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (20000ns max), Cache Line Size: 0x08 (32 bytes) Interrupt: pin A routed to IRQ 15 Region 0: Memory at d0004000 (32-bit, non-prefetchable) [size=4K] Can say me somebody what i make wrong? Greeding Markus

4 7

[LinuxBIOS] my zepto.se laptop info
by Peter Brännvall 14 Oct '07

14 Oct '07

2 1

[LinuxBIOS] [PATCH] fix resource end in K8 amdk8/northbridge.c
by Rudolf Marek 14 Oct '07

14 Oct '07

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 This patch fixes the resource end in amdk8/northbridge.c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFG/ZYo3J9wPJqZRNURAgtlAJ9JB2xTVLkl3kaQ37JY2JxZ7PFyeQCfUoH6 kwz4YzvLlUpaeNCUjswi0b4= =uWpJ -----END PGP SIGNATURE-----

4 6

[LinuxBIOS] LZMA compression of kernel image and p7zip (Carl-Daniel Hailfinger / Stefan Reinauer)
by liran tal 11 Oct '07

11 Oct '07

Hey everyone, I have stumbled upon posts by Carl-Daniel and Stefan while trying to get some information why when I compile a kernel image with 7zip (LZMA) the kernel image doesn't load up. The specific post is - http://www.mail-archive.com/linuxbios@linuxbios.org/msg06389.html I figured that maybe you could help diagnosing this problem as it seems that I have found the problem but I am not too sure actually. I have been given an SDK based on Linux 2.6.10 for an embedded mips 4Kec (TI Avalanche series) cpu to build an image from. When I build the image using GZIP (standard) the kernel boots fine but when I choose 7ZIP support for better compression, the 'make ram_zimage' procedure is working successfully but when the image attempts to run off the device (via nfs) it writes: Launching kernel decompressor. Starting LZMA Uncompression Algorithm. Compressed file is LZMA format. Kernel decompressor was successful ... launching kernel. and nothing happens after that. I've been attempting to figure out what is causing the kernel not to load and after reading the post by Carl-Daniel and Stefan about 7zip using different headers than "normal" LZMA sdk I thought that this could be the problem. I understand that this is not the best forum to ask, being a linuxbios mailing-list but I would appreciate your comments and any help on this issue as I am really trying to understand what is going on. Thanks, Sincerely, Liran.

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coreboot September 2007