coreboot December 2007

coreboot@coreboot.org

78 participants
271 discussions

[LinuxBIOS] r535 - LinuxBIOSv3/mainboard/emulation/qemu-x86

by svn＠openbios.org

Author: hailfinger Date: 2007-12-03 21:41:02 +0100 (Mon, 03 Dec 2007) New Revision: 535 Added: LinuxBIOSv3/mainboard/emulation/qemu-x86/initram_printktest.c Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c Log: Ron mentioned he had strange hangs in pll_reset on various targets. This may be due to miscompilation of XIP objects which do not have _MAINBOBJECT defined. This issue was impossible to see on qemu because no such object existed. Introduce initram_printktest.c in the Qemu target, which will test for miscompilation and crash with a descriptive error message. This has been build tested and runtime tested on Qemu, and with my compiler/linker combination it indeed crashes. gcc (GCC) 4.2.1 (SUSE Linux) GNU ld (GNU Binutils) 2.17.50.20070726-14 (SUSE Linux) Trying with gcc-4.1 (GCC) 4.1.3 20070724 (prerelease) (SUSE Linux) and the linker above had exactly the same results. Unless we manage to fix the bug uncovered by this patch, leaving the Qemu target in crashing state is the best thing we can do because this behaviour mirrors the state of all other targets. Ron says: I am comfortable with this. If hardware is broken, qemu should be broken. I avidly wait the fix :-) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-12-03 20:32:53 UTC (rev 534) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-12-03 20:41:02 UTC (rev 535) @@ -28,7 +28,8 @@ # directory and is built from what was auto.c in v2. # -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o +INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ + $(obj)/mainboard/$(MAINBOARDDIR)/initram_printktest.o STAGE2_MAINBOARD_OBJ = vga.o Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c 2007-12-03 20:32:53 UTC (rev 534) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c 2007-12-03 20:41:02 UTC (rev 535) @@ -2,6 +2,7 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2007 Stefan Reinauer <stepan(a)coresystems.de> + * Copyright (C) 2007 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,8 @@ #include <console.h> +int printktest(void); + /* printktest1() is here to increase the likelihood of main() not ending up at * the beginning of the file, so we can check whether the entry point at main() * was honored. @@ -39,6 +42,9 @@ printk(BIOS_INFO, "RAM init code started.\n"); printk(BIOS_INFO, "Nothing to do.\n"); printktest1(); + printk(BIOS_INFO, "Trying absolute call from non-_MAINOBJECT XIP code.\n"); + printktest(); + printk(BIOS_INFO, "Done.\n"); return 0; } Added: LinuxBIOSv3/mainboard/emulation/qemu-x86/initram_printktest.c =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/initram_printktest.c (rev 0) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/initram_printktest.c 2007-12-03 20:41:02 UTC (rev 535) @@ -0,0 +1,31 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console.h> + +int printktest(void) +{ + /* If printk succeeds, it will print the message below. This is not a + * success message after a test, but a success message used as test. + * In case of compiler/linker bugs the printk call is likely to crash. + */ + printk(BIOS_INFO, "Absolute call successful.\n"); + + return 0; +}

13 years, 3 months

[LinuxBIOS] [PATCH] v3: Refactoring, northbridgelib.c

by Uwe Hermann

See patch. Factor out common code. In v2 98% of all northbridges do exactly the same thing (in these functions), thus refactor. It's easy to override the common functions if a northbridge needs slightly different ones (I think K8 will, for example). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

13 years, 3 months

[LinuxBIOS] r534 - in LinuxBIOSv3: arch/x86 include lib northbridge/amd/geodelx northbridge/intel/i440bxemulation

by svn＠openbios.org

Author: uwe Date: 2007-12-03 21:32:53 +0100 (Mon, 03 Dec 2007) New Revision: 534 Added: LinuxBIOSv3/include/northbridgelib.h LinuxBIOSv3/lib/northbridgelib.c Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c Log: Factor out common functions which almost all northbridges share into lib/northbridgelib.c. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-11-30 22:43:42 UTC (rev 533) +++ LinuxBIOSv3/arch/x86/Makefile 2007-12-03 20:32:53 UTC (rev 534) @@ -172,7 +172,7 @@ # STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \ - compute_ip_checksum.o string.o + compute_ip_checksum.o string.o northbridgelib.o STAGE2_ARCH_X86_OBJ = archtables.o linuxbios_table.o udelay_io.o STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o Added: LinuxBIOSv3/include/northbridgelib.h =================================================================== --- LinuxBIOSv3/include/northbridgelib.h (rev 0) +++ LinuxBIOSv3/include/northbridgelib.h 2007-12-03 20:32:53 UTC (rev 534) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +void pci_domain_read_resources(struct device *dev); +void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek); +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); Added: LinuxBIOSv3/lib/northbridgelib.c =================================================================== --- LinuxBIOSv3/lib/northbridgelib.c (rev 0) +++ LinuxBIOSv3/lib/northbridgelib.c 2007-12-03 20:32:53 UTC (rev 534) @@ -0,0 +1,92 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> + +/** + * Set resources for the PCI domain. + * + * A PCI domain contains the I/O and memory resource address space below it. + * Set up basic global ranges for I/O and memory. Allocation of sub-resources + * draws on these top-level resources in the usual hierarchical manner. + * + * @param dev The northbridge device. + */ +void pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->limit = 0xffffUL; + res->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->limit = 0xffffffffULL; + res->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +/** + * Create a RAM resource, by taking the passed-in size and creating + * a resource record. + * + * @param dev The device. + * @param index A resource index. + * @param basek Base memory address in KB. + * @param sizek Size of memory in KB. + */ +void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *res; + + if (!sizek) + return; + + res = new_resource(dev, index); + res->base = ((resource_t) basek) << 10; /* Convert to bytes. */ + res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */ + res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); +} + +/** + * Support for scan bus from the "tippy top" -- i.e. the PCI domain, + * not the 0:0.0 device. + * + * This function works for almost all chipsets (AMD K8 is the exception). + * + * @param dev The PCI domain device. + * @param max Maximum number of devices to scan. + * @return TODO + */ +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) +{ + /* There is only one link on this device, and it is always link 0. */ + return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); +} Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-11-30 22:43:42 UTC (rev 533) +++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-12-03 20:32:53 UTC (rev 534) @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include <msr.h> #include <amd_geodelx.h> +#include <northbridgelib.h> /* Function prototypes */ extern void chipsetinit(void); @@ -270,58 +271,6 @@ } /** - * Set resources for the PCI domain. - * - * Just set up basic global ranges for I/O and memory. Allocation of - * sub-resources draws on these top-level resources in the usual - * hierarchical manner. - * - * @param dev The nortbridge device. - */ -static void geodelx_pci_domain_read_resources(struct device *dev) -{ - struct resource *resource; - - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -/** - * Create a RAM resource, by taking the passed-in size and creating - * a resource record. - * - * @param dev The device. - * @param index A resource index. - * @param basek Base memory address in KB. - * @param sizek Size of memory in KB. - */ -static void ram_resource(struct device *dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; - - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -/** * Set resources in the PCI domain. * * Also, as a side effect, create a RAM resource in the child which, @@ -386,21 +335,6 @@ } /** - * Support for scan bus from the "tippy top" -- i.e. the PCI domain, - * not the 0:0.0 device. - * - * @param dev The PCI domain device. - * @param max Maximum number of devices to scan. - * @return TODO - */ -static unsigned int geodelx_pci_domain_scan_bus(struct device *dev, - unsigned int max) -{ - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); - return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); -} - -/** * Support for APIC cluster init. * * TODO: Should we do this in phase 2? It is now done in phase 6. @@ -426,8 +360,8 @@ static struct device_operations geodelx_pcidomain_ops = { .constructor = default_device_constructor, .phase2_setup_scan_bus = geodelx_pci_domain_phase2, - .phase3_scan = geodelx_pci_domain_scan_bus, - .phase4_read_resources = geodelx_pci_domain_read_resources, + .phase3_scan = pci_domain_scan_bus, + .phase4_read_resources = pci_domain_read_resources, .phase4_set_resources = geodelx_pci_domain_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = 0, @@ -448,8 +382,8 @@ /** Operations for when the northbridge is running a PCI device. */ static struct device_operations geodelx_pci_ops = { .constructor = default_device_constructor, - .phase3_scan = geodelx_pci_domain_scan_bus, - .phase4_read_resources = geodelx_pci_domain_read_resources, + .phase3_scan = pci_domain_scan_bus, + .phase4_read_resources = pci_domain_read_resources, .phase4_set_resources = geodelx_northbridge_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = geodelx_northbridge_init, Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-11-30 22:43:42 UTC (rev 533) +++ LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-12-03 20:32:53 UTC (rev 534) @@ -43,46 +43,12 @@ #include <device/device.h> #include <device/pci.h> #include <string.h> +#include <northbridgelib.h> #include "i440bx.h" #include "statictree.h" /* Here are the ops for 440BX as a PCI domain. */ -/* A PCI domain contains the I/O and memory resource address space below it. */ -static void pci_domain_read_resources(struct device *dev) -{ - struct resource *resource; - - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->limit = 0xffffUL; - resource->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xffffffffULL; - resource->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -static void ram_resource(struct device *dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t) basek) << 10; - resource->size = ((resource_t) sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "%s: add ram resource %lld bytes\n", __func__, - resource->size); -} - static void pci_domain_set_resources(struct device *dev) { struct device *mc_dev; @@ -99,13 +65,6 @@ phase4_assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) -{ - /* There is only one link on this device, and it is always link 0. */ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - /* Here are the operations for when the northbridge is running a PCI domain. */ /* See mainboard/emulation/qemu-x86 for an example of how these are used. */ struct device_operations i440bxemulation_pcidomainops = {

13 years, 3 months

[LinuxBIOS] r72 - buildrom-devel/packages/gpxe

by svn＠openbios.org

Author: jcrouse Date: 2007-12-03 20:06:36 +0100 (Mon, 03 Dec 2007) New Revision: 72 Modified: buildrom-devel/packages/gpxe/gpxe.mk Log: For unknown reasons, gpxe.mk had two copies of itself - that made make very angry. Remove the offending lines. Trivial, no code changes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/gpxe/gpxe.mk =================================================================== --- buildrom-devel/packages/gpxe/gpxe.mk 2007-11-30 21:07:38 UTC (rev 71) +++ buildrom-devel/packages/gpxe/gpxe.mk 2007-12-03 19:06:36 UTC (rev 72) @@ -70,75 +70,3 @@ gpxe-distclean: @ rm -rf $(GPXE_DIR)/* -GPXE_URL=git://git.etherboot.org/scm/gpxe.git -GPXE_DIR=$(BUILD_DIR)/gpxe -GPXE_TAG=master -GPXE_SRC_DIR=$(GPXE_DIR)/gpxe-$(GPXE_TAG)/src -GPXE_SOURCE=gpxe-$(GPXE_TAG).tar.bz2 -GPXE_STAMP_DIR=$(GPXE_DIR)/stamps -GPXE_LOG_DIR=$(GPXE_DIR)/logs - -ifeq ($(GPXE_ARCH),) -GPXE_ARCH=i386 -endif - -GPXE_PATCHES = - -# Filter the quotes off the config string -GPXE_DRIVER := $(shell echo $(CONFIG_GPXE_DRIVER) | sed -e s:\"::g) -GPXE_OUTPUT=$(GPXE_SRC_DIR)/bin/$(GPXE_DRIVER).elf - -ifeq ($(CONFIG_VERBOSE),y) -GPXE_FETCH_LOG=/dev/stdout -GPXE_BUILD_LOG=/dev/stdout -GPXE_INSTALL_LOG=/dev/stdout -else -GPXE_FETCH_LOG=$(GPXE_LOG_DIR)/fetch.log -GPXE_BUILD_LOG=$(GPXE_LOG_DIR)/build.log -GPXE_INSTALL_LOG=$(GPXE_LOG_DIR)/install.log -endif - -$(SOURCE_DIR)/$(GPXE_SOURCE): - @ echo "Fetching the GPXE source..." - $(BIN_DIR)/fetchgit.sh $(GPXE_URL) $(SOURCE_DIR)/gpxe \ - $(GPXE_TAG) $(SOURCE_DIR)/$(GPXE_SOURCE) gpxe \ - > $(GPXE_FETCH_LOG) 2>&1 - -$(GPXE_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(GPXE_SOURCE) - @ echo "Unpacking GPXE..." - @ tar -C $(GPXE_DIR) -jxf $(SOURCE_DIR)/$(GPXE_SOURCE) - @ touch $@ - -$(GPXE_STAMP_DIR)/.patched: $(GPXE_STAMP_DIR)/.unpacked - @ echo "Patching GPXE..." - @ $(BIN_DIR)/doquilt.sh $(GPXE_SRC_DIR)/.. $(GPXE_PATCHES) - @ touch $@ - -$(GPXE_STAMP_DIR)/.configured: $(GPXE_STAMP_DIR)/.patched - @ cp $(PACKAGE_DIR)/gpxe/conf/Config.main \ - $(GPXE_SRC_DIR)/Config - @ cp $(PACKAGE_DIR)/gpxe/conf/Config.$(GPXE_ARCH) \ - $(GPXE_SRC_DIR)/arch/$(GPXE_ARCH)/Config - @ touch $@ - -$(GPXE_OUTPUT): $(GPXE_STAMP_DIR)/.configured - @ echo "Building GPXE..." - @ ( unset CFLAGS; export EXTRA_CFLAGS="$(CFLAGS)"; \ - unset ASFLAGS; export EXTRA_ASFLAGS="$(ASFLAGS)"; \ - unset LDFLAGS; \ - $(MAKE) -C $(GPXE_SRC_DIR) ARCH=$(GPXE_ARCH) \ - bin/$(GPXE_DRIVER).elf > $(GPXE_BUILD_LOG) 2>&1) - -$(GPXE_STAMP_DIR) $(GPXE_LOG_DIR): - @ mkdir -p $@ - -gpxe: $(GPXE_STAMP_DIR) $(GPXE_LOG_DIR) $(GPXE_OUTPUT) - @ mkdir -p $(OUTPUT_DIR) - @ cp $(GPXE_OUTPUT) $(PAYLOAD_ELF) - -gpxe-clean: - @ echo "Cleaning GPXE..." - @ $(MAKE) -C $(GPXE_SRC_DIR) clean > /dev/null 2>&1 - -gpxe-distclean: - @ rm -rf $(GPXE_DIR)/*

13 years, 3 months

[LinuxBIOS] Broken build for kexec-boot-loader in buildrom x86_64?

by Andreas B. Mundt

Hi all, buildrom gives me still an error when building kexec-boot-loader (x86_64) for the m57sli: gcc --32 -c -o kexec/x86-setup-32.o kexec/x86-setup-32.S cc1: error: unrecognized command line option "-f32" This has been reported for the tyan_s2891 before: http://www.linuxbios.org/pipermail/linuxbios/2007-November/026649.html Did I something wrong? Regards Andi

13 years, 3 months

[LinuxBIOS] [PATCH] flashrom: Acorp 6A815EPD board-enable

by jakllsch＠kollasch.net

Hi, This patch adds a board enable for Acorp 6A815EPD. Jonathan Kollasch

13 years, 3 months

[LinuxBIOS] r2995 - trunk/util/flashrom

by svn＠openbios.org

Author: uwe Date: 2007-12-02 20:03:23 +0100 (Sun, 02 Dec 2007) New Revision: 2995 Modified: trunk/util/flashrom/README trunk/util/flashrom/board_enable.c Log: Add board-enable for Acorp 6A815EPD. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/README =================================================================== --- trunk/util/flashrom/README 2007-11-30 02:08:26 UTC (rev 2994) +++ trunk/util/flashrom/README 2007-12-02 19:03:23 UTC (rev 2995) @@ -58,6 +58,7 @@ * GIGABYTE GA-M57SLI-S4 v2.0: use -m gigabyte:m57sli * GIGABYTE GA-M61P-S3: use -m gigabyte:m61p * MSI K8N Neo3: use -m msi:k8n-neo3 +* Acorp 6A815EPD: use -m acorp:6a815epd ROM Layout Support Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2007-11-30 02:08:26 UTC (rev 2994) +++ trunk/util/flashrom/board_enable.c 2007-12-02 19:03:23 UTC (rev 2995) @@ -323,6 +323,32 @@ } /** + * Suited for Acorp 6A815EPD + */ +static int board_acorp_6a815epd(const char *name) +{ + struct pci_dev *dev; + uint16_t port; + uint8_t val; + + dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ + if (!dev) { + fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n"); + return -1; + } + + /* Use GPIOBASE register to find where the GPIO is mapped. */ + port = (pci_read_word(dev, 0x58) & 0xFF80) + 0xE; + + val = inb(port); + val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ + val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ + outb(val, port); + + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -376,6 +402,8 @@ "ibm", "x3455", "IBM x3455", board_ibm_x3455}, {0x8086, 0x7110, 0x0000, 0x0000, 0x8086, 0x7190, 0x0000, 0x0000, "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3}, + {0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33, + "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

13 years, 3 months

[LinuxBIOS] Booting Windows with QEMU+LinuxBIOS

by Jun Koi

Hello, I am playing around with LinuxBIOS. The first step is to boot Windows on QEMU+LinuxBIOS. I follow the steps in http://www.linuxbios.org/Booting_Windows_using_LinuxBIOS, and do with LinuxBIOSv3. However, in the documentation, I read: ..... Building LinuxBIOSv3 Now it is time to build linuxBIOSv3. You should first download it: $ svn co svn://linuxbios.org/repository/LinuxBIOSv3 $ cd LinuxBIOSv3/util $ svn co svn://linuxbios.org/repos/trunk/LinuxBIOSv2/util/ADLO $ Apply patch that puts ADLO into LinuxBIOSv3 $ make menuconfig .... I just dont see how to "apply the patch to put ADLO into LinuxBIOSv3". ADLO was checked out from SVN, but it is a directory, so how can we "apply patch ...." as in the instructions? Thanks, Jun

13 years, 3 months

[LinuxBIOS] USB booting in LinuxBIOS

by Uwe Hermann

[New thread] On Thu, Nov 29, 2007 at 08:25:32PM -0500, Richard Smith wrote: > That said, here in the OLPC offices we have still have periodic pain > involved with USB booting. A lot of usb sticks are just trash. The > generic case requires up to several seconds of delay before you can access > them. I'm curious, what do you use for USB booting? Is it suitable for generic LinuxBIOS use, too? Both FILO and Etherboot seem pretty broken wrt USB at the moment, GRUB2 doesn't have support at all AFAIK. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

13 years, 3 months

[LinuxBIOS] [PATCH] Remove Bitworks IMS

by Corey Osgood

Well, as there seems to be a lot of cleaning up going on lately, might as well add this to the docket. The attached patch removes the Bitworks IMS, as 1) there's no video support for it, 2) no one objected when this was discussed previously, and 3) no one seems to have one, and they aren't readily available. Any comments are welcome. Signed-off-by: Corey Osgood <corey_osgood(a)verizon.net>

13 years, 3 months

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coreboot December 2007