coreboot December 2007

coreboot@coreboot.org

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[LinuxBIOS] [PATCH] v3: fix absolute calls from initram
by Carl-Daniel Hailfinger 04 Dec '07

04 Dec '07

Absolute calls from initram were only working from the file which had _MAINOBJECT #defined. Calls from all other files ended up in nirvana because the compiler was not able to calculate the address of the wrapper for the absolute call. The linker tried, but failed miserably. Use the -combine flag and compile all of initram at once. This enables GCC to calculate the address of the abscall wrapper, resulting in working code. Segher Boessenkool thinks the patched code works only by accident because GCC has no way to specify generation of XIP code. According to him, future GCC versions or other circumstances may break the code. While this patch makes code work for now, it does NOT check whether the generated code tries to write to memory outside the stack (general writable data). That will of course fail, but I hope porters are smart enough to avoid that. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-xiptest-working/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3-xiptest-working/mainboard/adl/msm800sev/Makefile (revision 535) +++ LinuxBIOSv3-xiptest-working/mainboard/adl/msm800sev/Makefile (working copy) @@ -21,10 +21,10 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/southbridge/amd/cs5536/smbus_initram.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Index: LinuxBIOSv3-xiptest-working/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3-xiptest-working/mainboard/amd/norwich/Makefile (revision 535) +++ LinuxBIOSv3-xiptest-working/mainboard/amd/norwich/Makefile (working copy) @@ -21,10 +21,10 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/southbridge/amd/cs5536/smbus_initram.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Index: LinuxBIOSv3-xiptest-working/mainboard/artecgroup/dbe61/Makefile =================================================================== --- LinuxBIOSv3-xiptest-working/mainboard/artecgroup/dbe61/Makefile (revision 535) +++ LinuxBIOSv3-xiptest-working/mainboard/artecgroup/dbe61/Makefile (working copy) @@ -21,8 +21,8 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Index: LinuxBIOSv3-xiptest-working/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3-xiptest-working/mainboard/pcengines/alix1c/Makefile (revision 535) +++ LinuxBIOSv3-xiptest-working/mainboard/pcengines/alix1c/Makefile (working copy) @@ -21,9 +21,9 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Index: LinuxBIOSv3-xiptest-working/mainboard/emulation/qemu-x86/Makefile =================================================================== --- LinuxBIOSv3-xiptest-working/mainboard/emulation/qemu-x86/Makefile (revision 535) +++ LinuxBIOSv3-xiptest-working/mainboard/emulation/qemu-x86/Makefile (working copy) @@ -28,8 +28,8 @@ # directory and is built from what was auto.c in v2. # -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/initram_printktest.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c STAGE2_MAINBOARD_OBJ = vga.o Index: LinuxBIOSv3-xiptest-working/Rules.make =================================================================== --- LinuxBIOSv3-xiptest-working/Rules.make (revision 535) +++ LinuxBIOSv3-xiptest-working/Rules.make (working copy) @@ -78,13 +78,3 @@ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ -# -# RAM initialization code can not be linked at a specific address, -# hence it has to be executed in place (XIP) position independently. -# - -$(obj)/%_xip.o: $(src)/%.c - $(Q)mkdir -p $(dir $@) - $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" - $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@ - Index: LinuxBIOSv3-xiptest-working/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3-xiptest-working/arch/x86/stage1.c (revision 535) +++ LinuxBIOSv3-xiptest-working/arch/x86/stage1.c (working copy) @@ -137,17 +137,17 @@ // find first initram if (check_normal_boot_flag()) { printk(BIOS_DEBUG, "Choosing normal boot.\n"); - ret = execute_in_place(&archive, "normal/initram.o/segment0"); + ret = execute_in_place(&archive, "normal/initram/segment0"); } else { printk(BIOS_DEBUG, "Choosing fallback boot.\n"); - ret = execute_in_place(&archive, "fallback/initram.o/segment0"); + ret = execute_in_place(&archive, "fallback/initram/segment0"); /* Try a normal boot if fallback doesn't exist in the lar. * TODO: There are other ways to do this. * It could be ifdef or the boot flag could be forced. */ if (ret) { printk(BIOS_DEBUG, "Fallback failed. Try normal boot\n"); - ret = execute_in_place(&archive, "normal/initram.o/segment0"); + ret = execute_in_place(&archive, "normal/initram/segment0"); } } Index: LinuxBIOSv3-xiptest-working/arch/x86/Makefile =================================================================== --- LinuxBIOSv3-xiptest-working/arch/x86/Makefile (revision 535) +++ LinuxBIOSv3-xiptest-working/arch/x86/Makefile (working copy) @@ -36,7 +36,7 @@ ROM_SIZE := $(shell expr $(CONFIG_LINUXBIOS_ROMSIZE_KB) \* 1024) -LARFILES := nocompress:normal/initram.o normal/stage2.o nocompress:normal/option_table +LARFILES := nocompress:normal/initram normal/stage2.o nocompress:normal/option_table ifneq ($(CONFIG_PAYLOAD_NONE),y) LARFILES += normal/payload endif @@ -57,11 +57,11 @@ COMPRESSFLAG := -C nrv2b endif -$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram.o $(obj)/linuxbios.stage2.o $(obj)/option_table +$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram $(obj)/linuxbios.stage2.o $(obj)/option_table $(Q)rm -rf $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp/normal - $(Q)cp $(obj)/linuxbios.initram.o $(obj)/lar.tmp/normal/initram.o + $(Q)cp $(obj)/linuxbios.initram $(obj)/lar.tmp/normal/initram $(Q)cp $(obj)/linuxbios.stage2.o $(obj)/lar.tmp/normal/stage2.o $(Q)cp $(obj)/option_table $(obj)/lar.tmp/normal/option_table ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -232,12 +232,14 @@ $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@ -$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ) + $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/linuxbios.initram_partiallylinked.o $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ - $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o + $(obj)/linuxbios.initram_partiallylinked.o -o $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map + $(Q)$(NM) $(obj)/linuxbios.initram | sort -u > $(obj)/linuxbios.initram.map endif

3 5

[LinuxBIOS] r537 - in LinuxBIOSv3: . arch/x86 mainboard/adl/msm800sev mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c
by svn＠openbios.org 04 Dec '07

04 Dec '07

Author: hailfinger Date: 2007-12-04 23:42:38 +0100 (Tue, 04 Dec 2007) New Revision: 537 Modified: LinuxBIOSv3/Rules.make LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/arch/x86/stage1.c LinuxBIOSv3/mainboard/adl/msm800sev/Makefile LinuxBIOSv3/mainboard/amd/norwich/Makefile LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile Log: Absolute calls from initram were only working from the file which had _MAINOBJECT #defined. Calls from all other files ended up in nirvana because the compiler was not able to calculate the address of the wrapper for the absolute call. The linker tried, but failed miserably. Use the -combine flag and compile all of initram at once. This enables GCC to calculate the address of the abscall wrapper, resulting in working code. Segher Boessenkool thinks the patched code works only by accident because GCC has no way to specify generation of XIP code. According to him, future GCC versions or other circumstances may break the code. While this patch makes code work for now, it does NOT check whether the generated code tries to write to memory outside the stack (general writable data). That will of course fail, but I hope porters are smart enough to avoid that. Corey Osgood writes: Great work tracking this down! This is okay for now, but we need to look for a better solution in the future. Counting on porters who may or may not remember this discussion to avoid something isn't good future-proofing. Checking the ELF sections for read-write data and stopping the build with an error could make this future-proof. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: LinuxBIOSv3/Rules.make =================================================================== --- LinuxBIOSv3/Rules.make 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/Rules.make 2007-12-04 22:42:38 UTC (rev 537) @@ -78,13 +78,3 @@ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ -# -# RAM initialization code can not be linked at a specific address, -# hence it has to be executed in place (XIP) position independently. -# - -$(obj)/%_xip.o: $(src)/%.c - $(Q)mkdir -p $(dir $@) - $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" - $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c $< -o $@ - Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/arch/x86/Makefile 2007-12-04 22:42:38 UTC (rev 537) @@ -36,7 +36,7 @@ ROM_SIZE := $(shell expr $(CONFIG_LINUXBIOS_ROMSIZE_KB) \* 1024) -LARFILES := nocompress:normal/initram.o normal/stage2.o nocompress:normal/option_table +LARFILES := nocompress:normal/initram normal/stage2.o nocompress:normal/option_table ifneq ($(CONFIG_PAYLOAD_NONE),y) LARFILES += normal/payload endif @@ -57,11 +57,11 @@ COMPRESSFLAG := -C nrv2b endif -$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram.o $(obj)/linuxbios.stage2.o $(obj)/option_table +$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram $(obj)/linuxbios.stage2.o $(obj)/option_table $(Q)rm -rf $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp/normal - $(Q)cp $(obj)/linuxbios.initram.o $(obj)/lar.tmp/normal/initram.o + $(Q)cp $(obj)/linuxbios.initram $(obj)/lar.tmp/normal/initram $(Q)cp $(obj)/linuxbios.stage2.o $(obj)/lar.tmp/normal/stage2.o $(Q)cp $(obj)/option_table $(obj)/lar.tmp/normal/option_table ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -232,12 +232,14 @@ $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@ -$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ) + $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/linuxbios.initram_partiallylinked.o $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ - $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o + $(obj)/linuxbios.initram_partiallylinked.o -o $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map + $(Q)$(NM) $(obj)/linuxbios.initram | sort -u > $(obj)/linuxbios.initram.map endif Modified: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/arch/x86/stage1.c 2007-12-04 22:42:38 UTC (rev 537) @@ -137,17 +137,17 @@ // find first initram if (check_normal_boot_flag()) { printk(BIOS_DEBUG, "Choosing normal boot.\n"); - ret = execute_in_place(&archive, "normal/initram.o/segment0"); + ret = execute_in_place(&archive, "normal/initram/segment0"); } else { printk(BIOS_DEBUG, "Choosing fallback boot.\n"); - ret = execute_in_place(&archive, "fallback/initram.o/segment0"); + ret = execute_in_place(&archive, "fallback/initram/segment0"); /* Try a normal boot if fallback doesn't exist in the lar. * TODO: There are other ways to do this. * It could be ifdef or the boot flag could be forced. */ if (ret) { printk(BIOS_DEBUG, "Fallback failed. Try normal boot\n"); - ret = execute_in_place(&archive, "normal/initram.o/segment0"); + ret = execute_in_place(&archive, "normal/initram/segment0"); } } Modified: LinuxBIOSv3/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-12-04 22:42:38 UTC (rev 537) @@ -21,10 +21,10 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/southbridge/amd/cs5536/smbus_initram.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Modified: LinuxBIOSv3/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-12-04 22:42:38 UTC (rev 537) @@ -21,10 +21,10 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/southbridge/amd/cs5536/smbus_initram.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/southbridge/amd/cs5536/smbus_initram.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile =================================================================== --- LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-12-04 22:42:38 UTC (rev 537) @@ -21,8 +21,8 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ = Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-12-04 22:42:38 UTC (rev 537) @@ -28,8 +28,8 @@ # directory and is built from what was auto.c in v2. # -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/initram_printktest.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c STAGE2_MAINBOARD_OBJ = vga.o Modified: LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile 2007-12-04 21:06:52 UTC (rev 536) +++ LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile 2007-12-04 22:42:38 UTC (rev 537) @@ -21,9 +21,9 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/arch/x86/geodelx/geodelx.o +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/arch/x86/geodelx/geodelx.c STAGE2_MAINBOARD_OBJ =

1 0

[LinuxBIOS] Add iso9660 support to LAB kernel for serengeti-cheetah
by Myles Watson 04 Dec '07

04 Dec '07

This is a trivial patch that adds support for iso9660 file systems to the LAB kernel for serengeti-cheetah. Myles Signed-off-by: Myles Watson <myles(a)pel.cs.byu.edu>

1 0

[LinuxBIOS] r2997 - trunk/util/flashrom
by svn＠openbios.org 04 Dec '07

04 Dec '07

Author: uwe Date: 2007-12-04 22:49:06 +0100 (Tue, 04 Dec 2007) New Revision: 2997 Modified: trunk/util/flashrom/board_enable.c trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/flash.h Log: Various coding style fixes, constification, fixed typos (trivial). Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2007-12-04 01:15:29 UTC (rev 2996) +++ trunk/util/flashrom/board_enable.c 2007-12-04 21:49:06 UTC (rev 2997) @@ -50,13 +50,13 @@ static unsigned char wbsio_read(uint16_t index, uint8_t reg) { outb(reg, index); - return inb(index+1); + return inb(index + 1); } static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { outb(reg, index); - outb(data, index+1); + outb(data, index + 1); } static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) @@ -64,8 +64,8 @@ uint8_t tmp; outb(reg, index); - tmp = inb(index+1) & ~mask; - outb(tmp | (data & mask), index+1); + tmp = inb(index + 1) & ~mask; + outb(tmp | (data & mask), index + 1); } /** @@ -79,8 +79,8 @@ { w836xx_ext_enter(index); - /* Is this the w83627hf? */ - if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID register */ + /* Is this the W83627HF? */ + if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID reg. */ fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", name, wbsio_read(index, 0x20)); w836xx_ext_leave(index); @@ -90,14 +90,12 @@ /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ wbsio_mask(index, 0x2B, 0x10, 0x10); - wbsio_write(index, 0x07, 0x08); /* Select logical device 8: GPIO port 2 */ + /* Select logical device 8: GPIO port 2 */ + wbsio_write(index, 0x07, 0x08); wbsio_mask(index, 0x30, 0x01, 0x01); /* Activate logical device. */ - wbsio_mask(index, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ - wbsio_mask(index, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ - wbsio_mask(index, 0xF1, 0x10, 0x10); /* Raise GPIO24 */ w836xx_ext_leave(index); @@ -107,6 +105,7 @@ static int w83627hf_gpio24_raise_2e(const char *name) { + /* TODO: Typo? Shouldn't this be 0x2e? */ return w83627hf_gpio24_raise(0x2d, name); } @@ -119,8 +118,9 @@ static int w83627thf_gpio4_4_raise(uint16_t index, const char *name) { w836xx_ext_enter(index); - /* Is this the w83627thf? */ - if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID register */ + + /* Is this the W83627THF? */ + if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID reg. */ fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", name, wbsio_read(index, 0x20)); w836xx_ext_leave(index); @@ -129,16 +129,12 @@ /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ - wbsio_write(index, 0x07, 0x09); /* Select logical device 9: GPIO port 4 */ + wbsio_write(index, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */ + wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */ + wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ + wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ + wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ - wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */ - - wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ - - wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ - - wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ - w836xx_ext_leave(index); return 0; @@ -146,8 +142,9 @@ static int w83627thf_gpio4_4_raise_4e(const char *name) { - return w83627thf_gpio4_4_raise(0x4E, name); + return w83627thf_gpio4_4_raise(0x4e, name); } + /** * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. * @@ -156,7 +153,7 @@ static int board_via_epia_m(const char *name) { struct pci_dev *dev; - unsigned int base; + uint16_t base; uint8_t val; dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ @@ -173,7 +170,7 @@ /* Get Power Management IO address. */ base = pci_read_word(dev, 0x88) & 0xFF80; - /* enable GPIO15 which is connected to write protect. */ + /* Enable GPIO15 which is connected to write protect. */ val = inb(base + 0x4D); val |= 0x80; outb(val, base + 0x4D); @@ -199,16 +196,16 @@ return -1; } - /* This bit is marked reserved actually */ + /* This bit is marked reserved actually. */ val = pci_read_byte(dev, 0x59); val &= 0x7F; pci_write_byte(dev, 0x59, val); - /* Raise ROM MEMW# line on Winbond w83697 SuperIO */ + /* Raise ROM MEMW# line on Winbond W83697 Super I/O. */ w836xx_ext_enter(0x2E); - if (!(wbsio_read(0x2E, 0x24) & 0x02)) /* flash rom enabled? */ - wbsio_mask(0x2E, 0x24, 0x08, 0x08); /* enable MEMW# */ + if (!(wbsio_read(0x2E, 0x24) & 0x02)) /* Flash ROM enabled? */ + wbsio_mask(0x2E, 0x24, 0x08, 0x08); /* Enable MEMW#. */ w836xx_ext_leave(0x2E); @@ -323,7 +320,7 @@ } /** - * Suited for Acorp 6A815EPD + * Suited for Acorp 6A815EPD. */ static int board_acorp_6a815epd(const char *name) { @@ -338,7 +335,7 @@ } /* Use GPIOBASE register to find where the GPIO is mapped. */ - port = (pci_read_word(dev, 0x58) & 0xFF80) + 0xE; + port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; val = inb(port); val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ @@ -357,25 +354,25 @@ * Keep the second set NULLed if it should be ignored. */ struct board_pciid_enable { - /* Any device, but make it sensible, like the isa bridge. */ + /* Any device, but make it sensible, like the ISA bridge. */ uint16_t first_vendor; uint16_t first_device; uint16_t first_card_vendor; uint16_t first_card_device; /* Any device, but make it sensible, like - * the host bridge. May be NULL + * the host bridge. May be NULL. */ uint16_t second_vendor; uint16_t second_device; uint16_t second_card_vendor; uint16_t second_card_device; - /* From linuxbios table */ - char *lb_vendor; - char *lb_part; + /* The vendor / part name from the LinuxBIOS table. */ + const char *lb_vendor; + const char *lb_part; - char *name; + const char *name; int (*enable) (const char *name); }; @@ -411,8 +408,7 @@ * Match boards on LinuxBIOS table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static struct board_pciid_enable *board_match_linuxbios_name(char *vendor, - char *part) +static struct board_pciid_enable *board_match_linuxbios_name(const char *vendor, const char *part) { struct board_pciid_enable *board = board_pciid_enables; @@ -431,7 +427,9 @@ continue; return board; } + printf("NOT FOUND %s:%s\n", vendor, part); + return NULL; } @@ -472,7 +470,7 @@ return NULL; } -int board_flash_enable(char *vendor, char *part) +int board_flash_enable(const char *vendor, const char *part) { struct board_pciid_enable *board = NULL; int ret = 0; Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2007-12-04 01:15:29 UTC (rev 2996) +++ trunk/util/flashrom/chipset_enable.c 2007-12-04 21:49:06 UTC (rev 2997) @@ -34,12 +34,14 @@ #include <unistd.h> #include "flash.h" -static int enable_flash_ali_m1533(struct pci_dev *dev, char *name) +static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; - /* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and - 0xFFFE0000-0xFFFFFFFF ROM select enable. */ + /* + * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and + * 0xFFFE0000-0xFFFFFFFF ROM select enable. + */ tmp = pci_read_byte(dev, 0x47); tmp |= 0x46; pci_write_byte(dev, 0x47, tmp); @@ -47,24 +49,28 @@ return 0; } -static int enable_flash_sis630(struct pci_dev *dev, char *name) +static int enable_flash_sis630(struct pci_dev *dev, const char *name) { - char b; + uint8_t b; - /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */ + /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ b = pci_read_byte(dev, 0x40); pci_write_byte(dev, 0x40, b | 0xb); - /* Flash write enable on SiS 540/630 */ + + /* Flash write enable on SiS 540/630. */ b = pci_read_byte(dev, 0x45); pci_write_byte(dev, 0x45, b | 0x40); - /* The same thing on SiS 950 SuperIO side */ + /* The same thing on SiS 950 Super I/O side... */ + + /* First probe for Super I/O on config port 0x2e. */ outb(0x87, 0x2e); outb(0x01, 0x2e); outb(0x55, 0x2e); outb(0x55, 0x2e); if (inb(0x2f) != 0x87) { + /* If that failed, try config port 0x4e. */ outb(0x87, 0x4e); outb(0x01, 0x4e); outb(0x55, 0x4e); @@ -99,7 +105,7 @@ * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Order Number: 290562-001 */ -static int enable_flash_piix4(struct pci_dev *dev, char *name) +static int enable_flash_piix4(struct pci_dev *dev, const char *name) { uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ @@ -132,23 +138,19 @@ return 0; } -static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl) +/* + * See ie. page 375 of "Intel ICH7 External Design Specification" + * http://download.intel.com/design/chipsets/datashts/30701302.pdf + */ +static int enable_flash_ich(struct pci_dev *dev, const char *name, + int bios_cntl) { - /* register 4e.b gets or'ed with one */ uint8_t old, new; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but + /* + * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but * just treating it as 8 bit wide seems to work fine in practice. */ - - /* see ie. page 375 of "Intel ICH7 External Design Specification" - * http://download.intel.com/design/chipsets/datashts/30701302.pdf - */ - old = pci_read_byte(dev, bios_cntl); new = old | 1; @@ -166,17 +168,17 @@ return 0; } -static int enable_flash_ich_4e(struct pci_dev *dev, char *name) +static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) { return enable_flash_ich(dev, name, 0x4e); } -static int enable_flash_ich_dc(struct pci_dev *dev, char *name) +static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { return enable_flash_ich(dev, name, 0xdc); } -static int enable_flash_vt823x(struct pci_dev *dev, char *name) +static int enable_flash_vt823x(struct pci_dev *dev, const char *name) { uint8_t val; @@ -194,7 +196,7 @@ return 0; } -static int enable_flash_cs5530(struct pci_dev *dev, char *name) +static int enable_flash_cs5530(struct pci_dev *dev, const char *name) { uint8_t reg8; @@ -224,7 +226,7 @@ return 0; } -static int enable_flash_cs5536(struct pci_dev *dev, char *name) +static int enable_flash_cs5536(struct pci_dev *dev, const char *name) { int fd_msr; unsigned char buf[8]; @@ -233,15 +235,15 @@ /* Geode systems write protect the BIOS via RCONFs (cache * settings similar to MTRRs). To unlock, change MSR 0x1808 * top byte to 0x22. Reading and writing to msr, however - * requires instrucitons rdmsr/wrmsr, which are ring0 privileged + * requires instructions rdmsr/wrmsr, which are ring0 privileged * instructions so only the kernel can do the read/write. This * function, therefore, requires that the msr kernel module be * loaded to access these instructions from user space using * device /dev/cpu/0/msr. This hard-coded driver location * could have potential problems on SMP machines since it - * assumes cpu0, but it is safe on the geode which is not SMP. + * assumes cpu0, but it is safe on the Geode which is not SMP. * - * This is probably not portable beyond linux. + * This is probably not portable beyond Linux. */ fd_msr = open("/dev/cpu/0/msr", O_RDONLY); @@ -272,7 +274,7 @@ return 0; } -static int enable_flash_sc1100(struct pci_dev *dev, char *name) +static int enable_flash_sc1100(struct pci_dev *dev, const char *name) { uint8_t new; @@ -288,16 +290,14 @@ return 0; } -static int enable_flash_sis5595(struct pci_dev *dev, char *name) +static int enable_flash_sis5595(struct pci_dev *dev, const char *name) { uint8_t new, newer; new = pci_read_byte(dev, 0x45); - /* clear bit 5 */ - new &= (~0x20); - /* set bit 2 */ - new |= 0x4; + new &= (~0x20); /* Clear bit 5. */ + new |= 0x4; /* Set bit 2. */ pci_write_byte(dev, 0x45, new); @@ -311,16 +311,11 @@ return 0; } -static int enable_flash_amd8111(struct pci_dev *dev, char *name) +static int enable_flash_amd8111(struct pci_dev *dev, const char *name) { - /* register 4e.b gets or'ed with one */ uint8_t old, new; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* enable decoding at 0xffb00000 to 0xffffffff */ + /* Enable decoding at 0xffb00000 to 0xffffffff. */ old = pci_read_byte(dev, 0x43); new = old | 0xC0; if (new != old) { @@ -344,17 +339,10 @@ return 0; } -static int enable_flash_ck804(struct pci_dev *dev, char *name) +static int enable_flash_ck804(struct pci_dev *dev, const char *name) { - /* register 4e.b gets or'ed with one */ uint8_t old, new; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* dump_pci_device(dev); */ - old = pci_read_byte(dev, 0x88); new = old | 0xc0; if (new != old) { @@ -378,14 +366,14 @@ return 0; } -static int enable_flash_sb400(struct pci_dev *dev, char *name) +/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ +static int enable_flash_sb400(struct pci_dev *dev, const char *name) { uint8_t tmp; - struct pci_filter f; struct pci_dev *smbusdev; - /* then look for the smbus device */ + /* Look for the SMBus device. */ pci_filter_init((struct pci_access *)0, &f); f.vendor = 0x1002; f.device = 0x4372; @@ -397,21 +385,21 @@ } if (!smbusdev) { - fprintf(stderr, "ERROR: SMBus device not found. aborting\n"); + fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); exit(1); } - /* enable some smbus stuff */ + /* Enable some SMBus stuff. */ tmp = pci_read_byte(smbusdev, 0x79); tmp |= 0x01; pci_write_byte(smbusdev, 0x79, tmp); - /* change southbridge */ + /* Change southbridge. */ tmp = pci_read_byte(dev, 0x48); tmp |= 0x21; pci_write_byte(dev, 0x48, tmp); - /* now become a bit silly. */ + /* Now become a bit silly. */ tmp = inb(0xc6f); outb(tmp, 0xeb); outb(tmp, 0xeb); @@ -423,19 +411,12 @@ return 0; } -static int enable_flash_mcp55(struct pci_dev *dev, char *name) +static int enable_flash_mcp55(struct pci_dev *dev, const char *name) { - /* register 4e.b gets or'ed with one */ - unsigned char old, new, byte; - unsigned short word; + uint8_t old, new, byte; + uint16_t word; - /* if it fails, it fails. There are so many variations of broken mobos - * that it is hard to argue that we should quit at this point. - */ - - /* dump_pci_device(dev); */ - - /* Set the 0-16 MB enable bits */ + /* Set the 0-16 MB enable bits. */ byte = pci_read_byte(dev, 0x88); byte |= 0xff; /* 256K */ pci_write_byte(dev, 0x88, byte); @@ -462,7 +443,7 @@ return 0; } -static int enable_flash_ht1000(struct pci_dev *dev, char *name) +static int enable_flash_ht1000(struct pci_dev *dev, const char *name) { uint8_t byte; @@ -479,12 +460,12 @@ } typedef struct penable { - unsigned short vendor, device; - char *name; - int (*doit) (struct pci_dev * dev, char *name); + uint16_t vendor, device; + const char *name; + int (*doit) (struct pci_dev *dev, const char *name); } FLASH_ENABLE; -static FLASH_ENABLE enables[] = { +static const FLASH_ENABLE enables[] = { {0x1039, 0x0630, "SIS630", enable_flash_sis630}, {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4}, {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, @@ -517,17 +498,14 @@ {0x1022, 0x2080, "AMD GEODE CS5536", enable_flash_cs5536}, {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, - /* this fallthrough looks broken. */ {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */ - {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804}, {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804}, - - {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */ + {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI-S4 */ {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ @@ -535,19 +513,18 @@ {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ - - {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ - + {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, }; int chipset_flash_enable(void) { struct pci_dev *dev = 0; - int ret = -2; /* nothing! */ + int ret = -2; /* Nothing! */ int i; - /* now let's try to find the chipset we have ... */ + /* Now let's try to find the chipset we have... */ + /* TODO: Use ARRAY_SIZE. */ for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) { dev = pci_dev_find(enables[i].vendor, enables[i].device); if (dev) Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2007-12-04 01:15:29 UTC (rev 2996) +++ trunk/util/flashrom/flash.h 2007-12-04 21:49:06 UTC (rev 2997) @@ -31,7 +31,7 @@ #include <stdio.h> struct flashchip { - char *name; + const char *name; int manufacture_id; int model_id; @@ -43,18 +43,18 @@ int (*write) (struct flashchip *flash, uint8_t *buf); int (*read) (struct flashchip *flash, uint8_t *buf); - /* some flash devices have an additional - * register space - */ + /* Some flash devices have an additional register space. */ volatile uint8_t *virtual_memory; volatile uint8_t *virtual_registers; }; extern struct flashchip flashchips[]; -/* Please keep this list sorted alphabetically by manufacturer. The first +/* + * Please keep this list sorted alphabetically by manufacturer. The first * entry of each section should be the manufacturer ID, followed by the * list of devices from that manufacturer (sorted by device IDs). + * * All LPC/FWH parts (parallel flash) have 8-bit device IDs. * All SPI parts have 16-bit device IDs. */ @@ -80,9 +80,11 @@ #define EMST_ID 0x8C /* EMST / EFST */ #define EMST_F49B002UA 0x00 +/* + * EN25 chips are SPI, first byte of device ID is memory type, + * second byte of device ID is log(bitsize)-9. + */ #define EON_ID 0x1C /* EON */ -/* EN25 chips are SPI, first byte of device id is memory type, - * second byte of device id is log(bitsize)-9. */ #define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */ #define EN_25B10 0x2011 #define EN_25B20 0x2012 @@ -103,13 +105,15 @@ #define ISSI_ID 0xD5 /* ISSI */ #define MSYSTEMS_ID 0x156F /* M-Systems */ -#define MSYSTEMS_MD2200 0xDB /* ? */ +#define MSYSTEMS_MD2200 0xDB #define MSYSTEMS_MD2800 0x30 /* hmm -- both 0x30 */ #define MSYSTEMS_MD2802 0x30 /* hmm -- both 0x30 */ +/* + * MX25 chips are SPI, first byte of device ID is memory type, + * second byte of device ID is log(bitsize)-9. + */ #define MX_ID 0xC2 /* Macronix (MX) */ -/* MX25 chips are SPI, first byte of device id is memory type, - * second byte of device id is log(bitsize)-9. */ #define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */ #define MX_25L1005 0x2011 #define MX_25L2005 0x2012 @@ -129,9 +133,11 @@ #define SHARP_ID 0xB0 /* Sharp */ #define SHARP_LHF00L04 0xCF +/* + * SST25 chips are SPI, first byte of device ID is memory type, second + * byte of device ID is related to log(bitsize) at least for some chips. + */ #define SST_ID 0xBF /* SST */ -/* SST25 chips are SPI, first byte of device id is memory type, second - * byte of device id is related to log(bitsize) at least for some chips. */ #define SST_25WF512 0x2501 #define SST_25WF010 0x2502 #define SST_25WF020 0x2503 @@ -196,22 +202,23 @@ #define W_49V002A 0xB0 #define W_49V002FA 0x32 -/* function prototypes from udelay.h */ - +/* udelay.c */ void myusec_delay(int time); void myusec_calibrate_delay(); -/* pci handling for board/chipset_enable */ -struct pci_access *pacc; /* For board and chipset_enable */ +/* PCI handling for board/chipset_enable */ +struct pci_access *pacc; struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); -int board_flash_enable(char *vendor, char *part); /* board_enable.c */ -int chipset_flash_enable(void); /* chipset_enable.c */ +/* board_enable.c */ +int board_flash_enable(const char *vendor, const char *part); -/* physical memory mapping device */ +/* chipset_enable.c */ +int chipset_flash_enable(void); +/* Physical memory mapping device */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) # define MEM_DEV "/dev/xsvc" #else

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[LinuxBIOS] [PATCH] Move northbridgelib.c code to pci_device.c
by Uwe Hermann 04 Dec '07

04 Dec '07

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[LinuxBIOS] r536 - in LinuxBIOSv3: arch/x86 device include include/device lib northbridge/amd/geodelx northbridge/intel/i440bxemulation
by svn＠openbios.org 04 Dec '07

04 Dec '07

Author: uwe Date: 2007-12-04 22:06:52 +0100 (Tue, 04 Dec 2007) New Revision: 536 Removed: LinuxBIOSv3/include/northbridgelib.h LinuxBIOSv3/lib/northbridgelib.c Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/device/pci_device.c LinuxBIOSv3/include/device/pci.h LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c Log: Move the code from northbridgelib.c to pci_device.c. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/arch/x86/Makefile 2007-12-04 21:06:52 UTC (rev 536) @@ -172,7 +172,7 @@ # STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \ - compute_ip_checksum.o string.o northbridgelib.o + compute_ip_checksum.o string.o STAGE2_ARCH_X86_OBJ = archtables.o linuxbios_table.o udelay_io.o STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o Modified: LinuxBIOSv3/device/pci_device.c =================================================================== --- LinuxBIOSv3/device/pci_device.c 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/device/pci_device.c 2007-12-04 21:06:52 UTC (rev 536) @@ -449,6 +449,32 @@ pci_get_rom_resource(dev, PCI_ROM_ADDRESS1); } +/** + * Set resources for the PCI domain. + * + * A PCI domain contains the I/O and memory resource address space below it. + * Set up basic global ranges for I/O and memory. Allocation of sub-resources + * draws on these top-level resources in the usual hierarchical manner. + * + * @param dev The northbridge device. + */ +void pci_domain_read_resources(struct device *dev) +{ + struct resource *res; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->limit = 0xffffUL; + res->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->limit = 0xffffffffULL; + res->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + static void pci_set_resource(struct device *dev, struct resource *resource) { resource_t base, end; @@ -580,6 +606,32 @@ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); } +/** + * Create a RAM resource, by taking the passed-in size and creating + * a resource record. + * + * @param dev The device. + * @param index A resource index. + * @param basek Base memory address in KB. + * @param sizek Size of memory in KB. + */ +void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *res; + + if (!sizek) + return; + + res = new_resource(dev, index); + res->base = ((resource_t) basek) << 10; /* Convert to bytes. */ + res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */ + res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); +} + void pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; @@ -1108,6 +1160,22 @@ } /** + * Support for scan bus from the "tippy top" -- i.e. the PCI domain, + * not the 0:0.0 device. + * + * This function works for almost all chipsets (AMD K8 is the exception). + * + * @param dev The PCI domain device. + * @param max Maximum number of devices to scan. + * @return TODO + */ +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) +{ + /* There is only one link on this device, and it is always link 0. */ + return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); +} + +/** * Scan a PCI bridge and the buses behind the bridge. * * Determine the existence of buses behind the bridge. Set up the bridge Modified: LinuxBIOSv3/include/device/pci.h =================================================================== --- LinuxBIOSv3/include/device/pci.h 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/include/device/pci.h 2007-12-04 21:06:52 UTC (rev 536) @@ -94,6 +94,12 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned device); +void pci_domain_read_resources(struct device *dev); +void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek); +unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); + + #define PCI_IO_BRIDGE_ALIGN 4096 #define PCI_MEM_BRIDGE_ALIGN (1024*1024) Deleted: LinuxBIOSv3/include/northbridgelib.h =================================================================== --- LinuxBIOSv3/include/northbridgelib.h 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/include/northbridgelib.h 2007-12-04 21:06:52 UTC (rev 536) @@ -1,26 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> - -void pci_domain_read_resources(struct device *dev); -void ram_resource(struct device *dev, unsigned long index, - unsigned long basek, unsigned long sizek); -unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); Deleted: LinuxBIOSv3/lib/northbridgelib.c =================================================================== --- LinuxBIOSv3/lib/northbridgelib.c 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/lib/northbridgelib.c 2007-12-04 21:06:52 UTC (rev 536) @@ -1,92 +0,0 @@ -/* - * This file is part of the LinuxBIOS project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <console.h> -#include <device/device.h> -#include <device/pci.h> - -/** - * Set resources for the PCI domain. - * - * A PCI domain contains the I/O and memory resource address space below it. - * Set up basic global ranges for I/O and memory. Allocation of sub-resources - * draws on these top-level resources in the usual hierarchical manner. - * - * @param dev The northbridge device. - */ -void pci_domain_read_resources(struct device *dev) -{ - struct resource *res; - - /* Initialize the system-wide I/O space constraints. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->limit = 0xffffUL; - res->flags = - IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system-wide memory resources constraints. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->limit = 0xffffffffULL; - res->flags = - IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -/** - * Create a RAM resource, by taking the passed-in size and creating - * a resource record. - * - * @param dev The device. - * @param index A resource index. - * @param basek Base memory address in KB. - * @param sizek Size of memory in KB. - */ -void ram_resource(struct device *dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *res; - - if (!sizek) - return; - - res = new_resource(dev, index); - res->base = ((resource_t) basek) << 10; /* Convert to bytes. */ - res->size = ((resource_t) sizek) << 10; /* Convert to bytes. */ - res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); -} - -/** - * Support for scan bus from the "tippy top" -- i.e. the PCI domain, - * not the 0:0.0 device. - * - * This function works for almost all chipsets (AMD K8 is the exception). - * - * @param dev The PCI domain device. - * @param max Maximum number of devices to scan. - * @return TODO - */ -unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) -{ - /* There is only one link on this device, and it is always link 0. */ - return pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); -} Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/northbridge/amd/geodelx/geodelx.c 2007-12-04 21:06:52 UTC (rev 536) @@ -25,7 +25,6 @@ #include <device/pci_ids.h> #include <msr.h> #include <amd_geodelx.h> -#include <northbridgelib.h> /* Function prototypes */ extern void chipsetinit(void); Modified: LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-12-03 20:41:02 UTC (rev 535) +++ LinuxBIOSv3/northbridge/intel/i440bxemulation/i440bx.c 2007-12-04 21:06:52 UTC (rev 536) @@ -43,7 +43,6 @@ #include <device/device.h> #include <device/pci.h> #include <string.h> -#include <northbridgelib.h> #include "i440bx.h" #include "statictree.h"

1 0

[LinuxBIOS] r73 - in buildrom-devel: config/platforms packages/filo/conf
by svn＠openbios.org 04 Dec '07

04 Dec '07

Author: ward Date: 2007-12-04 20:17:07 +0100 (Tue, 04 Dec 2007) New Revision: 73 Modified: buildrom-devel/config/platforms/supermicro-h8dmr.conf buildrom-devel/packages/filo/conf/supermicro-h8dmr-Config Log: This patch applies to the Supermicro H8DMR board. It upgrades the linuxbios version used to 2996 so that we can use a VGA option rom. It also fixes the devices FILO looks on to find the grub config file to hde1, which is what the first drive is recognized as on an MCP55-based board like this one. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/supermicro-h8dmr.conf =================================================================== --- buildrom-devel/config/platforms/supermicro-h8dmr.conf 2007-12-03 19:06:36 UTC (rev 72) +++ buildrom-devel/config/platforms/supermicro-h8dmr.conf 2007-12-04 19:17:07 UTC (rev 73) @@ -40,7 +40,7 @@ LINUXBIOS_BOARD=h8dmr LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=h8dmr -LINUXBIOS_TAG=2994 +LINUXBIOS_TAG=2996 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/packages/filo/conf/supermicro-h8dmr-Config =================================================================== --- buildrom-devel/packages/filo/conf/supermicro-h8dmr-Config 2007-12-03 19:06:36 UTC (rev 72) +++ buildrom-devel/packages/filo/conf/supermicro-h8dmr-Config 2007-12-04 19:17:07 UTC (rev 73) @@ -1,7 +1,7 @@ # Use grub instead of autoboot? USE_GRUB = 1 # Grub menu.lst path -MENULST_FILE = "hda1:/boot/grub/menu.lst" +MENULST_FILE = "hde1:/boot/grub/menu.lst" # Driver for hard disk, CompactFlash, and CD-ROM on IDE bus IDE_DISK = 1 # Add a short delay when polling status registers

1 0

[LinuxBIOS] Help with meaning of config options.
by Steve Isaacs 04 Dec '07

04 Dec '07

When I look at the options passed to the compiler on the command line I see the following: -DCONFIG_MAX_CPUS='4' -DCONFIG_MAX_PHYSICAL_CPUS='2' -DCONFIG_LOGICAL_CPUS='1' Can someone help me understand what the difference between these is? I'm working with two dual core opterons and this doesn't seem right to me. Steve

2 3

Re: [LinuxBIOS] r534 - in LinuxBIOSv3: arch/x86 include lib northbridge/amd/geodelx northbridge/intel/i440bxemulation
by Stefan Reinauer 04 Dec '07

04 Dec '07

* svn(a)openbios.org <svn(a)openbios.org> [071203 21:32]: > Author: uwe > Date: 2007-12-03 21:32:53 +0100 (Mon, 03 Dec 2007) > New Revision: 534 > > Added: > LinuxBIOSv3/include/northbridgelib.h > LinuxBIOSv3/lib/northbridgelib.c Reading the code this seems to belong to device/pci_device.c and device/device_util.c rather than in lib/? Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

[LinuxBIOS] Abit KN9 Ultra - output of 'lspci -tvnn', 'superiotool -dV' and 'flashrom -V'
by Dawn Light 04 Dec '07

04 Dec '07

-[0000:00]-+-00.0 nVidia Corporation MCP55 Memory Controller [10de:0369] +-01.0 nVidia Corporation MCP55 LPC Bridge [10de:0362] +-01.1 nVidia Corporation MCP55 SMBus [10de:0368] +-02.0 nVidia Corporation MCP55 USB Controller [10de:036c] +-02.1 nVidia Corporation MCP55 USB Controller [10de:036d] +-04.0 nVidia Corporation MCP55 IDE [10de:036e] +-05.0 nVidia Corporation MCP55 SATA Controller [10de:037f] +-05.1 nVidia Corporation MCP55 SATA Controller [10de:037f] +-05.2 nVidia Corporation MCP55 SATA Controller [10de:037f] +-06.0-[0000:01]----08.0 Texas Instruments TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) [104c:8023] +-06.1 nVidia Corporation MCP55 High Definition Audio [10de:0371] +-08.0 nVidia Corporation MCP55 Ethernet [10de:0373] +-09.0 nVidia Corporation MCP55 Ethernet [10de:0373] +-0c.0-[0000:02]-- +-0d.0-[0000:03]-- +-0e.0-[0000:04]-- +-0f.0-[0000:05]----00.0 nVidia Corporation G70 [GeForce 7600 GT] [10de:0391] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] \-18.3 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] ########################## superiotool r2922 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x8400, id=0x6388 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x8863, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 88 63 ff 00 84 00 00 ff 50 00 7c c0 08 01 00 ff def 88 MM ff 00 MM 00 MM RR 50 04 00 RR 00 21 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 00 00 00 04 38 def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 00 00 00 00 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 00 00 00 00 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 80 def 01 00 60 00 64 01 0c 83 LDN 0x06 (Serial flash interface) idx 30 62 63 val 00 ff ff def 00 00 00 LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f7 val 01 00 00 00 00 00 fd 00 00 02 ff ff ff 00 def 00 02 01 03 30 09 ff 00 00 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED) idx 30 f5 f6 f7 val 00 ff 00 ff def 00 00 00 00 LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED) idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7 val 00 ff ff ff ff ff ff ff ff ff 00 ff ff ff ff def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 f2 f3 f4 f6 f7 val 00 00 00 00 c0 00 00 00 0c 00 09 7c 00 00 00 00 def 00 00 01 00 ff 08 00 RR 00 00 RR 7c 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 val 01 02 90 00 c1 3f def 00 00 00 00 c1 00 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff ########################## Calibrating delay loop... 758M loops per second. OK. No LinuxBIOS table found. Found chipset "NVIDIA MCP55", enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0x49, id2 0x4d Probing for Am29LV040B, 512 KB probe_29f040b: id1 0x49, id2 0x4d Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for At29C040A, 512 KB probe_jedec: id1 0x9d, id2 0x6e Probing for At29C020, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0x49, id2 0x44 Probing for MX29F002, 256 KB probe_29f002: id1 0x9d, id2 0x6e Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST28SF040A, 512 KB probe_28sf040: id1 0x49, id2 0x4d Probing for SST39SF010A, 128 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST39SF020A, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST39SF040, 512 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST39VF020, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF040B, 512 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF040, 512 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF020A, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0x9d, id2 0x6e Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0x49, id2 0x4d Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0x9d, id2 0x6e Probing for Pm49FL004, 512 KB probe_jedec: id1 0x9d, id2 0x6e Pm49FL004 found at physical address 0xfff80000. Flash part is Pm49FL004 (512 KB). No operations were specified. -- Dawn Light שחר אור 050-7966664

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coreboot December 2007