coreboot November 2007

coreboot@coreboot.org

75 participants
397 discussions

[LinuxBIOS] Link error on Fedora 8
by Ed Swierk 21 Nov '07

21 Nov '07

I'm having trouble building emulation/qemu-i386 in the latest LinuxBIOSv2 snapshot on Fedora 8 (GNU ld version 2.17.50.0.18-1 20070731, gcc version 4.1.2 20070925 (Red Hat 4.1.2-33). First, ld segfaults unless I apply the attached patch. That one was fun to figure out :-) Now, ld is unable to find a home for the ".id" section: echo '/*ldoptions*/' > ldscript.ld; cat ldoptions >> ldscript.ld ; for file in /home/eswierk/LinuxBIOSv2-2976/src/arch/i386/init/ldscript.lb /home/eswierk/LinuxBIOSv2-2976/src//c\ pu/x86/16bit/entry16.lds /home/eswierk/LinuxBIOSv2-2976/src//cpu/x86/32bit/entry32.lds /home/eswierk/LinuxBIOSv2-2976/src//cpu/x86/16bit/reset16.lds /home/eswierk/LinuxBIOSv2-2976\ /src//arch/i386/lib/id.lds ; do echo /\* $file \*/ >> ldscript.ld; cat $file >> ldscript.ld ; done gcc -m32 -nostdlib -nostartfiles -static -o linuxbios -T ldscript.ld crt0.o /usr/bin/ld: linuxbios: section `.id' can't be allocated in segment 2 /usr/bin/ld: final link failed: Bad value collect2: ld returned 1 exit status Any clues about this one? The ldscript.ld is attached. --Ed

2 1

[LinuxBIOS] Setup of Memory Controller
by Linux Bios 20 Nov '07

20 Nov '07

I'm a student researching digital forensics and acquisition of memory using hardware. I had a few ideas I'm hoping is ok that I run by everyone here. I have Tyan s2891 motherboard with one dual core Opteron and an fpga in the second cpu socket. I would like to research two things that I would like to do in a customization to my own linuxbios setup. 1. Disable the Opteron's integrated memory controller and use my own fpga memory controller in the second cpu socket on the motherboard. In this case I would like CPU read/writes to memory to follow a path out of Northbridge to my memory controller in the second CPU socket. (I'm not worried about latency problems at this point.) The FPGA Im talking about (actually DRC computers setup) is seen the to the OS as another PCI device and not another CPU node. So what Im theorizing that needs to be done is disable the integrated memory controller in northbridge in the register called dramconfigreglo[24]=disinrcvrs (In AMD developer documentation) and change the DRAM address map to point to the HT link where my memory controller is. -or- 2. Continue to use the Opterons integrated memory controller and send a copy of all memory writes (not reads) to my own fpga memory controller in the second cpu socket. I dont see anywhere in the developer documentation in which there is a register setting to realize this so Im not sure if this is possible in AMDs direct connect architecture. Thanks to all for taking your time out to read this as well as your ideas and direction! -nate --------------------------------- Be a better pen pal. Text or chat with friends inside Yahoo! Mail. See how.

6 9

[LinuxBIOS] Could original VGA BIOS be responsible for long timeout before LinuxBIOS kicks in?
by Coquelicot 20 Nov '07

20 Nov '07

Hi all, what can be responsible for long delay before starting LinuxBIOS? I have it on VIA EPIA M-II with LB preppended by original VGA bios extracted from the original BIOS. The delay is ~20 seconds before I get first message on serial console (..."In auto.c:main()" messages). Correct me if I am wrong: do I need VGA BIOS at all? I want my booting Linux kernel to use framebuffer but I guess that original VGA BIOS is not really needed for that, just to be able to "control" LB/FILO from the local console, right? -- Coquelicot

1 0

[LinuxBIOS] [PATCH] v3: post_code.h / console.h fixup
by Uwe Hermann 20 Nov '07

20 Nov '07

See patch. We could also just #include post_code.h everywhere explicitly, but I think that's a bit of an overkill as we use console.h everywhere already. Note: There are build problems in v3 currently which are being investigated (and this patch won't fix them). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[LinuxBIOS] r513 - in LinuxBIOSv3: arch/x86 include mainboard/adl/msm800sev mainboard/amd/norwich mainboard/artecgroup/dbe61 northbridge/amd/geodelx southbridge/amd/cs5536
by svn＠openbios.org 20 Nov '07

20 Nov '07

Author: uwe Date: 2007-11-20 20:06:03 +0100 (Tue, 20 Nov 2007) New Revision: 513 Modified: LinuxBIOSv3/arch/x86/stage1.c LinuxBIOSv3/include/console.h LinuxBIOSv3/include/post_code.h LinuxBIOSv3/mainboard/adl/msm800sev/initram.c LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c LinuxBIOSv3/mainboard/amd/norwich/initram.c LinuxBIOSv3/mainboard/amd/norwich/stage1.c LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c LinuxBIOSv3/northbridge/amd/geodelx/raminit.c LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c Log: Only post_code.h should have the prototype for post_code() from post_code.c (thus drop it from console.h). Instead, have console.h #include post_code.h and drop other explicit #includes of post_code.h in the code; console.h is already included in pretty much every file. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/arch/x86/stage1.c 2007-11-20 19:06:03 UTC (rev 513) @@ -26,7 +26,6 @@ #include <tables.h> #include <lib.h> #include <mc146818rtc.h> -#include <post_code.h> /* ah, well, what a mess! This is a hard code. FIX ME but how? * By getting rid of ELF ... Modified: LinuxBIOSv3/include/console.h =================================================================== --- LinuxBIOSv3/include/console.h 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/include/console.h 2007-11-20 19:06:03 UTC (rev 513) @@ -19,6 +19,7 @@ #include <types.h> #include <shared.h> /* We share symbols from stage 0 */ +#include <post_code.h> #define BIOS_EMERG 0 /* system is unusable */ #define BIOS_ALERT 1 /* action must be taken immediately */ @@ -35,7 +36,6 @@ void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); -void post_code(u8 value); void die(const char *msg); struct console_driver { Modified: LinuxBIOSv3/include/post_code.h =================================================================== --- LinuxBIOSv3/include/post_code.h 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/include/post_code.h 2007-11-20 19:06:03 UTC (rev 513) @@ -18,9 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef POST_CODE_H +#define POST_CODE_H + #include <shared.h> SHARED(post_code, void, u8 value); #define POST_START_OF_MAIN 0x01 +#endif /* POST_CODE_H */ Modified: LinuxBIOSv3/mainboard/adl/msm800sev/initram.c =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/initram.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/mainboard/adl/msm800sev/initram.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/device.h> #include <device/pci.h> #include <io.h> Modified: LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/device.h> #include <device/pci.h> #include <io.h> Modified: LinuxBIOSv3/mainboard/amd/norwich/initram.c =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/initram.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/mainboard/amd/norwich/initram.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/device.h> #include <device/pci.h> #include <string.h> Modified: LinuxBIOSv3/mainboard/amd/norwich/stage1.c =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/stage1.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/mainboard/amd/norwich/stage1.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/device.h> #include <device/pci.h> #include <string.h> Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/initram.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/device.h> #include <device/pci.h> #include <string.h> Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c =================================================================== --- LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/stage1.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/device.h> #include <device/pci.h> #include <string.h> Modified: LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/northbridge/amd/geodelx/geodelxinit.c 2007-11-20 19:06:03 UTC (rev 513) @@ -20,7 +20,6 @@ #include <types.h> #include <console.h> -#include <post_code.h> #include <msr.h> #include <cpu.h> #include <amd_geodelx.h> Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c =================================================================== --- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2007-11-20 19:06:03 UTC (rev 513) @@ -21,7 +21,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <msr.h> #include <spd.h> #include <io.h> Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c 2007-11-20 18:20:53 UTC (rev 512) +++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536.c 2007-11-20 19:06:03 UTC (rev 513) @@ -20,7 +20,6 @@ #include <types.h> #include <lib.h> #include <console.h> -#include <post_code.h> #include <device/pci.h> #include <msr.h> #include <amd_geodelx.h>

1 0

[LinuxBIOS] [PATCH 1/2] v3: improve printk documentation
by Carl-Daniel Hailfinger 20 Nov '07

20 Nov '07

Improve printk documentation to match code realities. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- Index: LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c (Revision 509) +++ LinuxBIOSv3/mainboard/adl/msm800sev/stage1.c (Arbeitskopie) @@ -36,6 +36,8 @@ #define SERIAL_DEV W83627HF_SP1 #define SERIAL_IOBASE 0x3f8 +/* printk will not yet output anything */ + void hardware_stage1(void) { void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); @@ -51,5 +53,4 @@ */ cs5536_disable_internal_uart(); w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); - printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__); } Index: LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c (Revision 509) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/stage1.c (Arbeitskopie) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* no printk allowed until hardware is ready; hardware is ready */ +/* printk will not yet output anything */ /** * start up hardware needed for stage1 Index: LinuxBIOSv3/lib/stage2.c =================================================================== --- LinuxBIOSv3/lib/stage2.c (Revision 509) +++ LinuxBIOSv3/lib/stage2.c (Arbeitskopie) @@ -37,7 +37,8 @@ * * Device Enumeration: in the dev_enumerate() phase. * - * TODO: Check whether this documentation is still correct. Improve it. + * TODO: + * - Check whether this documentation is still correct. Improve it. */ int stage2(void) { @@ -54,7 +55,13 @@ post_code(0x20); - /* TODO: Explain why we use printk here although it is impossible */ + /* TODO: Explain why we use printk here although it is claimed to be + * impossible according to the documentation. The "has to be done + * before printk can be used" comment below seems to suggest the same. + * However, we already enable serial in arch/x86/stage1.c:stage1_main() + * when we call hardware_stage1(); uart_init(); console_init(); + * Why test the console again if it already is tested in stage 1? + */ printk(BIOS_NOTICE, console_test); dev_init(); Index: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c (Revision 509) +++ LinuxBIOSv3/arch/x86/stage1.c (Arbeitskopie) @@ -102,14 +102,17 @@ } // We have cache as ram running and can start executing code in C. - // hardware_stage1(); // uart_init(); // initialize serial port - console_init(); // print banner + /* Exactly from now on we can use printk to the serial port. + * Celebrate this by printing a LB banner. + */ + console_init(); + if (bist!=0) { printk(BIOS_INFO, "BIST FAILED: %08x", bist); die("");

4 7

[LinuxBIOS] r512 - in LinuxBIOSv3: device lib
by svn＠openbios.org 20 Nov '07

20 Nov '07

Author: hailfinger Date: 2007-11-20 19:20:53 +0100 (Tue, 20 Nov 2007) New Revision: 512 Modified: LinuxBIOSv3/device/device.c LinuxBIOSv3/lib/stage2.c Log: Cleanup printk usage and documentation. Drop the second banner as it was an artifact from the time when we needed stage2 phase 1 code to make printk work. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/device/device.c =================================================================== --- LinuxBIOSv3/device/device.c 2007-11-17 15:28:02 UTC (rev 511) +++ LinuxBIOSv3/device/device.c 2007-11-20 18:20:53 UTC (rev 512) @@ -692,14 +692,14 @@ * * Starting at the first device on the global device link list, * walk the list and call the device's phase1() method to do very - * early setup. phase1 should only be used for devices that CAN NOT use - * printk(), or that are part of making printk() work. + * early setup. */ void dev_phase1(void) { struct device *dev; post_code(0x31); + printk(BIOS_DEBUG, "Phase 1: Very early setup...\n"); for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->phase1_set_device_operations) { dev->ops->phase1_set_device_operations(dev); @@ -715,7 +715,7 @@ * * Starting at the first device on the global device link list, * walk the list and call the device's phase2() method to do - * early setup. You can use printk() in phase 2 methods. + * early setup. */ void dev_phase2(void) { @@ -729,7 +729,7 @@ printk(BIOS_SPEW, "Calling phase2 phase2_setup_scan_bus..."); dev->ops->phase2_setup_scan_bus(dev); - printk(BIOS_SPEW, " DONE"); + printk(BIOS_SPEW, " done"); } printk(BIOS_SPEW, "\n"); } Modified: LinuxBIOSv3/lib/stage2.c =================================================================== --- LinuxBIOSv3/lib/stage2.c 2007-11-17 15:28:02 UTC (rev 511) +++ LinuxBIOSv3/lib/stage2.c 2007-11-20 18:20:53 UTC (rev 512) @@ -34,6 +34,7 @@ * LinuxBIOS is divided into pre-DRAM part and DRAM part. The stages before * this part are stage 0 and stage 1. This part contains stage 2, which * consists of phases 1 through 6. + * printk has been set up in stage 1 and is working. * * Device Enumeration: in the dev_enumerate() phase. * @@ -45,29 +46,11 @@ /* TODO: Add comment. */ void show_all_devs(void); - static const char console_test[] = - "\n\nLinuxBIOS-" - LINUXBIOS_VERSION - LINUXBIOS_EXTRA_VERSION - " " - LINUXBIOS_BUILD - " booting...\n"; - post_code(0x20); - - /* TODO: Explain why we use printk here although it is claimed to be - * impossible according to the documentation. The "has to be done - * before printk can be used" comment below seems to suggest the same. - * However, we already enable serial in arch/x86/stage1.c:stage1_main() - * when we call hardware_stage1(); uart_init(); console_init(); - * Why test the console again if it already is tested in stage 1? - */ - printk(BIOS_NOTICE, console_test); - dev_init(); - /* Console init, also ANYTHING that has to be done - * before printk can be used. + /* Phase 1 was console init and making printk work. Both functions are + * now performed by stage 1 code. Phase 1 is now without purpose. */ post_code(0x30); dev_phase1();

1 0

Re: [LinuxBIOS] GIGABYTE GA-2761GXDK
by Morgan Tsai /SiS 20 Nov '07

20 Nov '07

Change Log: 1. Fix pirq routing table setting for GA-2761GXDK. 2. Southbridge PCIe slots are working correctly now. 3. Disable keyboard & mouse ports for GA-2761GXDK. Signed-off-by: Morgan Tsai <my_tsai(a)sis.com>

3 2

[LinuxBIOS] r2976 build service
by LinuxBIOS information 20 Nov '07

20 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "hailfinger" checked in revision 2976 to the LinuxBIOS source repository and caused the following changes: Change Log: 1. Fix pirq routing table setting for GA-2761GXDK. 2. Southbridge PCIe slots are working correctly now. 3. Disable keyboard & mouse ports for GA-2761GXDK. Signed-off-by: Morgan Tsai <my_tsai(a)sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2976&device=serengeti_che… Compilation of asus:a8v-e_se is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2976&device=a8v-e_se&vend… Compilation of iwill:dk8_htx is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2976&device=dk8_htx&vendo… Compilation of msi:ms9185 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2976&device=ms9185&vendor… Compilation of msi:ms9282 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2976&device=ms9282&vendor… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2976&device=h8dmr&vendor=… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2976 - in trunk/LinuxBIOSv2/src: mainboard/gigabyte/ga_2761gxdk southbridge/sis/sis966
by svn＠openbios.org 20 Nov '07

20 Nov '07

Author: hailfinger Date: 2007-11-20 15:11:24 +0100 (Tue, 20 Nov 2007) New Revision: 2976 Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c Log: 1. Fix pirq routing table setting for GA-2761GXDK. 2. Southbridge PCIe slots are working correctly now. 3. Disable keyboard & mouse ports for GA-2761GXDK. Signed-off-by: Morgan Tsai <my_tsai(a)sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2007-11-17 17:13:52 UTC (rev 2975) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2007-11-20 14:11:24 UTC (rev 2976) @@ -269,12 +269,12 @@ io 0x62 = 0x230 irq 0x70 = 9 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 end - device pnp 2e.6 on # Mouse + device pnp 2e.6 off # Mouse irq 0x70 = 12 end device pnp 2e.8 off # MIDI Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c 2007-11-17 17:13:52 UTC (rev 2975) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c 2007-11-20 14:11:24 UTC (rev 2976) @@ -75,7 +75,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...\n", addr); + printk_info("Writing IRQ routing tables to 0x%x...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -83,8 +83,8 @@ pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sis966[0]; - pirq->rtr_devfn = ((sbdn+6)<<3)|0; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(2, 0); pirq->exclusive_irqs = 0; @@ -98,81 +98,73 @@ pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; + write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + { device_t dev; dev = dev_find_slot(0, PCI_DEVFN(2,0)); - if (dev) { - + if (dev) { /* initialize PCI interupts - these assignments depend on the PCB routing of PINTA-D PINTA = IRQ10 PINTB = IRQ11 - PINTC = IRQ5 - PINTD = IRQ5 + PINTC = NA + PINTD = IRQ10 PINTE = IRQ11 PINTF = IRQ5 - PINTG = IRQ10 - PINTH = IRQ5 + PINTG = NA + PINTH = IRQ7 */ int i; uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63}; - uint8_t irq[8]={0x0A,0X0B,0X05,0X05,0X0B,0X05,0X0A,0X0A}; + uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07}; for(i=0;i<8;i++) pci_write_config8(dev, reg[i], irq[i]); - } + } // endif printk_debug("Setting Onboard SiS Southbridge\n"); - /* - * Non-layout for GA-2761GX - * dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE) pci_write_config8(dev, 0x3C, 0x0A); - */ - dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1 pci_write_config8(dev, 0x3C, 0x0B); dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1 pci_write_config8(dev, 0x3C, 0x05); dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0 - pci_write_config8(dev, 0x3C, 0x0A); + pci_write_config8(dev, 0x3C, 0x07); dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN) - pci_write_config8(dev, 0x3C, 0x05); + pci_write_config8(dev, 0x3C, 0x0A); dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA) pci_write_config8(dev, 0x3C, 0x0B); dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E pci_write_config8(dev, 0x3C, 0x0A); dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E pci_write_config8(dev, 0x3C, 0x0A); - - /* - * Non-layout for GA-2761GX - * dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia pci_write_config8(dev, 0x3C, 0x05); - */ } -//pci bridge - write_pirq_info(pirq_info, bus_sis966[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; + printk_debug("pirq routing table, size=%d\n", pirq->size); + for (i = 0; i < pirq->size; i+=4) + printk_debug("%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]); - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk_info("done.\n"); - return (unsigned long) pirq_info; } Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c 2007-11-17 17:13:52 UTC (rev 2975) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c 2007-11-20 14:11:24 UTC (rev 2976) @@ -151,7 +151,7 @@ {0x45, 0x00 ,0xFF}, //Reg 0x45 {0x46, 0x00 ,0x90}, //Reg 0x46 {0x47, 0x00 ,0xA0}, //Reg 0x47 -//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable +//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable {0x4E, 0x00 ,0x00}, //Reg 0x4E {0x4F, 0x00 ,0x02}, //Reg 0x4F {0x5B, 0x00 ,0x44}, //Reg 0x5B @@ -195,7 +195,7 @@ }; static const uint8_t SiS_NBAGP_init[34][3]={ -{0xCF, 0xDF, 0x00}, //HT issue +{0xCF, 0xDF, 0x00}, //HT issue {0x06, 0xDF, 0x20}, {0x1E, 0xDF, 0x20}, {0x50, 0x00, 0x02}, @@ -228,7 +228,7 @@ {0xBF, 0xF9, 0x06}, {0xBA, 0x00, 0x61}, {0xBD, 0x7F, 0x80}, -{0x00, 0x00, 0x00} //End of table +{0x00, 0x00, 0x00} //End of table }; static const uint8_t SiS_ACPI_2_init[56][3]={ @@ -298,7 +298,7 @@ {0x2E, 0x00, 0x83}, {0x2F, 0x00, 0x11}, {0x90, 0x00, 0x40}, -{0x91, 0x00, 0x00}, // set mode +{0x91, 0x00, 0x00}, // set mode {0x50, 0x00, 0xA2}, {0x52, 0x00, 0xA2}, {0x55, 0x00, 0x96}, @@ -313,7 +313,7 @@ {0x85, 0x00, 0xB3}, {0x86, 0x00, 0x72}, {0x87, 0x00, 0x40}, -{0x88, 0x00, 0xDE}, // after set mode +{0x88, 0x00, 0xDE}, // after set mode {0x89, 0x00, 0xB3}, {0x8A, 0x00, 0x72}, {0x8B, 0x00, 0x40}, @@ -334,7 +334,7 @@ {0xA1, 0x00, 0x15}, {0xA2, 0x00, 0x15}, {0xA3, 0x00, 0x15}, -{0x00, 0x00, 0x00} //End of table +{0x00, 0x00, 0x00} //End of table }; /* In => Share Memory size @@ -411,7 +411,7 @@ i++; }; // ========================== NBPCIE ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit temp8 = pci_read_config8(dev, 0x4C); GUI_En = temp8 & 0x10; pci_write_config8(dev, 0x4C, temp8 & (!0x10)); @@ -425,19 +425,19 @@ pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8); i++; }; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit temp8 = pci_read_config8(dev, 0x4C); pci_write_config8(dev, 0x4C, temp8 | GUI_En); - return; + return; } void sis_init_stage2(void) { - device_t dev; - msr_t msr; + device_t dev; + msr_t msr; int i; uint8_t temp8; uint16_t temp16; @@ -509,19 +509,36 @@ // ========================== Misc ============================= printk_debug("Init Misc -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); - // PCI Device Enable - pci_write_config8(dev, 0x7C, 0x03); // bit0=0 : enable audio controller(), bit1=1 : disable modem - pci_write_config8(dev, 0x76, pci_read_config8(dev, 0x76)|0x30); // SM bus enable, PCIEXP Controller 1 and 2 disable + + /* R77h Internal PCI Device Enable 1 (Power On Value = 0h) + * bit5 : USB Emulation (1=enable) + * bit3 : Internal Keyboard Controller Port Access Control enable (1=enable) + * bit2 : Reserved + * bit1 : Mask USB A20M# Event (1:K8, 0:P4/K7) + */ + pci_write_config8(dev, 0x77, 0x2E); + + /* R7Ch Internal PCI Device Enable 2 (Power On Value = 0h) + * bit4 : SATA Controller Enable (0=enable) + * bit3 : IDE Controller Enable (0=enable) + * bit2 : MAC Controller Enable (0=enable) + * bit1 : MODEM Controller Enable (1=disable) + * bit0 : AC97 Controller Enable (1=disable) + */ + pci_write_config8(dev, 0x7C, 0x03); + + /* R7Eh Enable Azalia (Power On Value = 08h) + * bit3 : Azalia Controller Enable (0=enable) + */ pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable - temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97 outb(temp8, 0x878); // ACPI select AC97 or HDA controller printk_debug("Audio select %x\n",inb(0x878)); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0); - if(!dev){ + + if (!dev) print_debug("SiS 1183 does not exist !!"); - } // SATA Set Mode pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);

1 0

← Newer
1
...
17
18
19
20
21
22
23
...
40
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2007